Figure 20. 8Pso Functional Block Diagram - Alcatel 1850 TSS-320 Technical Handbook

I2C I/F
#1 SFP
#8 SFP
O/E Rx
O/E Tx
LOS
Shutdown SFP
LFAIL
QDRII
SRAM
+3.3V
VOLTAGE
+2.5V
MONITOR
+1.8V
+1.2V
I2C I/F
STATUS
LED
Remote
Inventory
Alcatel 1850 TSS-320 Rel.1.1
58/84 8DG 07734 CAAA Edition 01
155.52 (or 622.08) Mbit/s
155.52 (or 622.08) Mbit/s
RST
MST
8
SA
8
8
HVC
FERMAT
PS FAIL
XO
38.88 MHZ
KYRA
Local SPI
ISPB
Local SPI
CK ISPB

Figure 20. 8PSO Functional block diagram

VCXO
622 MHz
PhDect
8
8
Aligner/
FAW ins.
Scrambler/
descrambler
16x622 Mb/s
Freq. Offset
16x622 Mb/s
Adaptation
EUCLIDE
Bkp OH
and
PhDect
Prot. CH
FEC/DEFEC
16x622 Mb/s
+
EPS Protection
SLOT Id
EN T1
GTL EN
Local SPI
FPGA Conf. I/F
GOBLIN
HVC
4G
FLASH
8
PRES SFP
+3.3V
+2.5V
DC/DC
+1.5V
+1.2V
GTPL
I/F
GTL EN
Zero
Delay
Buffer
38.88 MHZ
T0
SYNC
SYNC
2MHz
CBT
T1
Bus
Switch
EN T1
CK ISPB
ISPB
SLOT Id
VCXO
777.6 MHz
4x3.11 Gb/s
To/From
MT320_A
4x3.11 Gb/s
To/From
MT320_B
SLOT Id
SPI A/B
HVC ENA
GTPL
HVC Bus
I/F
(to/from SLC)
V3A
3.3VS
OR V3B
3.3V
CMISS
(to POW320 A/B)
BATT. B
OR
BATT. A
(to/from SLC)
SCA ACT (from SLCA)
BCLK A (from SLC A)
BCLK B (from SLC B)
Technical Handbook SDH
Units Description