3.3.2.1 Sink Side (Signal flow from Optical Line to HPC Matrix)
O/E RX:
it performs the conversion from an optical STM-16 signal to an equivalent electrical stream, by using
differential signaling so as defined by the SFP MSA specification.
CDR:
a Clock and Data recovery device performs 3R-regeneration on the incoming serial data stream.
Aligner:
this function is integrated in EUCLIDE Asic, it recovers frame alignment, detects OOF events.
Descrambler + B1/B2 Calculation:
it descrambles the incoming signal, performs BIP-8 (B1) and BIP-384 (B2) calculation.
Frequency Offset Adaptation:
it eliminates the frame alignment word from the incoming signal, performs rate adaptation to the on-
board local clock by means of negative stuffing and provides the data together with control and
synchronism bytes, via a double SFI4.1-like interface, to FERMAT Fpga.
RST*Sk (partial RSn_TT_Sk):
•
it recovers frame alignment, by detecting the synchronism of J0 (inserted by EUCLIDE)
•
it extracts OOF events (detected by EUCLIDE) and detects LOF alarm.
•
it performs regenerator section trace recovery and mismatch detection (J0), BIP-8 (B1) errored
blocks count, TSF insertion (on LOS, LOF or TIM detection)
•
it provides RS data communication (DCCR) extraction (D1-D3).
•
It provides RS OverHead bytes extraction (E1, F1...)
MST Sk (MSn_TT_Sk):
it performs BIP-384 (B2) errored blocks count, MS-REI recovery, K1 and K2 extraction and MS-RDI/
MS-AIS detection, MS data communication (DCCM) extraction (D4-D12) and MS OverHead
auxiliary bytes extraction (E2,....)
MSA Sk (MSn/Sn_A_Sk):
performs AU4's pointer processing, LOP and AIS detection, pointer justification (including AU4
Concatenation handling capability)
HVC Before Matrix (HTCM/HTCTsk, HPOM/HSUTsk, HSUTso, HTCTso):
performs path overhead processing such as: J1 and G1 recovery, C2 signal label monitoring, UNEQ
and VC-AIS detection, BIP-8 (B3) errored block count, N1 extraction, BIP-8 (B3) compensation.
Backpanel Framer:
receives the incoming data stream on a 16-bit differential LVDS interface, performs frame alignment
and generates a proprietary frame (Backplane Frame Format) for backpanel links (Rate Adaptation,
Slicing, insertion of OverHead and Protection channels generated by Fermat, FAW and J0Link Label
insertion).
FEC+Scrambler:
performs the FEC redundancy calculation and insertion (The Forward Error Correction code used
is a Reed-Solomon code: RS (243, 241)) and scrambling.
Technical Handbook SDH
Units Description
Alcatel 1850 TSS-320 Rel.1.1
8DG 07734 CAAA Edition 01
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