Register Definition; Fpga Reset Register (0X00); Control Register (0X02) - Sundance Spas SMT351 User Manual

Register definition

FPGA reset register (0x00)

Writing to this address will reset the DDR SDRAM memory control. You must wait
one second after writing to this register to allow the reset to complete.

Control register (0x02)

15 14-5
LED -
R/W, 0 -
Field Description (flags are active when 1)
CLR Writing '1' to this register will reset both input and output SHBs.
RDBKEN Read back enable. When this bit is set read back of memory is
enabled and SMT351 starts outputting data.
STARTACQ When this bit is set to 1, data coming from SHB A are stored in DDR
SDRAM.
LED LED register. Writing '1' to this register will light LED 4.
4 3
START -
ACQ
R/W, 0 -
2 1 0
- RDBK CLR
EN SHB
- W,1 R/W,0