Figure 6: Ttl I/Os (Jp2) Pinout - Sundance Spas SMT351 User Manual

Version 1.1

Figure 6: TTL I/Os (JP2) pinout

The following table shows JP2 mapping to the FPGA:
Signal name FPGA pin
number
TTL0 AC10
TTL1 AD10
TTL2 AC11
TTL3 AD11
Page 22 of 24 SMT351 User Manual