Tektronix Option 10 Service Manual page 168

DMM Option-Theory of Operation
24X5B12467B Options Service
loads shift register U5240 and resets counter U5242. The writes to address 7F84, making U5241 pin 11 LO. This
counter then outputs eight clock pulses at one-half the sets U5222A through U5252C and U5232C1 ending the
microprocessor clock (E) rate. The eight pulses shift the delay.
word through U5240.
The word (DATA) is sent to the Digital Control circuitry
COUNTERS. Timer U5272 takes all measurements. The
through ~ 5 2 4 2 8 , ~ 5 2 3 0 ~ ~ and ~ 5 2 3 0 . The DATA is only
timer contains three programmable counters. Except for
sent when the shift register is not being loaded and the
Continuity and Some Diagnostics modes, the timer is
counter is not at its maximum count. The same CLK used
programmed as follows:
to shift the word out of the shift register is sent to the
Digital Control circuitry through U5230B and T5220.
Counter 1 counts VIF clock pulses. Counting starts
when the counter's gate goes LO. When the gate goes
HI, counting stops and the measurement-complete bit
Before sending each group of three words, part of
is set.
- .
another word is sent. The sending of this word disables
the VIF output clock which also uses the data path
Counter 2 counts the most-significant bits of the
through T5230.
10-MHz clock over the same interval as Counter 1.
Counter 3 counts the internal E clock. The counter
Transformers T5230A and T5230B isolate the Digital
produces the 0.1 -s measurement interval, outputting a
Counter, Processor Interface, and Extended Front Panel
positive 0.1-s pulse when its gate goes LO.
circuitry from the floating ground and high input potentials
associated with the rest of the circuitry.
Counting does not start
until after the Delay
Generator's delay has ended. When the delay ends,
DELAY GENERATOR. The Delay Generator delays the
Counter 3 starts and its output goes HI. The first VIF
start of a measurement. The delay starts after the clock after the output of Counter 3 goes HI starts
Register Control circuitry has loaded the Digital Control Counters 1 and 2. The first VIF clock after Counter 3 goes
registers. This delay allows the measurement path (relays LO (0.1-s measurement interval ends) stops Counters 1
and FET switches) to settle before a measurement and
2.
When Counter 1 stops (its gate goes HI), Counters
is taken.
1 and 2 are read and the measurement calculated (see
Figure 4-4). Three of these measurements are required to
Whenever counter U5224 is not at its maximum count,
reset, or counting, counter U5231 and flip-flop U5222A are
reset. While the flip-flop is reset, counters U5272 and
U5274 do not count. When the Digital Control register (see
Diagram 29) has been loaded, U5224 will be at its max-
imum count. The MAXIMIN output (U5224, pin 2) goes HI,
removing the reset hold it had on both U5231 and
U5222A. This is the start of the delay. Counter U5231
then counts the 25-kHz clock (5.5 V ac) at U5231 pin 10.
About 50 ms after the start of the delay, pin 15 of
U5231 goes HI. If DATA (CO) was HI, U5222A sets, ending
the delay. If, however, the option is in its 20-Mil range,
DATA will be LO, keeping U5222A reset. In this case, the
delay lasts about 400 ms. The delay ends when pin 3 of
U5231 goes HI, stopping counter U5231 through CR5211,
and setting U5222A through U5252A1 U5232C, and
U5252C. In both cases, counter U5272 starts counting VIF
pulses once U5222A is set.
If the DMM mode is changed by pushing a front panel
switch, the microprocessor does not wait for the delay to
end. When the mode is changed, the microprocessor
display a reading; the unknown measurement measures
the input signal, the offset measurement measures zero
volts, and the reference measurement measures the
-0.2 V or the -2 V reference. After all three measure-
ments are made, the measurement to be displayed is cal-
culated and then displayed.
At the start of the delay period, pin 2 of U5274A, pin 2
of U5272, and pin 5 of U5272 all go HI. This resets the
least-significant bits, from the previous measurement, of
the 10-MHz counter (U5274A) and prevents Counters 2
and 3 from counting. When Counter 3 is not counting, its
output (U5272, pin 6) is LO.
When the delay ends (pin 6 of U5222A goes LO),
DELAY goes LO enabling Counter 3. When Counter 3 is
enabled, it starts counting and its output (U5272, pin 6)
goes HI. This HI, at pin 12 of U52738, allows U5273B to
set when the next V/F clock arrives (at pin 11 of U5273B).
When U5273B is set, Counter 1 and U5273A are both
enabled. Counter 1 starts counting the VIF clocks, and the
10-MHz counter (U5273A1 U5274A1 and Counter 2) starts
counting the B1 OMHZ clocks.