Internal Trigger Switching Logic; Z-Axi Am Plifier - Tektronix 2213 Instruction Manual

Theory of Operation—2213 Service
When S315 is set to A LT , a HI is placed on both the Set
and Reset inputs o f U317A. Flip-flop U317A w ill transfer
the logic level on the D input (pin 2) to the Q output
(pin 5) on each clock-pulse rising edge. Pin 1 o f NAND-gate
U310A is held HI by th e Chop Oscillator output, and pin 2
follows the A lt Sync signal produced by the H oldoff
circuitry in the A Sweep Generator (Diagram 5). The
output o f U310A (pin 3) is therefore an inverted A lt Sync
pulse. The signal on the D input o f U317A (pin 2) follows
the logic level set by the Q output pin. As each clock pulse
occurs, the states o f the Q and Q outputs reverse (toggle),
enabling Channel 1 and Channel 2 Diode Gates alternately
w ith each sweep.
CHOP OSCILLATOR. Setting S315 to CHOP enables
the Chop Oscillator and the Chop Blanking circuit. Pins C
and D o f S315 are connected to place a LO logic level on
the Set input (pin 10) o f U317B. The Q output of U317B is
set HI and the Chop Oscillator is allowed to run. A HI
level is present on U310D pin 13 due to C308 being
charged to the HI level on U310D pin 11. When pin 12 of
U310D also goes HI, the output of U310D goes LO.
Capacitor C308 now must discharge to the new dc level.
As soon as the charge o f C308 reaches the LO threshold
level of U310D, the output at pin 11 switches HI again and
C308 charges toward the HI logic level (see Figure 3-4).
When the HI switching threshold level is reached, the
output of U301D changes state to LO again. This cycle
continues at about 500 kHz to produce both the Chop
Clock and the Chop Blank signals.
The Chop signal is gated through NAND-gate U310C
and applied to U310A pin 1. The A lt Sync pulse on U310A
pin 2 is HI (except during holdoff time) so the output of
U310A pin 3 is the inverted Chop Oscillator signal on
pin 1. This signal is applied to the Clock Input (pin 3) o f
U317A to drive the Channel Switching circuitry. Since flip-
flop U317A clocks w ith rising edges only, the frequency o f
the chopped channel switching is about 250 kHz.
The signal output from U310C pin 8 is also fed to the
Chop Blanking circuit. Capacitor C311 and resistors R310
and R311 form a differentiating circuit that produces
positive and negative short-duration pulses when the Chop
Oscillator signal changes levels.
The dc level at U310B pins 4 and 5 is set slightly above
the HI switching threshold logic by a voltage divider con­
sisting o f R310 and R311. Positive pulses from C311 con­
tinue to hold U310B above the threshold level, so the
output remains LO. Negative pulses from C311 drop below
3 -1 0
the threshold level o f U310B, and the output o f U310B
switches HI for a duration o f about 0.4 fxs (see Figure 3-4)
to produce the positive Chop Blanking pulse. The Chop
Blanking pulse is fed to the Z-Axis Am plifier and is used to
prevent display o f the transistions when switching between
vertical channels.

Internal Trigger Switching Logic

Internal trigger-selection signals to the Trigger Pickoff
Am plifier (Diagram 2) are produced in a logic circuit com­
posed of U305B, U305C, U305D, U315B, and U315C.
The TRIGGER INT Source switch (S305), in conjunction
with CH1-BOTH-CH2 switch
internal trigger source selected. When either the CH 1 or
CH 2 Internal Trigger signal is selected by S305, the
selected channel w ill be the internal trigger source. When
VERT MODE is selected as the internal trigger signal, the
position of S317 determines the channel(s) selected as the
internal trigger source.
CHANNEL 1 SOURCE. The XY signal line from the A
SEC/DIV switch (S630B) applies a LO logic level to INT
switch S305 on pins B and C. In the CH 1 position, the
LO is coupled from pin C to pin D and applied to U305B
pin 4.
The LO is gated through U305B and applied to the CH 1
Trig signal line in a wired-AND connection. The LO from
U305B is applied to Q273 in the Channel 2 Internal Trigger
Pickoff Am plifier (Diagram 2) to bias it off, thus preventing
the Channel 2 signal from being selected. Operation o f the
Internal Trigger Pickoff Amplifiers is discussed in the
"Channel 1 and Channel 2 Preamps" circuit descriptions.
Concurrently, pins 9 and 10 o f U305C are pulled HI
through R304 and R300 respectively to place a HI at
U305C pin 8. The HI from U305C to the wired-AND
connection on the CH 2 Trig signal line enables the output
o f U315B to control the logic level o f the CH 2 Trig signal.
Control is accomplished by the logic levels on the inputs o f
U305D, pins 12 and 13.
The LO on U305B pin 4 (placed there by S305) also
occurs on U305D pin 13. This ensures a LO at U305D
pin 11, which is applied to U315C pin 9 and to U315B
pin 5. The logic level applied to U315C pin 9 has no effect
on the CH 1 Trig signal because a LO is already present at
the wired-AND connection to the signal line. However, the
LO applied to U315B pin 5 ensures that the output o f
U315B is HI. When the CH 2 Trig signal is HI, Q173 in the
Channel 1 Internal Trigger Pickoff Am plifier is biased on
and the Channel 1 signal is passed to the Internal Trigger
Am plifier (Diagram 4).
(S317), determines the