ZiLOG eZ80 User Manual page 19

Pull
Function Up/Down
WAIT PU 2k
HALT_SLP
NMI PU 10K
V
CC
GND
User Manual
Table 3. I/O Connector Pin Identification (Continued)
Signal
Direction Description
OUT Driving the WAIT pin Low forces the
provide additional clock cycles for an external periph-
eral or external memory to complete its READ or
WRITE operation.
IN, Active Low A Low on this pin indicates that the eZ80
enters either HALT or SLEEP mode because of exe-
cution of either a HALT or SLP instruction.
Schmitt Trigger The NMI input is a higher priority input than the
OUT, Active maskable interrupts. It is always recognized at the
Low end of an instruction, regardless of the state of the
interrupt enable control bits. This input includes a
Schmitt trigger to allow RC rise times. This external
NMI signal is combined with an internal NMI signal
generated from the WDT block before being con-
nected to the NMI input of the eZ80
n/a 3.3V Supply Input Pin.
n/a V
UM015201-0603
ZiLOG Development Platforms
®
eZ80 Sales Demonstration Platform
/Ground (0V)
SS
®
eZ80
CPU to
®
CPU
®
CPU.
I/O Connector
13