Watchdog Register - Siemens SIMATIC IPC127E Operating Instructions Manual

10.4.2

Watchdog register

Excerpt from Intel® technical specifications
TCO IO Register
ACPI IO Base Address= 0x400
TCO Register = ACPI IO Adr + TCO Offset
Offset
Start
60h
64h
68h
70h
TCO Reload Register (TCO_RLD) - Offset 60h
Bit
Range
31:10
9:0
TCO Timer Status (TCO_STS) - Offset 64h
Bit
Range
31:18
17
16:4
SIMATIC IPC127E
Operating Instructions, 01/2019, A5E44296915-AA
Offset End Register Name (ID) - Offset
63h TCO Reload Register (TCO_RLD) - Offset 60h
67h TCO Timer Status (TCO_STS) - Offset 64h
69h TCO Timer Control (TCO1_CNT) - Offset 68h
73h TCO Timer Register (TCO_TMR) - Offset 70h
Default & Field Name (ID): Description
Access
0h Reserved (rsvd): Reserved.
RO
0h TCO Timer Value (tco-val): Reading this register will return the current count
of the TCO timer. Writing any value to this register will reload the timer to
RO/V
prevent the timeout.
Default & Field Name (ID): Description
Access
0h Reserved (reserved2): Reserved.
RO
0h Second Timeout Status (second_to_sts): PMC sets this bit to 1 to indicate
that the TIMEOUT bit had been (or is currently) set and a second timeout
RW/1C/V
occurred before the TCO_RLD register was written. If this bit is set and the
NO_REBOOT config bit is 0, then the PMC will reboot the system after sec-
ond timeout. The reboot is done by interrupting the Arc and starting a reset
flow based on the OS_POLICY. This bit is only cleared by writing a 1 to this
bit or by a reset.
On some prior platforms, this field is reset on RSMRST_B, a reset signal
based on a RSMRST# pin that indicates the suspend/resume voltages are
stable.
This field is reset on RSM_RST_N de-assertion. This field is not reset on cold
reset, warm reset, an Sx.
0h Reserved (reserved1): Reserved.
RO
Hardware description
10.4 Input/output address areas
Default
Value
0h
0h
0h
40000h
79