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VOH/VOL Test
TEST_ODD
TEST_EVEN
VOH/VOL
mode
The following is the truth table for the above VOH/VOL tree.
Table 7-4 Truth Table for the VOH/VOL Tree Outputs
Test Vector
TEST_ODD
Number
1
2
3
4
Table 7-5
Refer to
7.4.2
VOH/VOL Tree Activation
To activate the VOH/VOL tree and run a VOH/VOL test, perform the sequence below:
1. Supply a 10MHz clock to I2C_CLK (Test Mode Clock) and a differential clock pair to the HT_REFCLKP/N,
GPP1_REFCLKP/N and GPP3_REFCLKP/N pins.
2. Set POWERGOOD to 0.
3. Set TESTMODE to 1.
4. Set PCIE_RESET_GPIO2 to 0.
5. Wait 5 or more I2C_CLK cycles.
6. Load JTAG instruction register with the instruction 0001 1111.
7. Load JTAG instruction register with the instruction 0010 0000.
8. Load JTAG instruction register with the instruction 0101 1101.
9. Go to Run-Test_Idle state.
10. Set POWERGOOD to 1.
© 2010 Advanced Micro Devices, Inc.
Proprietary
Figure 7-2 Sample of a Generic VOH/VOL Tree
TEST_EVEN
Output
Input
Input
Pin 1
0
0
0
1
1
0
1
1
below for the list of pins that are on the VOH/VOL tree.
Output
Output
Pin 2
Pin 3
0
0
0
0
1
0
1
0
1
1
1
1
Output
Output
Output
Pin 4
Pin 5
Pin 6
0
0
0
1
0
1
0
1
0
1
1
1
47062 SR5650 Databook 2.00
7-5
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