Power Up; Figure 4-1 Sr5650 Power Rail Power Up Sequence; Table 4-5 Sr5650 Power Rail Power-Up Sequence - AMD SR5650 Data Book

Power Rail Sequence
Table 4-4 Power Rail Groupings for the SR5650
Group Name
1.8V
Note:
1. Power rails from the same group are assumed to be generated by the same voltage regulator.
2. Power rails from different groups but at the same voltage can either be generated by separate regulators or by the same regulators as
long as they comply with the requirements specified in the SR5690 Motherboard Design Guide.
4.5.1

Power Up

Figure 4-1 below illustrates the power up sequencing for the various power groups, and Table 4-5
explains the symbols in the figure, as well as the associated requirements.
1.8V
VDDHTTX
VDDPCIE
HT_1.1V
VDDC

Table 4-5 SR5650 Power Rail Power-up Sequence

Symbol
T10 1.8V rails to VDDHTTX (1.2V)
T11 VDDHTTX (1.2V) to VDDPCIE (1.1V)
T12 VDDHTTX(1.2V) to HT_1.1V rails
T13 VDDHTTX(1.2V) to VDDC (1.1V)
Notes:
1. Power rail A ramps after power rail B means that the voltage of rail A does not exceed that of rail B at any time.
2. Power rail A ramps together with power rail B means that the two rails are controlled by the same enable signal and the difference
in their ramping rates is only due to the differences in the loadings.
© 2010 Advanced Micro Devices, Inc.
Proprietary
Power rail name
VDD18
VDDA18PCIE
VDDA18HTPLL
T10

Figure 4-1 SR5650 Power Rail Power Up Sequence

Parameter
ACPI
Voltage
STATE
1.8V S0-S2
1.8V S0-S2
1.8V S0-S2
T11
T12
T13
Requirement
VDDHTTX ramps after 1.8V rails.
VDDPCIE ramps together with or after VDDHTTX
HT_1.1V rails ramp together with or after VDDHTTX
VDDC ramps together with or after VDDHTTX
Description
I/O power for GPIO pads
PCI Express interface 1.8V IO and PLL
power
HyperTransport interface 1.8V PLL power
Comment
See Note 1.
See Note 1 and 2.
See Note 1 and 2.
See Note 1 and 2.
47062 SR5650 Databook 2.00
4-3