Audio Codec - ST STM32F103 Series Application Note

AN2739
Other board resources are used to interface the application:
●
Audio codec: AK4343 implemented on the STM3210E-EVAL and connected to the
I2S2 interface (and to relative passive components).
●
Stereo audio speaker and audio jack connected to the audio codec and implemented
on the STM3210E-EVAL.
● Joystick and key push-buttons: connected to the PG7, PD3, PG13, PG14, PG15 and
PG8 pins on the board. These push-buttons are used to control the audio stream.
●
LCD screen: implemented on the STM3210E-EVAL evaluation board and controlled by
the FSMC interface.
2.2.1

Audio codec

The audio codec implemented on the STM3210E-EVAL is the AK4343 from AKM. This
codec allows digital (PCM raw data transmitted with I
audio parameterization and the codec configuration are performed through an I
The codec has 36 configuration registers mainly used to:
●
program the audio output (speaker or headphone) and input (analog input or digital I
data, etc.).
●
enable or disable the master clock feature and, set the reference clock for internal and
sampling operations.
● set the digital volume level, the mute status and the digital filter coefficients.
The codec can operate in different modes. The modes allowed by the hardware board
implementation are listed below:
●
PLL Slave mode: the internal codec clock is derived, with an internal PLL, from an
external clock. The external clock can be either the bit clock (SCK) or the channel clock
(WS) (this mode requires a high clock accuracy on SCK/WS clock).
●
EXT slave mode: no PLL is used and the internal clock is derived from the MCLK input
clock (at 256 × F
Figure 4
to the STM32F103xx and the board components.
Figure 4. Audio codec hardware implementation
PC6
I2S_MCK
I2S Interface
PB15
I2S_SD
PB12
I2S_WS
PB13
I2S_SCK
PB6
I2C_SCK
I2C Interface PB7
I2C_SDA
PG11 (PDN)
+3V3
frequency rate).
S
illustrates the hardware implementation schematic and how the codec is connected
Default setting: 1<->2
3 TP7
2 MCKO
1 U10
18
MCKO
JP18 17
MCKI
11
SDTI
13
LRCK
14
BICK
6
+3V3 I2C
8
CSN/CAD0
9
CCLK/SCL
10
CDTI/SDA
7
PDN
25
MUTET
C59
1uF
R83
15
DVDD
10
C73
C66
10uF
100nF 16
DVSS
21
+3V3 HVDD
C79
C16
10uF
100nF 22
HVSS
AK4343
2
S protocol) to analog conversion. The
TP12 TP13 TP10
SPP SPN HPL
24
HPL
23
HPR
20 1
SPP
19 2
SPN
12
TEST2
1
C56
TEST1
32
RIN1/IN1+
31
LIN1/IN1-
1uF
30
LIN2/IN2+
29 C57
RIN2/IN2-
28
MIN/LIN3
5
VCOC/RIN3
1uF
27
LOUT/RCP
26
ROUT/RCN
TP6
LIN
+3V3
4
AVDD
C65
C34
10uF
3 100nF
AVSS
C53 C54
2 2.2uF 100nF
VCOM
Implementation example
2
C70
R84
TP8
HPR
6.8
47uF
C80
R87
6.8
47uF
SPEAKER C67 C76
KSS-1508 0.22uF 0.22uF
TP9 R73 R86
RIN 10 10
R67 0
R68 0
C interface.
2
S
CN15
3
2
1
Jack Output
DAC Output
PA4
Audio_RIN
PA5
Audio_LIN
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