3.1
AT91SAM9G10 Microcontroller
Incorporates the ARM926EJ-S™ ARM Thumb Processor
– DSP Instruction Extensions
– ARM Jazelle
– 16-KByte Data Cache, 16-KByte Instruction Cache, Write Buffer
– 266 MHz core frequency
– Memory Management Unit
– EmbeddedICE
– Mid-level implementation Embedded Trace Macrocell
Additional Embedded Memories
– 32K Bytes of Internal ROM, Single-cycle Access at Maximum Bus Speed
– 160K Bytes of Internal SRAM, Single-cycle Access at Maximum Processor or Bus Speed
External Bus Interface (EBI)
– Supports SDRAM, Static Memory, NAND Flash and CompactFlash
LCD Controller
– RGB Addressing
– Supports Passive or Active Displays
– Up to 16-bits per Pixel in STN Color Mode
– Up to 16M Colors in TFT Mode (24-bit per Pixel), Resolution up to 2048 x 2048
USB
– USB 2.0 Full Speed (12 Mbits per second) Host Double Port
– USB 2.0 Full Speed (12 Mbits per second) Device Port
Bus Matrix
– Handles Five Masters and Five Slaves
– Boot Mode Select Option
– Remap Command
Fully Featured System Controller (SYSC) for Efficient System Management, including
– Reset Controller, Shutdown Controller, Four 32-bit Battery Backup Registers for a Total of 16
AT91SAM9G10-EK Evaluation Board User Guide
®
Technology for Java
™
In-circuit Emulation, Debug Communication Channel Support
Dual On-chip Transceivers
Integrated FIFOs and Dedicated DMA Channels
On-chip Transceiver, 2-Kbyte Configurable Integrated FIFOs
Bytes
®
Acceleration
™
Section 3
Board Description
®
6479A–ATARM–26-May-09
3-1
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