Lpc Connector; Smbus Connector - DFI PIC-Q170 User Manual

LPC Connector

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The Low Pin Count Interface was defined by Intel
sition towards legacy free systems. It allows the integration of low-bandwidth legacy I/O com-
ponents within the system, which are typically provided by a Super I/O controller. Furthermore,
it can be used to interface firmware hubs, Trusted Platform Module (TPM) devices and embed-
ded controller solutions. Data transfer on the LPC bus is implemented over a 4 bit serialized
data interface, which uses a 33MHz LPC bus clock. For more information about LPC bus refer
to the Intel Low Pin Count Interface Specification Revision 1.1'. The table below indicates the
®
pin functions of the LPC connector.
Pin Function Pin Function
1 2
CLK
3 4
RST#
5 6
FRAME#
7 8
LAD3
9 10
LAD2
11 12
SERIRQ
13 5VSB 14
Chapter 2 Hardware Installation
LPC
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1
® Corporation to facilitate the industry's tran-
LAD1
LAD0
3V3
GND
---
GND
5V
Chapter 2

SMBus Connector

SMBus
GND
SMB_Data
2
1
5
SMB_Alert
SMB_CLK
3V3DU
The SMBus (System Management Bus) connector is used to connect SMBus devices. It is a mul-
tiple device bus that allows multiple chips to connect to the same bus and enable each one to act
as a master by initiating data transfer.
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