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AK5394A Evaluation Board Rev.B GENERAL DESCRIPTION AKD5394A is an evaluation board for AK5394A, the 24bit A/D converter for professional audio. It has analog input buffer circuits, clock generator circuits, and digital audio interfaces, therefore it can achieve the interface with digital audio systems via optical connector or BNC connector. And it can achieve the direct interface with AKM’s D/A converter evaluation boards via 10-line flat cable.
2) Set-up the evaluation modes, jumper pins and DIP switches. (See the followings.) 3) Power on. The AK5394A and AK4103A should be reset once by bringing SW1 (PDN) to “L” after power-on. After that, release the reset by bringing SW1 (PDN) to “H”.
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PORT2(TOTX176) or J5(TX) are used. It is able to send A/D converted data through optical connector or BNC connector. And it is able to connect to AKM’s D/A evaluation board and digital amp. When MCLK is received from external source through BNC connector (J6), JP2(CLK) should be connected to “BNC” side, and JP16(XTE) should be short.
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HPFE SMODE2 SMODE ZCAL Table1. Polarity of DIP switch: SW2 CKS0 CKS1 Table2. Polarity of DIP switch: SW3 2. Setting of DIP switch : SW2(AK5394A), SW3(AK4103A) (1) Setting of DIP switch : SW2(AK5394A) Sampling Speed Normal Double Quad DFS1 (SW2-1)
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Table6. Audio format of AK4103A [SW3-2,3,4,5] : Set sampling frequency of channel status. (default is all “OFF”.) [SW3-1] : Set validity of channel status. (default is “OFF”.) 3. Setting of clock Setting of clock of AK5394A and AK4103A LRCK(fs) MCLK BICK JP11...
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96k (Note2) : x 1/256 48k (Note2) : x 1/512 (default) [JP13] (LRCK1) : select the adjust of the phase of LRCK and SCLK(BICK) for AK5394A and AK4103A. 74HC4040 : supply LRCK without the adjust of the phase of LRCK and SCLK(BICK).
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Figure 5. The analog signal is able to input through XLR or BNC connectors. (For BNC input, jumper should be short. For XLR input, jumper should be open.) The input level of this circuit is +/-12.7Vpp (AK5394A: +/-2.4Vpp Typ.). When using this circuit, analog characteristics at fs=48kHz is DR=120dB, S/(N+D)=105dB.
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Because the internal VREF cannot settle to the appropriate voltage when the calibration cycle is completed. In this case, the offset calibration cycle should be started again after the VREF voltage settled. (Figure 8) The relationship between the capacitance and the VREF settling time is shown in Table 10. AK5394A VREF+ 0.22u VREF- Figure 6.
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ASAHI KASEI [AKD5394A] [Measurement Example] Ta=25°C; VA=5.0V; VD=3.3V; AGND, BGND, DGND=0V; fs=48kHz; Audio Precision System Two. 24 bit Output; BW=10Hz~20kHz; DFS0= “L”, DFS1= “L”, Using AK M A K5394A THD +N vs Frequency 220µF 100µF 10µF -100 -105 -110 -115 -120 1000µF 470µF...
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