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Evaluation board Rev.0 for AK4552 GENERAL DESCRIPTION AKD4552-A is an evaluation board for the digital audio 24bit A/D and D/A converter, AK4552. The AKD4552-A can evaluate A/D converter and D/A converter separately in addition to loopback mode (A/D → D/A). The A/D section can be evaluated by interfacing with AKM’s DAC evaluation boards directly. The AKD4552-A has the interface with AKM’s ADC evaluation boards.
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R6(R4) Figure 2. Input buffer circuit on board * AKM assumes no responsibility for the trouble when using the circuit examples. Analog Output Circuit The AK4552 includes a combination of switched-capacitor filter (SCF) and continuous-time filter (CTF), so any external filters are not required.
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PORT2 (DIT) and X2 (X’tal) is used. DIT generates audio bi-phase signal from received data and which is output through optical connector (TOTX176). It is possible to connect AKM’s D/A converter evaluation boards on the digital-amplifier which equips DIR input. Nothing should be connected to PORT1 (DIR), PORT3 (ROM).
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ASAHI KASEI [AKD4552-A] (2) Evaluation of D/A using DIR (Optical Link) PORT1 (DIR) is used. DIR generates MCLK, BCLK, LRCK and SDATA from the received data through optical connector (TORX176). Used for the evaluation using CD test disk. Nothing should be connected to PORT3 (ROM).
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ASAHI KASEI [AKD4552-A] 2-4) 1/2 decimation of DAC (MCLK=128fs) Input fs example for PORT1 : fs = 64kHz, 88.2kHz, 96kHz JP10 JP11 JP12 MCKO SPEED MCLK MODE BCFS LRFS (3) Evaluation of loopback mode (default) Using U4 (AK4112B) and X1 (X’tal). Nothing should be connected to PORT1 (DIR), PORT3 (ROM). Set up “H”...
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It is possible to make evaluation in the form of analog inputs and analog outputs by interfacing with various AKM’s A/D evaluation boards with PORT3 (ROM). Nothing should be connected to PORT1 (DIR). In case of using external clock through a BNC connector (J5), select EXT on JP11 (CLK) and short JP8 (XTE) and open JP13 (EXT).
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(5) Evaluation of A/D using D/A converted data It is possible to make evaluation in the form of analog inputs and analog outputs by interfacing with various AKM’s D/A evaluation boards with PORT3 (ROM). Nothing should be connected to PORT1 (DIR). JP13...
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ASAHI KASEI [AKD4552-A] (6) All interface signals including master clock are fed externally. Under the following set-up, all external signals needed for the AK4552 to operate could be fed through PORT3 (ROM). In case of interfacing external sources to D/A converter, JP6 (SDTI) should be open. And in case of using A/D data to externally, JP6 (SDTI) is set ADC side.
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ASAHI KASEI [AKD4552-A] Other jumper pins set up [JP1] (GND): Analog ground and digital ground open: separated short: common (The connector “DGND” can be open.) <default> [JP5] (SDTO): SDTO of AK4552 Always open. It is possible to short for evaluation mode 6.
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ASAHI KASEI [AKD4552-A] 1. ADC (Normal Speed) AK4552 AD C THD+N vs. Input Level VA=VD =3.0V, fs=44.1kHz, fin=1kHz -100 -120 -110 -100 dB r Figure 1. THD+N vs. Input Level AK4552 AD C THD+N vs. Input Frequency VA=VD=3.0V, fs=44.1kHz, Input=-0.5dBr -100 Figure 2.
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ASAHI KASEI [AKD4552-A] 3. ADC (Double Speed) AK4552 AD C THD+N vs. Input Level VA=VD=3.0V, fs=96kHz, fin=1kHz -100 -120 -110 -100 dB r Figure 1. THD+N vs. Input Level AK4552 AD C THD+N vs. Input Frequency VA=VD =3.0V, fs=96kHz, Input=-0.5dBr -100 Figure 2.
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ASAHI KASEI [AKD4552-A] 4. DAC (Double Speed) AK4552 D AC THD+N vs. Input Level VA=VD=3.0V, fs=96kHz, fin=1kHz -100 -105 -110 -115 -120 -120 -110 -100 dB FS Figure 1. THD+N vs. Input Level AK4552 D AC THD+N vs. Input Frequency VA=VD=3.0V, fs=96kHz, Input=0dBFS...
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AK4552 0.1u 0.1u 74LVC541 74LVC541 1S1588 1S1588 74HC14 74HC14 74HC14 74HC14 0.1u 0.1u Title Title Title AKD4552-A AKD4552-A AKD4552-A Size Size Size Document Number Document Number Document Number AK4552 AK4552 AK4552 Date: Date: Date: Monday , September 26 , 2005...
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PORT1 PORT1 RX3/DIF1 + C33 + C33 0.1u 0.1u RX4/DIF2 AUTO AK4112B AK4112B Title Title Title AKD4552-A AKD4552-A AKD4552-A Size Size Size Document Number Document Number Document Number Date: Date: Date: Monday, September 26, 2005 Monday, September 26, 2005 Monday, September 26, 2005...
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X_LRCK 74HCU04 74HCU04 JP12 JP12 LRFS LRFS 74HC4040 74HC4040 JP13 JP13 Title Title Title AKD4552-A AKD4552-A AKD4552-A Size Size Size Document Number Document Number Document Number Date: Date: Date: Monday, September 26, 2005 Monday, September 26, 2005 Monday, September 26, 2005...
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