AKM AKD4951AEN-B Manual

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The AKD4951AEN-B is an evaluation board for the AK4951AEN 24bit CODEC with built-in PLL and

MIC/HP/SPK Amplifier. The AKD4951AEN-B has the interface with AKM's A/D evaluation boards. Therefore,

it's easy to evaluate the AK4951AEN. The AKD4951AEN-B also has the digital audio interface and can achieve

the interface with digital audio systems via opt-connector.

 Ordering Guide

AKD4951AEN-B ---

 Compatible with 2 types of interface

- Direct interface with AKM's A/D converter evaluation boards

- DIT/DIR with optical input/output

 USB port for board control

Digital

MIC

Mini

Jack

* Circuit diagram and PCB layout are attached at the end of this manual.

Evaluation board Rev.2 for AK4951AEN

GENERAL DESCRIPTION

Evaluation board for AK4951AEN

(Control software is included in this package.)

TVDD DVDD AVDD SVDD

3.3V

1.8V

LIN1

RIN1

LIN2

AK4951AEN

RIN2

LIN3

RIN3

SPP SPN

SPK

Figure 1. AKD4951AEN-B Block Diagram

AKD4951AEN-B

FUNCTION

GND1

3.3V

LINE-

OUT

Jack

- 1 -

[AKD4951AEN-B]

REG1

REG

1.8V

LDO

(T3)

USB

PIC4550

External

Clock

AK4118A

(DIT/DIR)

Opt Out

Opt In

2016/09

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Summary of Contents for AKM AKD4951AEN-B

Page 1 The AKD4951AEN-B is an evaluation board for the AK4951AEN 24bit CODEC with built-in PLL and MIC/HP/SPK Amplifier. The AKD4951AEN-B has the interface with AKM’s A/D evaluation boards. Therefore, it’s easy to evaluate the AK4951AEN. The AKD4951AEN-B also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector.
Page 2: Operation Sequence
[AKD4951AEN-B]  Operation Sequence (1) Set up the power supply lines. (1-1) In case of supplying the power from regulator. <Default> JP17 SVDD USB5V 1.8V 3.3V Name of Color Default Setting Using Jack REG1 for regulator input GND1 black ground Table 1.
Page 3: Evaluation Mode
[AKD4951AEN-B]  Evaluation mode In case of using the AK4118A when evaluating the AK4951AEN, audio interface format of both devices must be matched. Reter to the datasheet for audio interface format of the AK4951AEN, and Table 2 for audio interface format of the AK4118A.
Page 4 [AKD4951AEN-B] (1) A/D Evaluation using the AK4118A (DIT) (1-1) Setting in External Slave Mode X1 (X’tal: 12.288MHz) and PORT2 (DIT) are used. Do not connect anything to PORT1 (DIR). Registers of the AK4951AEN should be set to “EXT Slave Mode”. MCKI, BICK and LRCK are supplied from the AK4118A, and SDTO of the AK4951AEN is output to the AK4118A.
Page 5 [AKD4951AEN-B] A/D or D/A Evaluation using the external clock. External clocks are used. Do not connect anything to PORT1 (DIR) and PORT2 (DIT). (3-1) Setting in PLL Master Mode The master clock is input from the MCKI pin of JP11. An internal PLL circuit generates BICK and LRCK.
Page 6 [AKD4951AEN-B] (3-2) Setting in PLL Slave Mode A reference clock of PLL is selected among the input clocks that are supplied to the BICK pin. The required clock to operate the AK4951AEN is generated by an internal PLL circuit. Registers of the AK4951AEN should be set to “PLL Slave Mode” (Reference Clock = BICK).
Page 7 [AKD4951AEN-B] (3-3) Setting in External Slave Mode Registers of the AK4951AEN should be set to “EXT Slave Mode”. MCLK, BICK, LRCK SDTI and SDTO are input into and output from JP11, JP14, JP12, JP13 and JP15. DSP or P AK4951AEN...
Page 8 [AKD4951AEN-B] (4-2) Setting in PLL Slave Mode Registers of the AK4951AEN should be set to “PLL Slave Mode” (Reference Clock: BICK). Do not connect anything to PORT1 (DIR) and PORT2 (DIT). (4-2-1) In case of supplying BICK and LRCK from the external clock The jumper pins should be set as follows.
Page 9: Dip Switch Setting
*Upper-side is “H” and lower-side is “L”. [SW1] (PDN): Power downs AK4951AEN and AK4118A. Keep “H” during normal operation.  Control Port It is possible to control AKD4951AEN-B via general USB port. Connect cable with the USB connection(PORT3) on the board and PC. <KM121002>...
Page 10: Analog Input/Output Circuits
[AKD4951AEN-B]  Analog Input/Output Circuits (1) Input Circuits Figure 5. LIN1/RIN1, LIN2/RIN2, LIN3/RIN3 Input Circuits (1-1) LIN1/RIN1Input Circuit <Default> LIN1 and RIN1are input to J1. When the Mic Power is not used, JP6 and JP7 should be set to open.
Page 11 [AKD4951AEN-B] (1-2) LIN2/RIN2 Input Circuit <Default> LIN2 and RIN2 are input to J2 and J3. When the Mic Power is not used, JP8 and JP9 should be set to open. LIN3 RIN3 LIN2 RIN2 MP-LIN2 MP-RIN2 LIN1 RIN1 LIN-SEL RIN-SEL (1-3) LIN3/RIN3 Input Circuit LIN3 and RIN3 are input to J2 and J3.
Page 12 C25 1u J3 LINE-OUT ROUT LOUT C24 1u VSS3 Figure 8. LOUT/ROUT Output Circuit LOUT and ROUT are output from J3. * AKM assumes no responsibility for the trouble when using the above circuit examples. <KM121002> 2016/09 - 12 -...
Page 13 2. Connect the evaluation board and PC with a USB cable. 3. The USB control is recognized as HID (Human Interface Device) on the PC. 4. Double-click the icon “akd4951aen-b.exe” to open the control program. (Note 5. When the screen does not display “AKDUSBIF-B” at bottom left, reconnect the PC and the USB cable, and push the [Port Reset] button.
Page 14: Operation Overview
[AKD4951AEN-B] ■Operation Overview Function and Register map are controlled by this control software. These controls may be selected by the upper tabs. Frequently used Buttons, such as the register initializing button “Write Default”, are located outside of the switching tab window. Refer to the “■ Dialog Box” section for details of each dialog box setting.
Page 15: Tab Functions
[AKD4951AEN-B] ■Tab Functions 1. [Function] Tab: Function Control When a button in the “Function” frame is clicked, a sequential process is executed. When other button is clicked, the setting dialog opens. (Refer to the “■ Sequential process” section for details of each dialog box setting, or “■ Dialog Box” section for details of each dialog box setting.)
Page 16: Function Button
[AKD4951AEN-B] 1- 1. [Function] Button Figure 11. [Function] Button A function button executes the sequence process shown on the each button and updates several registers. These functions are mainly for path settings. Function Name Description Input Output Path Recording_MIC+18dB MIC Input Recording...
Page 17 [AKD4951AEN-B] 1- 2. Setting Dialog Button Figure 12. Setting Dialog button [System Clock Audio I/F] button : Opens “System Clock & Audio I/F” dialog box. [MIC – ADC Setting] button : Opens “MIC_ADC Setting” dialog box. [Digital MIC Setting] button : Opens “Digital MIC Setting”...
Page 18 [AKD4951AEN-B] 2. [REG] Tab: Register Map This tab is for register read and write. Each bit on the register map is a push-button switch. The register is updated by mouse operation. Button Down indicates “1” and the bit name is shown in red (when read-only the name is shown in dark red).
Page 19 [AKD4951AEN-B] 2-1. [Write]: Data Write Dialog Select the [Write] button located on the right of the each corresponding address when changing two or more bits on the same address simultaneously. Click the [Write] button located on the right of the each corresponded address for a pop-up dialog box.
Page 20 [AKD4951AEN-B] ■Dialog Box 1. [Save]: [Save Address of Register] Dialog Box Click the [Save] button in the main window for save address setting dialog box. Figure 15. [Save] Window [All Address] check box : When the [All Address] checkbox is checked, all register settings will be saved.
Page 21: Operating Suggestions
[AKD4951AEN-B] 2. [All Reg Write]: [All Register Write] Dialog Box Click the [All Reg Write] button in the main window to open register setting file window show below. Register setting files saved by the [Save] button may be applied. Figure 16. [All Reg Write] Window [Open (left)] button : Selects a register setting file (*.akr).
Page 22: Sequence Setting
[AKD4951AEN-B] 3. [Sequence]: [Sequence] Dialog Box Click the [Sequence] button in the main window to open register sequence setting dialog box Register sequence can be set in this dialog box. Figure 17. [Sequence] Window ~ Sequence Setting ~ Set register sequence according to the following process.
Page 23: Control Buttons
[AKD4951AEN-B] Input sequence [Address] : Data address [Data] : Write data [Mask] : Mask This value “ANDed” with the write data becomes the input data. The bits which corresponding Mask bit = “0” are not changed. At this time, data read is not executed, and the storage data of this software is used.
Page 24 [AKD4951AEN-B] 4. [Sequence (File)]:[Sequence by *.aks file] Dialog Box Click the [Sequence (File)] button to open sequence setting file dialog box shown below. Files saved in the “Sequence setting dialog” can be applied in this dialog. Figure 18. [Sequence (File)] Window [Open (left)] button : Opens a sequence setting file (*.aks).
Page 25 [AKD4951AEN-B] 5. [System Clock Audio I/F]: [System Clock & Audio I/F] Dialog Box Click the [System Clock Audio I/F] button in the main window to open system clock and Audio I/F setting dialog. The settings on this dialog are interlocked with the settings on register map.
Page 26 [AKD4951AEN-B] 6. [MIC – ADC Setting]: [MIC – ADC Setting (Recording)] Dialog Box Click the [MIC-ADC Setting] button in the main window to open MIC and ADC setting dialog box. MIC/Line input, ADC, MIC gain and sensitivity setting are available.
Page 27 [AKD4951AEN-B] ~ Gain Control by Slider ~ The volume can also be changed by slider. When a value is input in the edit box, the slide bar is moved to the value that selected by the edit box. Use the mouse or arrow keys on the keyboard for small adjustments.
Page 28 [AKD4951AEN-B] 8. [Digital Filter]: [Filter Setting] Dialog Box Click the [Digital Filter] button in the main window to open Digital Filter setting dialog. Coefficient and frequency of digital filter are calculated on this dialog. (Refer to the datasheet for register definitions.) Figure 24.
Page 29: Parameter Setting
[AKD4951AEN-B] 8-1. Parameter Setting Please set a parameter of each Filter Parameter Detail Setting Range Sampling Rate Sampling Frequency (fs) 8, 11.025, 12, 16, 22.05, 24 32, 44.1 or 48kHz 3.7×fs/48 ～ 236.8×fs/48 (kHz) HPF1 Cut Off Frequency High Pass Filter 1 cut off frequency 0.0001 ≦...
Page 30 [AKD4951AEN-B] 8-2. [Register Setting]: [Register Setting for Filter] Dialog Box Click the [Register Setting] button, a register set value is displayed. When a value out of a setting range is set, error message is displayed, and a calculation of register setting is not carried out.
Page 31 [AKD4951AEN-B] 8-3. [F Response]: [Filter Plot] Dialog Box A frequency characteristic is displayed when push a [F Response] button. Then, a register set point is also updated. Change Frequency Range, and indication of a frequency characteristic is updated when push a [UpDate] button.
Page 32 [AKD4951AEN-B] 8-4. 5-BandEQ operation on Filter Plot screen When EQ (1~5) is turning “ON”, a green number is displayed on the Filter Plot dialog box. This number shows the setting of the center frequency and the gain of each EQ.
Page 33 [AKD4951AEN-B] 8-5. Simulation of Fil3 Filter Setting of Stereo-MIC [L-ch Level] / [R-ch Level] : Gain mismatch of stereo MIC sensitivity are set. [Distance] : The distance between the sound source and the MIC is set. [Angle] : The angle between the sound source and the MIC is set.
Page 34 [AKD4951AEN-B] 8-6. About “Notch Auto Correct” If the gain of 5-Band EQ is set to “-1”, Equalizer becomes a notch filter. When the center frequency of two or more notch filters is adjacent, the gap is generated in the center frequency.
Page 35 [AKD4951AEN-B] 8-7. Common Gain Sequence for Noise If “EQ Sequence for Noise (ON/OFF)” button is pushed, setup bit about EQ2-5 shown below are changed. When the button pushed to OFF, each setup is returned the state of before pushing a button.
Page 36 [AKD4951AEN-B] 9. [ALC Setting]: [ALC Setting] Dialog Box Click the [ALC Setting] button in the main window to open ALC setting dialog. ALC parameters are controlled in this dialog. The settings on this dialog are interlocked with the settings on register map.
Page 37: Dialog Box
[AKD4951AEN-B] Dialog Box 10. [DAC Setting]: [DAC_LINE/SPK/HP Setting(Playback)] Click the [DAC Setting] button in the main window to open DAC setting dialog. Output mode, DAC and output gain setting are available. The settings on this dialog are interlocked with the settings on register map.
Page 38 [AKD4951AEN-B] 11. [BEEP Setting]: [BEEP Setting] Dialog Box Click the [BEEP Setting] button in the main window to open BEEP setting dialog. The settings on this dialog are interlocked with the settings on register map. (Refer to the datasheet for register definitions.) Figure 39.
Page 39 [AKD4951AEN-B] ■Sequential process 1. [ Recording_MIC+18dB (ALC, AHPF ON) When [Recording_MIC+18dB] button in the main window is clicked, the sequence for MIC input Settings (stereo) is executed. (Note [MIC-ADC Setting] Window [ALC Setting] Window [Filter Setting] Window Figure 40. [Recording_MIC+18dB] Setting <KM121002>...
Page 40 [AKD4951AEN-B] 2. [ Recording_DigitalMIC (AHPF, ALC ON) When [Recording_DigitalMIC] button in the main window is clicked, the sequence for Digital MIC input Settings (stereo) is executed. (Note [Digital MIC Setting] Window [ALC Setting] Window [Filter Setting] Window Figure 41. [Recording_DigitalMIC] Setting <KM121002>...
Page 41 [AKD4951AEN-B] 3. [ Playback_Headphone When [Playback_Headphone] button in the main window is clicked, the sequence for Headphone output Settings is executed. [DAC_LINE/SPK/HP Setting] Window Figure 42. [Playback_Headphone] Setting 4. [ Playback_Speaker (ALC ON) When [Playback_Speaker] button in the main window is clicked, the sequence for Speaker output Settings is executed.
Page 42 [AKD4951AEN-B] 5. [ Playback_Lineout When [Playback_Lineout] button in the main window is clicked, the sequence for Line output Settings is executed. (Note [DAC_LINE/SPK/HP Setting] Window Figure 44. [Playback_Lineout] Setting 5. [ Loopback_Headphone When [Loopback_Lineout] button in the main window is clicked, the sequence of Loopback settings is executed.
Page 43 [AKD4951AEN-B] [Filter Setting] Window [DAC_LINE/SPK/HP Setting] Window Figure 45. [Loopback_Headphone] Setting Note 7. The register setting of ALC by the sequence of [Recording_MIC+18dB], [Recording_DigitalMIC], [Playback_Speaker] or [Loopback_Headphone] is same. The register setting of Digital Filter is also the same among the above except [Playback_Speaker].
Page 44 [AKD4951AEN-B] MEASUREMENT RESULTS [Measurement Condition] ・ Measurement unit : Audio Precision, System two Cascade ・ MCKI : 256fs (12.288MHz) ・ BICK : 64fs ・ fs : 48kHz ・ Bit : 24bit ・ Measurement Mode : EXT Slave Mode ・ Power Supply : AVDD = SVDD = TVDD = 3.3V, DVDD = 1.8V...
Page 45 [AKD4951AEN-B] [Plot]  1. ADC (LIN1/RIN1 ADC) (Ceramic Capacitor) [MGAIN=+18dB] AK4951AEN ADC FFT (-1dBFS) -100 -120 -140 Figure 46. FFT (Input level= -1dBFS) AK4951AEN ADC FFT (-60dBFS) -100 -120 -140 Figure 47. FFT (Input level= -60dBFS) <KM121002> 2016/09 - 45 -...
Page 46 [AKD4951AEN-B] AK4951AEN ADC FFT (No signal) -100 -120 -140 Figure 48. FFT (No signal) AK4951AEN ADC THD+N vs Input Level (fin=1kHz) -100 -100 Figure 49. THD+N vs. Input Level <KM121002> 2016/09 - 46 -...
Page 47 [AKD4951AEN-B] AK4951AEN ADC THD+N vs Frequency (-1dBFS) -100 Figure 50. THD+N vs. Input Frequency AK4951AEN ADC Linearity (fin=1kHz) -100 -100 Figure 51. Linearity <KM121002> 2016/09 - 47 -...
Page 48 [AKD4951AEN-B] AK4951AEN ADC Crosstalk (-1dBFS) T TT T T T T T T TT T T T TT T T T T T T T T T T T T T T T T TT T T T T T T T...
Page 49 [AKD4951AEN-B] [MGAIN=0dB] AK4951AEN ADC FFT (-1dBFS) -100 -120 -140 Figure 54. FFT (Input level= -1dBFS) AK4951AEN ADC FFT (-60dBFS) -100 -120 -140 Figure 55. FFT (Input level= -60dBFS) <KM121002> 2016/09 - 49 -...
Page 50 [AKD4951AEN-B] AK4951AEN ADC FFT (No signal) -100 -120 -140 Figure 56. FFT (No signal) AK4951AEN ADC THD+N vs Input Level (fin=1kHz) -100 -100 Figure 57. THD+N vs. Input Level <KM121002> 2016/09 - 50 -...
Page 51 [AKD4951AEN-B] AK4951AEN ADC THD+N vs Frequency (-1dBFS) -100 Figure 58. THD+N vs. Input Frequency AK4951AEN ADC Linearity (fin=1kHz) -100 -100 Figure 59. Linearity <KM121002> 2016/09 - 51 -...
Page 52 [AKD4951AEN-B] AK4951AEN ADC Crosstalk (-1dBFS) T T T TT T T T T T TTTT T T T T T T T T -100 -110 -120 -130 -140 Figure 60. Crosstalk AK4951AEN ADC Frequency Response (-1dBFS) -0.2 -0.4 -0.6 -0.8 -1.2...
Page 53 [AKD4951AEN-B]  2. ADC (LIN3/RIN3 ADC) (Electrolytic Capacitor) [MGAIN=+18dB] AK4951AEN ADC FFT (-1dBFS) -100 -120 -140 Figure 62. FFT (Input level= -1dBFS) AK4951AEN ADC FFT (-60dBFS) -100 -120 -140 Figure 63. FFT (Input level= -60dBFS) <KM121002> 2016/09 - 53 -...
Page 54 [AKD4951AEN-B] AK4951AEN ADC FFT (No signal) -100 -120 -140 Figure 64. FFT (No signal) AK4951AEN ADC THD+N vs Input Level (fin=1kHz) -100 -100 Figure 65. THD+N vs. Input Level <KM121002> 2016/09 - 54 -...
Page 55 [AKD4951AEN-B] AK4951AEN ADC THD+N vs Frequency (-1dBFS) -100 Figure 66. THD+N vs. Input Frequency AK4951AEN ADC Linearity (fin=1kHz) -100 -100 Figure 67. Linearity <KM121002> 2016/09 - 55 -...
Page 56 [AKD4951AEN-B] AK4951AEN ADC Crosstalk (-1dBFS) TTT T T T T T T T TT TT T T T T T T TT T T T T T TTT T TT T T T -100 -110 -120 -130 -140 Figure 68. Crosstalk AK4951AEN ADC Frequency Response (-1dBFS) -0.2...
Page 57 [AKD4951AEN-B] [MGAIN=0dB] AK4951AEN ADC FFT (-1dBFS) -100 -120 -140 Figure 70. FFT (Input level= -1dBFS) AK4951AEN ADC FFT (-60dBFS) -100 -120 -140 Figure 71. FFT (Input level= -60dBFS) <KM121002> 2016/09 - 57 -...
Page 58 [AKD4951AEN-B] AK4951AEN ADC FFT (No signal) -100 -120 -140 Figure 72. FFT (No signal) AK4951AEN ADC THD+N vs Input Level (fin=1kHz) -100 -100 Figure 73. THD+N vs. Input Level <KM121002> 2016/09 - 58 -...
Page 59 [AKD4951AEN-B] AK4951AEN ADC THD+N vs Frequency (-1dBFS) -100 Figure 74. THD+N vs. Input Frequency AK4951AEN ADC Linearity (fin=1kHz) -100 -100 Figure 75. Linearity <KM121002> 2016/09 - 59 -...
Page 60 [AKD4951AEN-B] AK4951AEN ADC Crosstalk (-1dBFS) T T T T T T T TT T TT TT T -100 -110 -120 -130 -140 Figure 76. Crosstalk AK4951AEN ADC Frequency Response (-1dBFS) -0.2 -0.4 -0.6 -0.8 -1.2 -1.4 -1.6 -1.8 Figure 77. Frequency Response <KM121002>...
Page 61 [AKD4951AEN-B]  3. DAC (DAC Headphone (HPL/HPR)) AK4951AEN DAC=>HP FFT (0dBFS) -100 -120 -140 Figure 78. FFT (Input level= 0dBFS) AK4951AEN DAC=>HP FFT (-60dBFS) -100 -120 -140 Figure 79. FFT (Input level= -60dBFS) <KM121002> 2016/09 - 61 -...
Page 62 [AKD4951AEN-B] AK4951AEN DAC=>HP FFT (No signal) -100 -120 -140 Figure 80. FFT (No signal) AK4951AEN DAC=>HP FFT (Out-of-band Noise) -100 -120 -140 100k Figure 81. FFT (Out-of-band Noise) <KM121002> 2016/09 - 62 -...
Page 63 [AKD4951AEN-B] AK4951AEN DAC=>HP THD+N vs Input Level (fin=1kHz) -100 -110 -120 -120 -100 dBFS Figure 82. THD+N vs. Input Level AK4951AEN DAC=>HP THD+N vs Frequency (0dBFS) -100 -110 -120 Figure 83. THD+N vs. Input Frequency <KM121002> 2016/09 - 63 -...
Page 64 [AKD4951AEN-B] AK4951AEN DAC=>HP Linearity (fin=1kHz) -100 -100 dBFS Figure 84. Linearity AK4951AEN DAC=>HP Crosstalk (0dBFS) -100 -110 -120 Figure 85. Crosstalk <KM121002> 2016/09 - 64 -...
Page 65 [AKD4951AEN-B] AK4951AEN DAC=>HP Frequency Response (0dBFS) +0.5 +0.4 +0.3 +0.2 +0.1 -0.1 -0.2 -0.3 -0.4 -0.5 Figure 86. Frequency Response <KM121002> 2016/09 - 65 -...
Page 66 [AKD4951AEN-B]  4. DAC (DAC Speaker (SPP/SPN)) AK4951AEN DAC=>SKP FFT (-0.5dBFS, SPKG=01) -100 -120 -140 Figure 87. FFT (Input level= -0.5dBFS) AK4951AEN DAC=>SKP FFT (-60dBFS, SPKG=01) -100 -120 -140 Figure 88. FFT (Input level= -60dBFS) <KM121002> 2016/09 - 66 -...
Page 67 [AKD4951AEN-B] AK4951AEN DAC=>SKP FFT (No signal, SPKG=01) -100 -120 -140 Figure 89. FFT (No signal) AK4951AEN DAC=>SKP Out of band noise (SPKG=01) -100 -120 -140 100k Figure 90. FFT (Out-of-band Noise) <KM121002> 2016/09 - 67 -...
Page 68 [AKD4951AEN-B] AK4951AEN DAC=>SKP THD+N vs Frequency (-0.5dBFS, SPKG=01) -100 -110 -120 Figure 91. THD+N vs. Input Frequency AK4951AEN DAC=>SKP Linearity (-0.5dBFS, SPKG=01) -100 -100 dBFS Figure 92. Linearity <KM121002> 2016/09 - 68 -...
Page 69 [AKD4951AEN-B] AK4951AEN DAC=>SKP Frequency Response (-0.5dBFS, SPKG=01) -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 Figure 93. Frequency Response AK4951AEN DAC=>SKP THD+N vs Output Power (fin=1kHz, SPKG=00) 200m 180m 160m 140m 120m 100m dBFS Figure 94. THD+N vs. Output Power (SPKG=00) <KM121002>...
Page 70 [AKD4951AEN-B] AK4951AEN DAC=>SKP THD+N vs Output Power (fin=1kHz, SPKG=01) 300m 250m 200m 150m 100m -100 dBFS Figure 95. THD+N vs. Output Power (SPKG=01) AK4951AEN DAC=>SKP THD+N vs Output Power (fin=1kHz, SPKG=10) 500m 450m 400m 350m 300m 250m 200m 150m 100m...
Page 71 [AKD4951AEN-B] AK4951AEN DAC=>SKP THD+N vs Output Power (fin=1kHz, SPKG=11) 800m 600m 400m -100 200m -120 dBFS Figure 97. THD+N vs. Output Power (SPKG=11) <KM121002> 2016/09 - 71 -...
Page 72 [AKD4951AEN-B] 5. DAC (DAC  Line-out (LOUT/ROUT)) AK4951AEN DAC=>Line-out FFT (0dBFS, LVCM=01) -100 -120 -140 Figure 98. FFT (Input level= 0dBFS) AK4951AEN DAC=>Line-out FFT (-3dBFS, LVCM=01) -100 -120 -140 Figure 99. FFT (Input level= -3dBFS) <KM121002> 2016/09 - 72 -...
Page 73 [AKD4951AEN-B] AK4951AEN DAC=>Line-out FFT (-60dBFS, LVCM=01) -100 -120 -140 Figure 100. FFT (Input level= -60dBFS) AK4951AEN DAC=>Line-out FFT (No signal, LVCM=01) -100 -120 -140 Figure 101. FFT (No signal) <KM121002> 2016/09 - 73 -...
Page 74 [AKD4951AEN-B] AK4951AEN DAC=>Line-out Out-of-band Noise (LVCM=01) -100 -120 -140 100k Figure 102. FFT (Out-of-band Noise) AK4951AEN DAC=>Line-out THD+N vs Input Level (fin=1kHz, LVCM=01) -100 -110 -120 -100 dBFS Figure 103. THD+N vs. Input Level <KM121002> 2016/09 - 74 -...
Page 75 [AKD4951AEN-B] AK4951AEN DAC=>Line-out THD+N vs Frequency (-3dBFS, LVCM=01) -100 -110 -120 Figure 104. THD+N vs. Input Frequency AK4951AEN DAC=>Line-out Linearity (fin=1kHz, LVCM=01) -100 -100 dBFS Figure 105. Linearity <KM121002> 2016/09 - 75 -...
Page 76 [AKD4951AEN-B] AK4951AEN DAC=>Line-out Crosstalk (-3dBFS, LVCM=01) TT T TT T T T T T T T TT T T T -100 -110 -120 Figure 106. Crosstalk AK4951AEN DAC=>Line-out Frequency Response (-3dBFS, LVCM=01) -2.2 -2.4 -2.6 -2.8 -3.2 -3.4 -3.6 -3.8 Figure 107.
Page 77 [AKD4951AEN-B] REVISION HISTORY Date Manual Board Reason Page Contents (YY/MM/DD) Revision Revision 15/03/31 KM121000 First edition 16/03/10 KM121001 Board change AK4951AEN : Rev.C→Rev.D Change 44-76 Measurement data were changed. 16/09/20 KM121002 Board change 79,81 Part number was changed.(T2,T3) <KM121002> 2016/09...
Page 78 AKM or any third party with respect to the information in this document. You are fully responsible for use of such information contained in this document in your product design or applications.
Page 79 2.2k VSS1 LIN-SEL VSS1 open 2.2k 2.2k open VSS1 open VSS1 VSS1 Title Title Title AKD4951AEN-B AKD4951AEN-B AKD4951AEN-B - 79- Size Size Size Document Number Document Number Document Number R e v R e v R e v AK4951AEN AK4951AEN...
Page 80 INT0 IPS0/RX4 HSU119 0.47u C45 0.1u RESET 0.1u PORT1 R21 470 0.1u OPT-IN Title Title Title AKD4951AEN-B AKD4951AEN-B AKD4951AEN-B - 80- Size Size Size Document Number Document Number Document Number R e v R e v R e v DIR/DIT...
Page 81 100k 0.1u 0.1u MCLR VREF1 VREF2 SCL1 SCL2 JP16 SDA1 SDA2 Title Title Title AKD4951AEN-B AKD4951AEN-B AKD4951AEN-B USB-PDN - 81- Size Size Size Document Number Document Number Document Number R e v R e v R e v Control I/F (USB)
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