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AKM AKD4344-A Manual

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The AKD4344-A is an evaluation board for the AK4344, 24bit and 96kHz DAC with DIT for portable and
home audio systems. The AKD4344-A has the interface with AKM's A/D converter evaluation boards and
the interface with digital audio systems via optical connector. Therefore, it is easy to evaluate the
AK4344.
Ordering guide
AKD4344-A ---
• Compatible with 2 types of input data interface
- Direct interface with AKM's A/D converter evaluation boards via 10-pin header
- On-board AK4112B as DIR, which accepts optical or BNC Inputs
• Optical output for internal DIT
• BNC connector for an external clock input
• BNC connector for DAC output
Digital In
OPT
BNC
MCLK
* Circuit diagram and PCB layout are attached at the end of this manual.
<KM087902>
GENERAL DESCRIPTION
AK4344 Evaluation Board
FUNCTION
DGND
74LVC541
AK4112B
(DIR)
Clock
Divider
Generator
10pin Header
DSP Data
Figure 1. AKD4344-A Block Diagram
AKD4344-A
AK4344 Evaluation Board Rev.2
VCC
VDD AGND
AK4344
- 1 -
[AKD4344-A]
Digital Out
OPT
Analog Out
LOUT
ROUT
2007/07

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Summary of Contents for AKM AKD4344-A

  • Page 1 AK4344 Evaluation Board Rev.2 GENERAL DESCRIPTION The AKD4344-A is an evaluation board for the AK4344, 24bit and 96kHz DAC with DIT for portable and home audio systems. The AKD4344-A has the interface with AKM’s A/D converter evaluation boards and the interface with digital audio systems via optical connector. Therefore, it is easy to evaluate the AK4344.

  • Page 2: Operation Sequence

    2) D/A part evaluation using 10-pin connector on the AKM’s A/D evaluation board Use PORT3 (DSP). It is able to evaluate the AK4344, connecting the 10-pin connector on the AKM’s A/D evaluation board and PORT3 (DSP) via 10-line flat cable. MCLK, BICK, LRCK and SDTI1 are sent from the A/D converter evaluation board to the AKD4344 through PORT3 (DSP) via 10-line flat cable.
  • Page 3 [AKD4344-A] Other Jumper pins set up (1) JP15 (VDD): VDD and VCC OPEN: Separated SHORT: Common. (The connector “VCC” can be open.) <Default> By opening the connector “VCC”, shorting JP15 (VDD) and supplying 3.3V to the connector “VDD”, the connector “VDD” can supply 3.3V to all circuits...
  • Page 4 [AKD4344-A] Example for External Clock setting Refer to the following setting when MCLK, BICK and LRCK are supplied to the AK4344 from J1 (EXT). Mode MCLK JP11 (DIV) JP9 (CLK) JP13 (LRFS) 512fs = 4.096MHz 768fs = 6.144MHz 8kHz 1024fs = 8.192MHz 1536fs = 12.288MHz...
  • Page 5 [AKD4344-A] DIP Switch set up [SW3]: Setting the audio data format of the AK4112B (ON=“H”, OFF=“L”) Mode SW3-3 SW3-2 SW3-1 SDTI Format DIF2 DIF1 DIF0 16bit, LSB justified 24bit, LSB justified 24bit, MSB justified 24bit, I S Compatible Default Table 2. SW3: Audio Data Format of AK4112B Note.

  • Page 6: Analog Output Circuit

    The AKD4344-A can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT4 (uP-I/F) to PC by 10-line flat cable packed with the AKD4344-A. Take care of the direction of connector. There is a mark at pin#1. The pin layout of PORT4 as shown Figure 3.
  • Page 7 1. Set up the AKD4344-A according to the Operating Sequence located on page 2. 2. Connect IBM-AT compatible PC with AKD4344-A by 10-line type flat cable (packed with AKD4344-A). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP.
  • Page 8 [AKD4344-A] Explanation of each dialog 1. [Write Dialog] : Dialog to write data by mouse operation There are dialogs corresponding to each register. Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes “H”...

  • Page 9: Save] And [Open]

    [AKD4344-A] 4. [Save] and [Open] 4-1. [Save] Save the current register setting data. The extension of file name is “akr”. (Operation flow) (1) Click [Save] Button. (2) Set the file name and push [Save] Button. The extension of file name is “akr”.
  • Page 10 [AKD4344-A] 5. [Function3 Dialog] The sequence of register setting can be set and executed. (1) Click [F3] Button. (2) Set the control sequence. Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be paused.
  • Page 11 [AKD4344-A] 6. [Function4 Dialog] The sequence that is created on [Function3] can be assigned to buttons and executed. When [F4] button is clicked, window Figure as shown in opens. Figure 5. [F4] window <KM087902> 2007/07 - 11 -...
  • Page 12 [AKD4344-A] 6-1. [OPEN] buttons on left side and [START] buttons (1) Click [OPEN] button and select the sequence file (*.aks). Figure The sequence file name is displayed as shown in Figure 6. [F4] window(2) (2) Click [START] button, then the sequence is executed.
  • Page 13 [AKD4344-A] 7. [Function5 Dialog] The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. When Figure [F5] button is clicked, the following window as shown in opens. Figure 7. [F5] window 7-1.

  • Page 14: Measurement Results

    [AKD4344-A] MEASUREMENT RESULTS [Measurement condition] • Measurement unit : Audio Precision, System Two Cascade • MCLK : 512fs (fs=44.1KHz) / 256fs (fs=96KHz) • BICK : 64fs • fs : 44.1kHz / 96kHz • BW : 20Hz~20KHz (fs=44.1kHz) / 20Hz~40KHz (fs=96kHz) •...
  • Page 15 [AKD4344-A] [DAC Plot: fs=44.1kHz] THD+N vs. Input Level 06/18/07 09:30:43 fs=44.1kHz, fin=1kHz -100 -140 -130 -120 -110 -100 dBFS Figure 1. THD+N vs. Input Level (fin=1KHz) THD+N vs. Input Freqency 06/18/07 09:28:48 fs=44.1kHz, fin=0dBFs -100 Figure 2. THD+N vs. Input Frequency (Input Level=0dBFS) <KM087902>...
  • Page 16 [AKD4344-A] [DAC Plot: fs=44.1kHz] Linearity 06/18/07 09:35:13 fs=44.1kHz, fin=1kHz -100 -110 -120 -130 -140 -140 -130 -120 -110 -100 dBFS Figure 3. Linearity (fin=1KHz) Freqency Response 06/18/07 09:49:36 fs=44.1kHz, fin=0dBFs +0.9 +0.8 +0.7 +0.6 +0.5 +0.4 +0.3 +0.2 +0.1 -0.1 -0.2...
  • Page 17 [AKD4344-A] [DAC Plot: fs=44.1kHz] Crosstalk 06/18/07 09:56:53 fs=44.1kHz -100 -106 -112 -118 -124 -130 Figure 5. Crosstalk (fin=1KHz, Input Level=0dBFS/no-input) 06/18/07 10:07:31 fs=44.1kHz, fin=0dBFs,1kHz -100 -110 -120 -130 -140 -150 -160 Figure 6. FFT Plot (fin=1KHz, Input Level=0dBFS) <KM087902> 2007/07...
  • Page 18 [AKD4344-A] [DAC Plot: fs=44.1kHz] 06/18/07 10:08:53 fs=44.1kHz, fin=-60dBFs,1kHz -100 -110 -120 -130 -140 -150 -160 Figure 7. FFT Plot (fin=1KHz, Input Level=−60dBFS) FFT Noise floor 06/18/07 10:09:30 fs=44.1kHz -100 -110 -120 -130 -140 -150 -160 Figure 8. FFT Plot (no-input) <KM087902>...
  • Page 19 [AKD4344-A] [DAC Plot: fs=96kHz] FFT Out-of-band Noise 06/18/07 10:32:35 fs=44.1kHz -100 -110 -120 -130 -140 -150 -160 100k Figure 9. FFT Plot (out-of-band-noise) THD+N vs Input Level fs=96KHz, fin=1KHz -72.5 -77.5 -82.5 -87.5 -92.5 -97.5 -100 -102.5 -105 -107.5 -110 -112.5...
  • Page 20 [AKD4344-A] [DAC Plot: fs=96kHz] THD+N vs Input Frequency fs=96KHz, Input Level=0dBFS -72.5 -77.5 -82.5 -87.5 -92.5 -97.5 -100 -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120 Figure 11. THD+N vs. Input Frequency (Input Level=0dBFS) Linearity 06/18/07 10:46:53 fs=96kHz -100 -110...
  • Page 21 [AKD4344-A] [DAC Plot: fs=96kHz] Frequency response 06/18/07 10:49:42 fs=96kHz +0.9 +0.8 +0.7 +0.6 +0.5 +0.4 +0.3 +0.2 +0.1 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 2.5k 7.5k 12.5k 17.5k 22.5k 27.5k 32.5k 37.5k Figure 13. Frequency Response (Input Level=0dBFS)
  • Page 22 [AKD4344-A] [DAC Plot: fs=96kHz] 06/18/07 10:24:00 fs=96kHz, fin=0dBFs,1kHz -100 -110 -120 -130 -140 -150 -160 Figure 15. FFT Plot (fin=1KHz, Input Level= 0dBFS) 06/18/07 10:28:58 fs=96kHz, fin=-60dBFs,1kHz -100 -110 -120 -130 -140 -150 -160 Figure 16. FFT Plot (fin=1KHz, Input Level= −60dBFS) <KM087902>...
  • Page 23 [AKD4344-A] [DAC Plot: fs=96kHz] FFT Noise floor 06/18/07 10:29:37 fs=96kHz -100 -110 -120 -130 -140 -150 -160 Figure 17. FFT Plot (no-input) FFT Out-of-band Noise 06/18/07 10:30:24 fs=96kHz -100 -110 -120 -130 -140 -150 -160 100k Figure 18. FFT Plot (out-of-band-noise) <KM087902>...

  • Page 24: Important Notice

    [AKD4344-A] Revision History Date Manual Board Reason Contents (yy/mm/dd) Revision Revision 07/03/15 KM087900 First Edition 07/04/17 KM087901 Circuit Change U1 (AK4344): 28pin SOP 16pin TSSOP Change Remove jumper pins: JP1 (TEST2), JP3 (TEST1). TEST2 is open. Connect TEST1 to GND.
  • Page 25 AK4344-LOUT LOUT AK4344-CCLK CCLK ROUT AK4344-ROUT AK4344-CDTI CDTI TEST1 AK4344 AK4344 Title Title Title AKD4344-A AKD4344-A AKD4344-A Size Size Size Document Number Document Number Document Number AK4344 AK4344 AK4344 Tuesday, June 12, 2007 Tuesday, June 12, 2007 Tuesday, June 12, 2007...
  • Page 26 AK4112B-LRCK AVSS LRCK AK4112B-ERF AK4112B-RX1 AK4112B-DIF0 RX2/DIF0 FS96 AK4112B-DIF1 RX3/DIF1 AK4112B-DIF2 RX4/DIF2 AUTO AK4112B AK4112B Title Title Title AKD4344-A AKD4344-A AKD4344-A Size Size Size Document Number Document Number Document Number AK4112B AK4112B AK4112B Date: Date: Date: Sheet Sheet Sheet Thursday, May 31, 2007...
  • Page 27 JP7 (3x1) AK4344-LRCK LRCK AK4112B-LRCK 74LVC541A-PDN AK4344-PDN PORT3 PORT3-SDTI2 JP8 (3x1) JP8 (3x1) AK4344-SDTI2 SDTI2 74LVC541A 74LVC541A Title Title Title AKD4344-A AKD4344-A AKD4344-A Size Size Size Document Number Document Number Document Number 74LVC541A 74LVC541A 74LVC541A Date: Date: Date: Sheet Sheet...
  • Page 28 74HC14 74HC14 LOAD 74HC14 74HC14 74HC14 74HC14 74HC14 74HC14 74HC14 74HC14 Title Title Title AKD4344-A AKD4344-A AKD4344-A Size Size Size Document Number Document Number Document Number External Master Clock Divider External Master Clock Divider External Master Clock Divider Date: Date:...
  • Page 29 100K CCLK CDTI CDTO 74HCT04 74HCT04 Title Title Title uP-I/F (short) (short) AKD4344-A AKD4344-A AKD4344-A Size Size Size Document Number Document Number Document Number Input Output for Digital Analog Input Output for Digital Analog Input Output for Digital Analog Date:...

  • Page 30: Power Supply

    0.1u 0.1u 0.1u 0.1u 0.1u 0.1u (short) (short) JP16 JP16 AGND (2x1) (2x1) DGND Title Title Title AKD4344-A AKD4344-A AKD4344-A Size Size Size Document Number Document Number Document Number Power Supply Power Supply Power Supply Date: Date: Date: Sheet Sheet...