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AKM AK4558EN Manual

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The AKD4558-A is an evaluation board for AK4558, which is 24/32bit, CODEC including 2ch ADC and
2ch DAC. The control settings of this board may be controlled via USB port, allowing for easy A/D and
D/A evaluation. BNC connectors are used for the input and output of the analog signals. This board also
has a digital interface which can be connected to the digital audio system via optical connector.
 Ordering guide
AKD4558-A
 Clock generator circuit (AK4118A used)
 Compatible with 2types of digital audio interface
- Optical input (x1) / Optical output (x1)
- Pin header for external data source
 BNC connector for an external clock input
 ADC 2ch input, DAC 2ch output
 USB port and 10pin header for board control
* Circuit diagram and PCB layout are attached at the end of this manual.
<KM116603>
GENERAL DESCRIPTION
--
Evaluation board for
Control software included with package
Figure 1. AKD4558-A Block Diagram
AK4558 Evaluation Board Rev.3
AK4558
FUNCTION
- 1-
[AKD4558-A]
AKD4558-A
2022/01

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  • Page 1 [AKD4558-A] AKD4558-A AK4558 Evaluation Board Rev.3 GENERAL DESCRIPTION The AKD4558-A is an evaluation board for AK4558, which is 24/32bit, CODEC including 2ch ADC and 2ch DAC. The control settings of this board may be controlled via USB port, allowing for easy A/D and D/A evaluation.

  • Page 2: Evaluation Board Diagram

    [AKD4558-A] Evaluation Board Diagram  Board Diagram J700 J706 J703 J701 J702 J705 J704 PORT600 SW500 J200 J201 PORT2 J202 PORT1 J203 J400 SW501 SW300 SW401 SW400 AKD4558-A Board Diagram Figure 2.  Description (1) U1 ( AK4558 ) 24/32bit,2ch A/D Converter, 2ch D/A Converter. (2) J200, J201, J202, J203 ( Analog data ) J200, J201 BNC connector : Analog Input for LIN, RIN.
  • Page 3 [AKD4558-A] (8) SW300 ( Dip-switch ) DIP type switch. Sets clock and audio format of AK4118A. DIF[2:0] used to set audio interface format and OCKS[1:0] used to master clock frequency. (9) SW500, SW501 ( Dip-switch ) DIP type switch. Sets clock and audio format and filter of AK4558. (10) SW400 ( Toggle switch ) Toggle type-switch PDN for AK4558.
  • Page 4 [AKD4558-A] Evaluation Board Manual  Operation sequence [1] Power supply line settings [2] Jumped pins settings [3] DIP switches settings [4] Toggle switches settings [5] Data format settings [6] Register control (Serial control) [7] Evaluation modes <KM116603> 2022/01 - 4-...
  • Page 5 [AKD4558-A] [1] Power supply line settings (1-1) Power supply settings : Used the regulator (T1,T2,T3) <Default> Set up the power supplied lines. * Each supply line should be distributed from the power supply unit. Name Color Setting (Typ) Function Comments Default Settings J700 +12V...
  • Page 6 [AKD4558-A] (1-2) About jumper for power supply The roles of the jumper for each power supply supplied from the regulator are as follows. Connection of the jumper for power supply : Name Function Comments Default Settings JP700 AVDD1 Select regulator power supply AVDD for AK4558: REG : or jack for AVDD1...
  • Page 7 [AKD4558-A] [2] Jumped pins settings Names Default Functions JP100 VDD18SEL Short Select Short / Open VDD18. Open: VDD18 pin of AK4558 open. Short: VDD18 pin of AK4558 input 1.8V. (default) JP400 Open Open: No input (default) Short: External MCLK(JACK:J400 EXT) input. JP401 BICK-SEL Select input to AK4558 (U1) BICK Buffer...
  • Page 8 [AKD4558-A] JP501 PMADR/SDASEL Select input to AK4558 (U1) PMADR/SDA SDA: SDA signal input to AK4558. (default) PMADR: PMADR signal of SW500 input to AK4558. JP502 PMDAL/CAD0SEL CAD0 Select input to AK4558 (U1) PMDAL/CAD0 CAD0: CAD0 signal input to AK4558. (default) PMDAL: PMDAL signal of SW500 input to AK4558.
  • Page 9 [AKD4558-A] [3] DIP switches settings (3-1). Setting for SW300 (Sets AK4118 (U2) audio format and master clock setting) Switch Name Function default DIF0 Set-up of DIF0 pin. (in parallel mode) DIF1 Set-up of DIF1 pin. (in parallel mode) DIF2 Set-up of DIF2 pin. (in parallel mode) OCKS1 Set-up of OCKS1 pin.
  • Page 10 [AKD4558-A] (3-2). Setting for SW500 (Sets AK4558 (U1) ) Switch Name Function default ADC Lch Power Management Pin in parallel control mode. (PS pin =”H”) PMADL L: ADC Lch Power Down H: Normal Mode ADC Rch Power Management Pin in parallel control mode. (PS pin =”H”) PMADR L: ADC Rch Power Down H: Normal Mode...
  • Page 11 [AKD4558-A] [4] Toggle switches settings Up=”H”, Down=”L” [SW401] ( Power Down (PDN) for AK4558): Power Down (PDN) Switch for AK4558 Reset AK4558 (U1) once by brining SW401 to “L” once upon power-up. Keep “H” when AK4558 is in use; keep “L” when AK4558 is not in use. [SW400] ( Power Down (PDN) for AK4118A): Power Down (PDN) Switch for AK4118A Reset AK4118A (U2) once by brining SW400 to “L”...
  • Page 12 [AKD4558-A] [5] Data format settings (5-1) Settings of Data Format (SDTI/SDTO) Audio Interface Format settings of SDTI/SDTO can be set change by switching CKS3-0. (5-1-1): Case1 : PS pin = “L” CKS3 pin CKS2 pin Mode Slave Mode Slave Mode default Slave Mode Master Mode...
  • Page 13 [AKD4558-A] [6] Register control (Serial control) AKD4558-A can be controlled via USB (serial port). Connect board to PC using the USB cable (PORT600 - serial) included with the AKD4558-A. The control software is packed with the evaluation board. The software operation sequence is included in the evaluation board manual.

  • Page 14: Evaluation Modes

    [AKD4558-A] [7] Evaluation modes (7-1) ADC (Analog  Digital)  Toggle switch setting: SW400 SW401 L→H L→H AK4118(U2) : Used AK4558(U1) : Used Table 11. Toggle switch setting  Start up Control Register Setting 1: Port Reset & Write Default. 2: Set Addr: 00h = “1D”...
  • Page 15 [AKD4558-A] Control Software Manual ■ Evaluation Board and Control Soft Settings 1. Set an evaluation board properly. 2. Connect a PC (IBM-AT compatible) and an evaluation board via a USB cable. The evaluation board recognized as HID (Human Interface Device) on the PC. It is not necessary to install a new driver.
  • Page 16 [AKD4558-A] ■ Operation Overview Function, register map and testing tool can be controlled by this control soft. These controls are selected by upper tabs. Buttons which are frequently used such as register initializing button “Write Default”, are located outside of the switching tab window.

  • Page 17: Reg]: Register Map

    [AKD4558-A] 1. [REG]: Register Map This tab is for a register writing and reading. Each bit on the register map is a push-button switch. Button Down indicates “H” or “1” and the bit name is in red (when read only it is in deep red). Button Up indicates “L”...
  • Page 18 [AKD4558-A] 1-1. [Write]: Data Writing Dialog It is for when changing two or more bits on the same address at the same time. Click [Write] button located on the right of the each corresponded address for a pop-up dialog box. When the checkbox is checked, the data will be “H”...

  • Page 19: Tool]: Testing Tools

    [AKD4558-A] 2. [Tool]: Testing Tools This tab screen is for the evaluation testing tool. Click button for each testing tool. Figure 6. Window of [Tool] <KM116603> 2022/01 - 19-...
  • Page 20 [AKD4558-A] 2-1. [Repeat Test]: Repeat Test Dialog Click [Repeat Test] button in the Test tab to open a repeat test dialog shown below. Repeat writing test can be executed by this dialog. Figure 7. Window of [ Repeat Test ] [Start] Button : Starts the repeat test.
  • Page 21 [AKD4558-A] 2-2. [Loop Setting]: Loop Dialog Click [Loop Setting] button in the Tool tab to open loop setting dialog as shown below. Writing test can be executed. Figure 8. Window of [ Loop ] [ OK ] Button : Starts the test. [ Cancel ] Button : Closes the dialog and finishes the process.

  • Page 22: Operating Suggestions

    [AKD4558-A] ■ Dialog Boxes 1. [All Req Write]: All Reg Write dialog box Click [All Reg Write] button in the main window to open register setting files. Register setting files saved by [SAVE] button can be applied. Figure 9. Window of [ All Reg Write ] [Open (left)]: Selects a register setting file (*.akr).
  • Page 23 [AKD4558-A] 2. [Data R/W]: Data R/W Dialog Box Click the [Data R/W] button in the main window for data read/write dialog box. Data write is available to specified address. Figure 10. Window of [ Data R/W ] [Address] Box: Input data address in hexadecimal numbers for data writing. [Data] Box : Input data in hexadecimal numbers.

  • Page 24: Sequence Setting

    [AKD4558-A] 3. [Sequence]: Sequence Dialog Box Click [Sequence] button to open register sequence setting dialog box. Register sequence can be set in this dialog box. Figure 11. Window of [Sequence ] ~ Sequence Setting ~ Set register sequence by following process bellow. Select a command Use [Select] pull-down box to choose commands.

  • Page 25: Control Buttons

    [AKD4558-A] Input sequence [Address]: Data address [Data]: Writing data [Mask]: Mask [Data] box data is ANDed with [Mask] box data. This is the actual writing data. When Mask = 0x00, current setting is hold. When Mask = 0xFF, the 8bit data which is set in the [Data] box is written. When Mask =0x0F, lower 4bit data which is set in the [Data] box is written.
  • Page 26 [AKD4558-A] 4. [Sequence(File)]: Sequence Setting File Dialog Box Click [Sequence(File)] button to open sequence setting file dialog box. Those files saved in the “Sequence setting dialog” can be applied in this dialog. Figure 12. Window of [ Sequence(File) ] [Open (left)]: Opens a sequence setting file (*.aks). [Start]: Executes the sequence by the setting of selected file.

  • Page 27: Measurement Results

    [AKD4558-A] Measurement Results [Measurement condition] ・Measurement unit : Audio Precision, SYS-2722 (No.00122) : PSIA-2722 (No00096) ・MCKI : 256fs/128fs (12.288MHz/24.576MHz) ・BICK : 64fs ・fs : 48kHz/96kHz/192kHz ・Bit : 24bit ・Measurement Mode : Slave Mode ・Power Supply : VOP+(12V)=12V, GND AVDD=3.3V (Regulator), TVDD=VDD18=1.8V (Regulator) ・Input Frequency : 1kHz ・Measurement Frequency...
  • Page 28 [AKD4558-A] [Plot Data] ADC (LIN/RIN => ADC) ADC (fs = 48kHz); LIN/RIN => ADC => SDTO AK4558 FFT ADC (LIN/RIN:L/R) [fs=48kHz, fin=1kHz, -1dBFS] -100 -110 -120 -130 -140 -150 -160 -170 -180 Figure 14. ADC – FFT (-1dBFS) [fs = 48kHz] AK4558 FFT ADC (LIN/RIN:L/R) [fs=48kHz, fin=1kHz, -60dBFS] -100 -110...
  • Page 29 [AKD4558-A] AK4558 FFT ADC (LIN/RIN:L/R) [fs=48kHz, fin=1kHz, no signal] -100 -110 -120 -130 -140 -150 -160 -170 -180 Figure 16. ADC – FFT (No Signal) [fs = 48kHz] AK4558 THD+N vs Amplitude ADC (LIN/RIN:L/R) [fs=48kHz, fin=1kHz] -100 -105 -110 -115 -120 -140 -120...
  • Page 30 [AKD4558-A] AK4558 THD+N vs Input Frequency ADC (LIN/RIN:L/R) [fs=48kHz, -1dBFS] R R R R R R R R R R R R R R R RR R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R RR R R R R R R RR R R R R R R R R R R R R R R R R R R R -100 -105...
  • Page 31 [AKD4558-A] AK4558 Frequency Response ADC (LIN/RIN:L/R) [fs=48kHz, -1dBFS] -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1.1 -1.2 -1.3 -1.4 -1.5 -1.6 -1.7 -1.8 -1.9 Figure 20. ADC – Frequency Response [fs = 48kHz] AK4558 Crosstalk ADC (LIN/RIN:L/R) [fs=48kHz, -1dBFS] -100 -105 -110...
  • Page 32 [AKD4558-A] DAC (SDTI => DAC) DAC (fs = 48kHz); SDTI => DAC => LOUT/ROUT AK4558 FFT DAC (LOUT/ROUT) [fs=48kHz, fin=1kHz, 0dBFS] -100 -110 -120 -130 -140 -150 -160 -170 -180 Figure 22. DAC – FFT (0BFS) [fs = 48kHz] AK4558 FFT DAC (LOUT/ROUT) [fs=48kHz, fin=1kHz, -60dBFS] -100 -110 -120...
  • Page 33 [AKD4558-A] AK4558 FFT DAC (LOUT/ROUT) [fs=48kHz, fin=1kHz, no signal] -100 -110 -120 -130 -140 -150 -160 -170 -180 Figure 24. DAC – FFT (No Signal) [fs = 48kHz] AK4558 THD+N vs Amplitude DAC (LOUT/ROUT) [fs=48kHz, fin=1kHz] -100 -105 -110 -115 -120 -140 -120...
  • Page 34 [AKD4558-A] AK4558 THD+N vs Input Frequency DAC (LOUT/ROUT) [fs=48kHz, 0dBFS] -100 -105 -110 -115 -120 Figure 26. DAC1 – THD+N vs. Input Frequency [fs = 48kHz] AK4558 Linearity DAC (LOUT/ROUT) [fs=48kHz,fin=1kHz] -100 -110 -120 -130 -140 -140 -120 -100 dBFS Figure 27.
  • Page 35 [AKD4558-A] AK4558 Frequency Response DAC (LOUT/ROUT) [fs=48kHz, 0dBFS] +0.9 +0.8 +0.7 +0.6 +0.5 +0.4 +0.3 +0.2 +0.1 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 Figure 28. DAC – Frequency Response [fs = 48kHz] AK4558 Crosstalk DAC (LOUT/ROUT) [fs=48kHz, 0dBFS] -100 -105 -110...

  • Page 36: Revision History

    [AKD4558-A] REVISION HISTORY Date Manual Board Reason Page Contents (YY/MM/DD) Revision Revision 14/04/09 KM116600 First edition 14/10/07 KM116601 Modification P27-P35 Update of measurement results. 15/04/02 KM116602 Modification P27-P35 Update of measurement results. Board revision update(Rev.2→3). － 22/01/17 KM116603 Modification Change of U1. <KM116603>...

  • Page 37: Important Notice

    AKM or any third party with respect to the information in this document. You are fully responsible for use of such information contained in this document in your product design or applications.
  • Page 38 PMDAR/CAD1 PMDAL/CAD0 PMADR/SDA LOPS PMADL/SCL LDOE PDN1 7pin_3 C109 Cap Dip open + 1pin Socket (C109) open AVSS R129 R128 R111 LDOE=L : VDD18=1.8V(input), TVDD=1.8V(Input) -> VDD18SEL=Short, TVDDSEL=TVDD18V LDOE=H : VDD18=1.8V(Output), TVDD=3.3V(Input) -> VDD18SEL=Open, TVDDSEL=TVDD33V 7pin_4 7pin_2 JP100 VDD18SEL R119 VDD18 LIN1 VDD18...
  • Page 39 J200 C200 LIN1 Cap(C200,C201) -> +,-Check AVSS J201 C201 RIN1 AVSS J202 R202 LOUT LOUT1 C202 C204 R200 open AVSS Cap(C202,C203) -> +,-Check J203 AVSS AVSS R203 ROUT ROUT1 C203 C205 R201 open AVSS AVSS AVSS + 1pin Socket (C204,C205,R200,R201) Title Title Title...
  • Page 40 L300 47uH D33V D33V PORT1 C300 C301 0.1u TP300 PLRx DGND C305 R300 C306 0.1u DGND R306 C307 0.47u IPS0/RX4 INT0 INT0 OCKS0/CSN/CAD0 OCKS0 D33V OCKS1 DIF0/RX5 OCKS1/CCLK/SCL SW300 TEST2 CM1/CDTI/SDA D33V DIF1/RX6 CM0/CDTO/CAD1 DGND OCKS0 VSS1 PDN2 OCKS1 AK4118A DIF2/RX7 C310 X300...
  • Page 41 U400 JP401 TP400 MCLK-256fs MCLK/2 JP404 BICK MCLK/4 MCLK/8 BICK0 MCLK/16 BICK-PHASE DIR-BICK PORT3 D33V BICK-SEL TP401 LRCK JP402 MCLK/128 DGND LRCK0 MCLK/256 C400 0.1u MCLK/512 74HC4040 DIR-LRCK PORT3 LRCK-SEL DGND JP405 TP404 D33V SDTI DIR-SDTO PORT4 D33V SDTI0 U401 SDTI-SEL TP406 TP403...
  • Page 42 U500 U503 R500 R522 TVDD -> D33V (SDTO) SDTO1 PDN10 PDN1 SDTO D33V -> TVDD (PDN1,MCLK,SDTI,TDMI) R523 CKS30 R501 MCLK CKS31 R524 MCLK0 SDTI CKS20 CKS21 R525 R502 TDMI/I R504 R526 SDTI0 R505 R527 Res 0ohm Chip TVDD D33V R503 R506 R528 R523 - R529...
  • Page 43 R608 TVDD 100k 0.1u 4.7k C610 R602 C600 2.2u DGND R609 R610 TP608 C611 0.1u VREF2 VREF1 TP609 SCL2 SCL1 SDA2 SDA1 DGND PCA9306DP1 C602 C604 C601 1u DGND DGND C603 C605 0.1u 0.1u JP600 SILK-SCREEN 1:VDD 2:MCLR 3:PGD USB-RST 4:PGC MCLR_N/Vpp/RE3 C606...
  • Page 44 J700 +12V C700 +12V-->+3.3V TP700 LT1963AEST-3.3 AVDD1 JP700 R700 AVDD1 C701 C702 C704 J701 AVDD1 C703 AVSS AVDD1 0.1u 0.1u AVDD1-SEL AVSS AVSS AVSS AVSS AVSS C713 TP701 JP701 AVSS TVDD TVDDVOL-SEL REG3.3V TVDD JP702 R701 TVDD REG1.8V J702 TVDD TVDD-SEL +12V-->+1.8V LT1963AEST-1.8...
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