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AKM AKD4497-SA Instruction Manual

Ak4497 evaluation board rev.0
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The AKD4497-SA is an evaluation board for the AK4497 (Premium 32-bit 2ch DAC) that supports
Network-Audios, USB-DAC, Car-Audio Systems. It integrates differential output low pass filters, allowing
quick evaluation with digital audio interface.
■
Ordering Guide
AKD4497-SA -- Evaluation Board for the AK4497
 10-pin Header for Serial Control
 Low Pass Filters (LPF) for Pre-amplifier Outputs
 Digital Audio Interface (AK4118A)
COAX In
Opt In
Note 1. Circuit schematics are attached at the end of this document.
< KM122101>
1. General Description
IBM-AT compatible computers and control software are
(A USB I/F board for
included in this package.
DIR
AK4118A
Figure 1. AKD4497-SA Block Diagram
AK4497 Evaluation Board Rev.0
)
2. Function
2nd Order LPF
AK4497
(Note
- 1-
[AKD4497-SA]
AKD4497-SA
Lch
Rch
1)
2020/03

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Summary of Contents for AKM AKD4497-SA

  • Page 1 AK4497 Evaluation Board Rev.0 1. General Description The AKD4497-SA is an evaluation board for the AK4497 (Premium 32-bit 2ch DAC) that supports Network-Audios, USB-DAC, Car-Audio Systems. It integrates differential output low pass filters, allowing quick evaluation with digital audio interface.

  • Page 2: Appearance Diagram

    PORT201 Filter Block2-2 Regulator Block2 J403 Figure 2. AKD4497-SA Outline View ■ Description (1) Connectors for Power Supply and GND ( J500 / +15V, J404 / -15V, J501 / GND ) Connectors for power supply and the ground Power Supply Connections Refer to the “...
  • Page 3 [AKD4497-SA] (5) EXT PORT (PORT200) 10-pin Header for External Interfacing External digital audio devices are interfaced to this port. Set the R202, R204, R206 and R208 resistances to short when using the PORT200 (EXT). Function Function MCLK BICK SDTO LRCK Table 1.

  • Page 4: Operation Sequence

    [AKD4497-SA] 4. Operation Sequence  Operation sequence 1). Power Supply Connections 2). Evaluation Mode 3). ■ Resistance and DIP Switch Settings 4). Power-up ■ Power Supply Connections Default Name Color Voltage Content Note Setting MVDD (AK4497), J500 +10 to +15V This jack is always needed.
  • Page 5 [AKD4497-SA] ■ Evaluation Mode (1) Evaluation with a DIR (COAX) < Default > The J300 (COAX) jack is used in this mode. The DIR (AK4118A) generates MCLK, BICK, LRCK and SDATA from the input data of the J300 (COAX) connector.
  • Page 6 [AKD4497-SA] ■ Resistance and DIP Switch Settings (1) Resistance Settings [R201 / R202 (MCLK)]: MCLK pin input select R201 short: MCLK signal is supplied from the DIR (AK4118A). < Default > R202 short: MCLK signal is supplied from the PORT200.
  • Page 7 [AKD4497-SA] (2) DIP Switch Setting Upside is ON (“H”), and Downside is OFF (“L”). [SW300]: Setting of the AK4118A Name ON (“H”) OFF (“L”) Default OCKS1 Master Clock setting for AK4118A OCKS0 Refer to Table 5. Table 3. SW300 Setting...
  • Page 8 [SW200] (PDN): DAC / DIR Reset control. It must be set to “H” during operation. After power-up, the AKD4497-SA must be reset once. To reset the AKD4497-SA, set the SW200 toggle switch to “L” and power down the AK4497 and the AK4118A. Then, release the power-down by setting back the SW200 to “H”.
  • Page 9 (Note Note Note 2. The AKD4497-SA accepts only one AKDUSBIF-B at one time. It does not operate if two or more AKDUSBIF-Bs are connected. Note 3. Connect the 10pin Flat Cable as the red line of the cable is connected to the 1 pin of the 10pin Header of the board.
  • Page 10 PC. 4. Insert the CD-ROM labeled “AKD4497-SA Evaluation Kit” into the CD-ROM drive. 5. Access the CD-ROM drive and double-click the icon “AKD4497-SA.exe” to open the control program. 6. Begin evaluation by following the procedure below.
  • Page 11 [AKD4497-SA] ■ Operation Overview Register map is controlled by this control software. Frequently used buttons, such as the register initializing button “Write Default”, are located outside of the switching tab window. Refer to the “■ Dialog Box” section for details of each dialog box setting.
  • Page 12 [AKD4497-SA] ■ Tab Functions 1. [REG] Tab: Register Map This tab is for register read and write. Each bit on the register map is a push-button switch. Button Down indicates “1” and the bit name is shown in red (when read-only the name is shown in dark red).
  • Page 13 [AKD4497-SA] [Write] button: Data Write Dialog Select the [Write] button located on the right of the each corresponding address when changing two or more bits on the same address simultaneously. Click the [Write] button for the register pop-up dialog box shown below.

  • Page 14: Operating Suggestions

    [AKD4497-SA] ■ Dialog Box 1. [All Reg Write]: All Register Write dialog box Click [All Reg Write] button in the main window to open register setting file window shown below. Register setting files saved by [SAVE] button may be applied.
  • Page 15 [AKD4497-SA] 2. [Data R/W]: Data R/W Dialog Box Click the [Data R/W] button in the main window for data read/write dialog box. Data is written to the specified address. Figure 9. [Data R/W] Window [Address] Box: Input data write address in hexadecimal numbers.

  • Page 16: Sequence Setting

    [AKD4497-SA] 3. [Sequence]: Sequence Dialog Box Click the [Sequence] button in the main window for Sequence dialog box. Register sequence may be set and executed. Figure 10. [Sequence] Window ~ Sequence Setting ~ Set register sequence according to the following process.

  • Page 17: Control Buttons

    [AKD4497-SA] 2. Input Sequence [Address]: Data Address [Data]: Write Data [Mask]: Mask This value “ANDed” with the write data becomes the input data. When Mask = 0x00, current setting is hold. When Mask = 0xFF, the 8bit data which is set in the [Data] box is written.
  • Page 18 [AKD4497-SA] 4. [Sequence(File)]: Sequence(File) Dialog Click the [Sequence(File)] button to open sequence setting file dialog box shown below. Files saved in the “Sequence setting dialog” can be applied in this dialog. Figure 11. [Sequence (File)] Window [Open (left)] button: Select a sequence setting file (*.aks) [Start ] button: Execute the sequence by the setting of selected file.
  • Page 19 [AKD4497-SA] 6. Measurement Results [Measurement condition]  Measurement unit : Audio Precision APX 555 Audio Analyzer  MCLK : 256fs (44.1 kHz), 256fs (96 kHz), 128fs (192 kHz)  BICK : 64fs  fs : 44.1kHz, 96kHz, 192kHz  Bit : 24bit ...
  • Page 20 [AKD4497-SA] ■ Capacitance between the VREFH pin and the VREFL pin Distortion (THD+N) can be improved by increasing the capacitance of a capacitor between the VREFH pin and the VREFL pin. Applicable capacitors are C108 and C111 in the circuit schematic.
  • Page 21 [AKD4497-SA] [Plots] fs = 44.1 kHz AK4497 THD+N vs. Input Level AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz Figure 14. THD+N vs. Input Level AK4497 THD+N vs. Input Frequency AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz Figure 15. THD+N vs. Input Frequency < KM122101> 2020/03 - 21-...
  • Page 22 [AKD4497-SA] fs = 44.1 kHz AK4497 Linearity AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz Figure 16. Linearity AK4497 Frequency Response AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz Figure 17. Frequency Response < KM122101> 2020/03 - 22-...
  • Page 23 [AKD4497-SA] fs = 44.1 kHz AK4497 Crosstalk AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz Figure 18. Crosstalk AK4497 FFT (0dBFS Input) AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz Figure 19. FFT (0dBFS Input) < KM122101> 2020/03 - 23-...
  • Page 24 [AKD4497-SA] fs = 44.1 kHz AK4497 FFT ( -60dBFS Input) AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz Figure 20. FFT (-60dBFS Input) AK4497 FFT ( No Signal Input) AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz Figure 21. FFT (No Signal Input) < KM122101> 2020/03 - 24-...
  • Page 25 [AKD4497-SA] fs = 96 kHz AK4497 THD+N vs. Input Level AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz Figure 22. THD+N vs. Input Level AK4497 THD+N vs. Input Frequency AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz Figure 23. THD+N vs. Input Frequency < KM122101> 2020/03 - 25-...
  • Page 26 [AKD4497-SA] fs = 96 kHz AK4497 Linearity AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz Figure 24. Linearity AK4497 Frequency Response AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz Figure 25. Frequency Response < KM122101> 2020/03 - 26-...
  • Page 27 [AKD4497-SA] fs = 96 kHz AK4497 Crosstalk AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz Figure 26. Crosstalk AK4497 FFT (0dBFS Input) AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz Figure 27. FFT (0dBFS Input) < KM122101> 2020/03 - 27-...
  • Page 28 [AKD4497-SA] fs = 96 kHz AK4497 FFT (-60dBFS Input) AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz Figure 28. FFT (-60dBFS Input) AK4497 FFT (No Signal Input) AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz Figure 29. FFT (No Signal Input) < KM122101> 2020/03 - 28-...
  • Page 29 [AKD4497-SA] fs = 192 kHz AK4497 THD+N vs. Input Level AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz Figure 30. THD+N vs. Input Level AK4497 THD+N vs. Input Frequency AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz Figure 31. THD+N vs. Input Frequency < KM122101> 2020/03 - 29-...
  • Page 30 [AKD4497-SA] fs = 192 kHz AK4497 Lnearity AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz Figure 32. Linearity AK4497 Frequency Response AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz Figure 33. Frequency Response < KM122101> 2020/03 - 30-...
  • Page 31 [AKD4497-SA] fs = 192 kHz AK4497 Crosstalk AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz Figure 34. Crosstalk AK4497 FFT (0dBFS Input) AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz Figure 35. FFT (0dBFS Input) < KM122101> 2020/03 - 31-...
  • Page 32 [AKD4497-SA] fs = 192 kHz AK4497 FFT (-60dBFS Input) AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz Figure 36. FFT (-60dBFS Input) AK4497 FFT (No Signal Input) AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz Figure 37. FFT (No Signal Input) < KM122101> 2020/03 - 32-...
  • Page 33 [AKD4497-SA] 7. Revision History Date Manual Board Reason Page Contents (y/m/d) Revision Revision 15/10/30 KM122100 First Edition Change setting. 20/03/09 KM122101 Change Table 6. Digital Filter Setting < KM122101> 2020/03 - 33-...

  • Page 34: Important Notice

    AKM or any third party with respect to the information in this document. You are fully responsible for use of such information contained in this document in your product design or applications.
  • Page 35 R123 open TVDD R122 AVSS AVSS LDOE=L SLOW-S SD-S SSLOW-S - 35- Title Title Title AKD4497-SA AKD4497-SA AKD4497-SA Size Size Size Document Number Document Number Document Number AK4497 64LQFP AK4497 64LQFP AK4497 64LQFP Date: Date: Date: Wednesday, October 28, 2015...
  • Page 36 CCLK/SCL CCLK/SCL-10PIN CDTI/SDA CDTI/SDA-10PIN WCK-R1 SDA2 SDA1 uP-I/F AVSS Title Title Title - 36- AKD4497-SA AKD4497-SA AKD4497-SA Size Size Size Document Number Document Number Document Number Digital Signal for AK4497 Digital Signal for AK4497 Digital Signal for AK4497 Date: Date:...
  • Page 37 LRCK-DIR LRCK-DIR C306 C308 0.1u 0.1u MCLK-DIR MCLK-DIR C307 C309 VCC-R1 AVSS - 37- Title Title Title AKD4497-SA AKD4497-SA AKD4497-SA Size Size Size Document Number Document Number Document Number <AK4118A-DIR> <AK4118A-DIR> <AK4118A-DIR> Date: Date: Date: Wednesday, October 28, 2015 Wednesday, October 28, 2015...
  • Page 38 C418 OPA1612 AVSS AVSS R421 AVSS AVSS C803 AVSS R423 R422 AVSS Title Title Title - 38- AKD4497-SA AKD4497-SA AKD4497-SA AVSS Size Size Size Document Number Document Number Document Number External LPF External LPF External LPF Date: Date: Date: Thursday, October 29, 2015...
  • Page 39 C512 C516 R518 470u AVSS AVSS AVSS AVSS AVSS AVSS AVSS Title Title Title - 39- AKD4497-SA AKD4497-SA AKD4497-SA Size Size Size Document Number Document Number Document Number Puwer Supply Unit Puwer Supply Unit Puwer Supply Unit Date: Date: Date:...