Analog Devices ADXL180 iMEMS Manual page 6

ADXL180
1
Parameter
ASYNCHRONOUS MODE TIMING
Message Transmission Period
Phase 2, Mode 0
All Other Phases and Modes
Initialization State (Phase 1)
Device Data State (Phase 2)
Mode 0
Mode 1
Mode 2
Mode 3
Self-Test State (Phase 3)
3
Self-Test Time
Self-Test Interval
Self-Test Cycle
Auto-Zero Initialization State
(Phase 4)
SYNCHRONOUS MODE TIMING
Message Transmission Period
Initialization State1 (Phase 1)
Device Data State (Phase 2)
Mode 0
Mode 1
Mode 2
Mode 3
Self-Test State (Phase 3)
3
Self-Test Time
Self-Test Interval
Self-Test Cycle
Auto-Zero Initialization State
(Phase 4)
CLOCK
2
Period
5
PSRR
POWER SUPPLY HOLDUP TIME
THERMAL RESISTANCE, JUNCTION
TO CASE
1
All parameters are specified using the application circuit shown in Figure 6. C
2
All timing is driven from the on-chip master clock.
3 t and t are the times for six self-test cycles. This is the maximum number of cycles in the internal self-test mode.
ST STS
4
Transmission timing is defined by the internal system clock in asynchronous mode and by the synchronization pulse period in synchronous mode.
Symbol Min Typ
2
t 456
PM0
t 228
P
t 100
I
t 4.10
DD0
t 109
DD1
t 109
DD2
t 117
DD3
t 394
ST
t 21.9
STI
t 65.7
STC
t 14.94
AZ
4
t N/A
PS
t 100
I
t 9 × t
DD0s
t 480 × t
DD1s
t 480 × t
DD2s
t 512 × t
DD3s
t 1728 × t
STS
t 96 × t
STIS
t 288 × t
STCS
t 65,535 × t
AZs
t 1.05 1.0
CLK
<1
500
θ 30
JC
Max Unit
μs
μs
ms
ms
ms
ms
ms
ms
ms
ms
ms
sec
ms
ms
ms
PS
ms
PS
ms
PS
ms
PS
ms
PS
ms
PS
ms
PS
sec
PS
0.95 μs
LSB
ns
°C/W
= 10 nF, C = 100 nF.
B VDD
Rev. 0 | Page 6 of 56
Test Conditions/Comments
ADIFX compatible
See Figure 26
See Figure 26
See Figure 26
Determined by sync pulse, See Figure 12,
minimum t = t + t + t
PS SPD STD M
f = 1/t
CLK CLK
8-bit LSB; test conditions: V
BP
V = 500 mV p-p, 100 kHz to 1.1 MHz
AC
@ I = I
BUS SIG
+ t
B
− V = 7.00 V,
BN