Configuration Register Reference - Analog Devices ADXL180 iMEMS Manual

ADXL180

CONFIGURATION REGISTER REFERENCE

The following tables define the codes for each programmable field in the three configuration registers (CREG0, CREG1, and CREG2).
The default setting (unprogrammed state) of all bits in all configuration registers is zero. As a result, the default configuration of the
ADXL180 is compatible with the ADIFX operation mode and communication protocol as implemented in the ADXS101 satellite
transmitter.
Table 44. Configuration and User Data Bit Map
Configuration Configuration
Mode Register Mode Register
Address Name
0000b UREG
0001b CREG0
0010b CREG1
0011b CREG2
0100b...1001b NU
1010b CMEXIT
1011b SN0
1100b SN1
1101b SN2
1110b SN3
1111b MFGID
1 X = don't care.
2 NU = not used.
MSB
D7 D6 D5
UD7 UD6 UD5
UD8 BDE MD1
STI AZE SYEN
CUPRG CUPAR SCOE
X X X
1 0 0
SNB7 SNB6 SNB5
SNB15 SNB14 SNB13
SNB23 SNB22 SNB21
SNB31 SNB30 SNB29
SNPRG SNPAR REV2
Rev. 0 | Page 50 of 56
D4 D3 D2
UD4 UD3 UD2
MD0 FDLY DLY2
ADME ERC SVD
FC1 FC0 RG2
X X X
0 0 0
SNB4 SNB3 SNB2
SNB12 SNB11 SNB10
SNB20 SNB19 SNB18
SNB28 SNB27 SNB26
REV1 REV0 MFGID2
LSB
D1 D0
UD1 UD0
DLY1 DLY0
DAT MAN
RG1 RG0
X X
0 0
SNB1 SNB0
SNB9 SNB8
SNB17 SNB16
SNB25 SNB24
MFGID1 MFGID0