Application Layer: Communication Protocol State Machine; Adxl180 State Machine; Phase 1: Power-On-Reset Initialization; Phase 2: Device Data Transmission - Analog Devices ADXL180 iMEMS Manual

ADXL180

APPLICATION LAYER: COMMUNICATION PROTOCOL STATE MACHINE

Table 21. ADXL180 Start-Up Sequence Summary
Phase 1
Name Initialization
Function Power-on reset
Data Type None
Transmitted

ADXL180 STATE MACHINE

After power is applied and stabilized, the ADXL180 follows a
five-phase start-up sequence. The basic function of each phase
is fixed as shown in Figure 20. The five phases and the function
modes available in each phase are detailed in the following
sections.
RESET
RESET
PHASE 1 INITIALIZATION
RESET
PHASE 2
DEVICE DATA
RESET
PHASE 3
SELF-TEST
RESET
PHASE 4
AUTO-ZERO INITIALIZATION
RESET
PHASE 5
NORMAL OPERATION
RESET
Figure 20. ADXL180 Start-Up Sequence
Phase 2 Device Data
None
Serial number,
configuration and range
V > V
DD PUR
ERROR
ERROR
ERROR
ERROR
ERROR STATE
TRANSMIT ERROR CODE
Phase 3 Self-Test
Sequence self-test
pattern
Sensor, range, device OK
or delimiter

PHASE 1: POWER-ON-RESET INITIALIZATION

The power-on-reset initialization period is typically 100 ms
long. It is the period of time from when the internal reset signal
is deasserted until the beginning of Phase 2. This time allows
for circuit stabilization and entry into configuration mode. No
data is transmitted during Phase 1. No errors are reported
during Phase 1. Additionally, until phase 1 is exited, the device
does not respond to a transmitted sync pulse (see Table 21).

PHASE 2: DEVICE DATA TRANSMISSION

Overview
The device data consists of the serial number and configuration
data. Device data is transmitted during Phase 2. This data can
be transmitted in one of four configurable modes (see Table 22).
These modes are described in detail in the following sections.
The parity of all OTP memory blocks is continuously monitored
(provided that the block has been programmed) beginning at
the end of Phase 2. See the Parity Encoding section for more
details.
Table 22. MD Phase 2 Device Data Mode Select Codes
MD1 MD0
0 0
0 1
1 0
1 1
During Phase 2, if Mode 0, Mode 1, or Mode 2 is selected, the
device data is 8-bit data. If the 10-bit data mode is selected in
combination with Phase 2 Mode 0, Mode 1, or Mode 2, the 8-bit
device data is left justified in the 10-bit data field. The two LSBs
are held at zero (see Table 24).
Rev. 0 | Page 26 of 56
Phase 4 Auto-Zero
Initialization
Fast auto-zero
Sensor
Name Definition
Mode 0 ADIFX mode device data (default)
Mode 1 Range data only (range selection
limited)
Mode 2 8-bit coded device data
Mode 3 10-bit coded device data
Phase 5
Run Time
Slow auto-
zero
Sensor