Altera Arria GX Reference Manual
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Altera Arria GX Reference Manual

Altera Arria GX Reference Manual

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Arria GX Development Board
Reference Manual
101 Innovation Drive
San Jose, CA 95134
www.altera.com
Document Date:
October 2007

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Summary of Contents for Altera Arria GX

  • Page 1 Arria GX Development Board Reference Manual 101 Innovation Drive San Jose, CA 95134 www.altera.com Document Date: October 2007...
  • Page 2 Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al- tera products are protected under numerous U.S.

  • Page 3: Table Of Contents

    Contents About this Manual Revision History ............................v How to Contact Altera ..........................v Typographic Conventions........................vi Chapter 1. Overview Introduction............................. 1-1 General Description..........................1-1 Board Component Blocks......................... 1-2 Block Diagram ........................... 1-4 Handling the Board........................... 1-4 Chapter 2. Board Components Introduction.............................
  • Page 4 Contents Stratix Device Handbook, Volume 1 Altera Corporation Preliminary...

  • Page 5: About This Manual

    Note (1) Technical support www.altera.com/mysupport/ Technical training www.altera.com/training/ Technical training services custrain@altera.com Product literature www.altera.com/literature Product literature services literature@altera.com FTP site ftp.altera.com Note to table: You can also contact your local Altera sales office or sales representative. Altera Corporation Preliminary...

  • Page 6: Typographic Conventions

    How to Contact Altera Cyclone FPGA Device Handbook Typographic This document uses the typographic conventions shown below. Conventions Visual Cue Meaning Bold Type with Initial Command names, dialog box titles, checkbox options, and dialog box options are Capital Letters shown in bold, initial capital letters. Example: Save As dialog box.

  • Page 7: Chapter 1. Overview

    FPGA designs that interface with all components of the board. For information on setting up and powering up the Arria GX development board and using the kit’s demo software, please refer to the Arria GX Development Kit Getting Started User Guide.

  • Page 8: Board Component Blocks

    II CPLD and 16-bit page mode flash memory ● ■ Clocking circuitry The Arria GX development board uses three clock oscillators on ● the transceivers and user logic to support all Arria GX device protocols: • 62.5 MHz • 100.00 MHz •...
  • Page 9 Power multiplexer that allows the load to be shared by both the ● external supply and by the PCIe slot. Temperature sensing device and fan control circuit ● ■ Mechanical PCI Express short form factor (four 3.76 "x 6.600") ● Altera Corporation Reference Manual 1–3 October 2007 Arria GX Development Board...

  • Page 10: Block Diagram

    Handling the Board Block Diagram Figure 1–1 shows the functional block diagram of the Arria GX development board. Figure 1–1. Arria GX Development Board Block Diagram HSMC Port 512 MB Flash 3.3V CMOS 3.3V CMOS TX/RX LEDs MAX II User LEDs...

  • Page 11: Chapter 2. Board Components

    GERBER files for the Arria GX development board are installed in the Arria GX Development Kit documents directory. For information on powering up the development board and installing the demo software, refer to the Arria GX Development Kit Getting Started User Guide. Altera Corporation Reference Manual 2–1...

  • Page 12: Board Overview

    Board Overview Board Overview This section provides an overview of the Arria GX development board, including an annotated board image and component descriptions. Figure 2–1 shows the top view of the Arria GX development board. Figure 2–1. Top View of the Arria GX Development Board 2–2...
  • Page 13 Green LEDs that indicate the presence of 1.5 V, 2.5 V, and 1.2 V power. Configuration push button Push button to reconfigure the Arria GX device. SW2, SW3 JTAG chain bypass Switches to include or exclude HSMC Port A and MAX II from switches the JTAG chain.

  • Page 14: Featured Device

    Note to Table 2–1: Power switch is bypassed when the board is plugged into a PCI slot. Featured Device The Arria GX Development Kit features the EP1AGX60DF780 FPGA (U7) ® in a 780-pin flip-chip FineLine BGA (FBGA) package. Table 2–2 lists some Arria GX device features.

  • Page 15: I/O & Clocking Resources

    EP1AGX60DF780 device. Figure 2–2 illustrates the available I/O mapping on the EP1AGX60DF780 device. Figure 2–2. Arria GX Device I/O Mapping Resources Figure 2–3 illustrates the clocking resources for the EP1AGX60DF780 device. The parenthetical text refers to board-level signals as they relate ®...

  • Page 16: Configuration Schemes

    Configuration Schemes Figure 2–3. Arria GX Device Clocking Resources Configuration The Arria GX device is configured using the on-board MAX II complex programmable logic device (CPLD) and a 16-bit page-mode flash Schemes memory device. The 512 Mb flash memory device can hold eight designs, where each design is 16,951,824 bits in size for the EP1AGX60DF780 device plus 32 MBytes for other storage.
  • Page 17 Board Components Table 2–3 shows the Arria GX development board’s configuration parts list. Table 2–3. Arria GX Development Board’s Configuration Parts List Board Manufacturer Manufacturer Description Manufacturer Reference Part Number Web Site MAX II CPLD Altera EPM570F100C5N www.altera.com 512 Mbit flash memory...
  • Page 18 Configuration Schemes Figure 2–4 shows the Arria GX configuration scheme. Figure 2–4. Arria GX Configuration Scheme Table 2–4 lists the supported configuration modes and settings. The MSEL(3:0)bits are set using the MAX II device. The CFG_MODE(1:0)pins must be set on the configuration DIP switch.

  • Page 19: Jtag Chain Configuration

    To setup JTAG configuration, connect one end of the USB-Blaster cable to the computer’s USB port and the other end to the 10-pin JTAG header on the board. To download a design file to the Arria GX device, use the Quartus II Programmer.
  • Page 20 Arria GX data output (USB Blaster input) FPGA_TDO Note to Table 2–5: All signals are LVTTL. For more information about programming Altera devices, refer to the Altera Configuration Handbook. 2–10 Reference Manual Altera Corporation Arria GX Development Board October 2007...

  • Page 21: Flash Memory Configuration

    FPGA design 5 0x017F.FFFF 0x0140.0000 FPGA design 4 0x013F.FFFF 0x0100.0000 FPGA design 3 0x00FF.FFFF 0x00C0.0000 FPGA design 2 0x00BF.FFFF 0x0080.0000 FPGA design 1 0x007F.FFFF 0x0040.0000 FPGA design 0 (default) 0x003F.FFFF 0x0000.0000 Altera Corporation Reference Manual 2–11 October 2007 Arria GX Development Board...
  • Page 22 Flash signals are routed from the Spansion flash device to the MAX II device. The required signals are then routed from the MAX II device to the Arria GX device (see Figure 2–4).

  • Page 23: Max Ii Cpld Configuration Controller

    Flash address bus 3.3-V CMOS out K2,K3,H4,J4,K4, FLASH_A(24:0) J5,K5,K6,J6,K7,K8, H7,J8,H8,K10,J9, H9,J10,H10,G8,G9, G10,F10,F9 Flash data bus 3.3-V CMOS in/out C2,B1,C1,D3,D2, FLASH_D (15:0) D1,E3,F2,F3,F1, G1,H1,G2,G3,K1,J3 Flash chip enable 3.3-V CMOS out FLASH_CEn Altera Corporation Reference Manual 2–13 October 2007 Arria GX Development Board...

  • Page 24: Configuration Push Button (S5)

    Arria GX device’s CONFIGn signal that—upon pressing to drive low— forces a reconfiguration of the FPGA from the on board flash memory. The Arria GX device’s pin name associated with the CONFIGn signal is V16. Pushing the S5 switch causes the FPGA to reload a configuration from the on-board flash device.

  • Page 25: Clocking Circuitry

    Switch (S6)” on page 2–19. The 62.5 MHz and 125 MHz oscillators ensure that all protocols supported by the Arria GX device are provided for. Table 2–11 lists the Arria GX development board’s clocking parts list. Table 2–11. Arria GX Development Board’s Clocking Parts List...
  • Page 26 Clocking Circuitry Figure 2–6. Oscillator Clocking Diagram Table 2–12 lists the board’s clock distribution system. Table 2–12. Arria GX Development Board Clock Distribution (Part 1 of 2) Schematic Arria GX Pin MAX II Pin Source I/O Standard Signal Name Number...

  • Page 27: General User Interfaces

    Pin 7 in the 0n position selects SMA_CLK. CLK2_P and CLK2_N are connected to TP3 and TP4 respectively. General User To allow you to fully leverage the I/O capabilities of the Arria GX device for debugging, control, and monitoring purposes, the following general Interfaces user interfaces are available on the board: ■...

  • Page 28: User-Defined Dip Switch (S3)

    USER_RESET AE17 is the DEV_CLRn pin; when enabled in the Quartus II AE17 software, it will reset all Arria GX device registers. The USER_RESET push button is board reference S4. Pin AE17 also be used as a standard input. User-Defined DIP Switch (S3) Board reference S3 is an eight-pin DIP switch.

  • Page 29: User Leds (D9 Through D16)

    The board provides eight user-defined LEDs. A logic 0 driven to an LED turns it On; a logic 1 driven to an LED turns it Off. Table 2–15 lists the schematic signal name and the corresponding Arria GX device’s pin number. Table 2–15. User-Defined LED Pin-Out Arria GX Device Board Reference...

  • Page 30: Board-Specific Leds

    LEDs. Table 2–18. Board Status LEDs Board Reference Transceiver Interface Color Number Indicators Green HSMC present Green CONF_DONE Blue POWER_ON D21, D22, D23 Green Power_Good 2–20 Reference Manual Altera Corporation Arria GX Development Board October 2007...

  • Page 31: Off-Chip Memory

    233 MHz DDR2 device available in a 32M x16 data configuration. Table 2–20. DDR2 Description, Signal Type, Schematic Signal Name & Arria GX Pin Number (Part 1 of 2) Arria GX...
  • Page 32 Notes to Table 2–20: This is a power pin that is not connected to the Arria GX device. For power connection information, refer to the Micron MTA47H32M16 8 Meg X 16 x 4 DDR2 data sheet. Table 2–21 lists the DDR2 component reference and manufacturing information.

  • Page 33: Standard Communication Ports

    Some computers may require that the jumper be installed to operate in the PCIe x1 mode. The PCIe signals have differential traces terminated on the receive-side using internal termination resistors in the Arria GX device receiver pins. Table 2–22 lists the PCIe edge connector pin-out, descriptions, and signal type.

  • Page 34: High-Speed Mezzanine Connector Interface

    The LVDS channels can be used for CMOS signaling as well as LVDS. Due to limited transceiver resources, four transceiver channels route to the HSMC interface. For more information about the Altera HSMC interface, refer to the HSMC specifications on the Altera website, www.altera.com. Table 2–23 lists the HSMC interface component reference and manufacturing information.
  • Page 35 Board Components Table 2–24 lists HSMC interface pin-out as well as corresponding Arria GX device pin numbers. Table 2–24. HSMC Interface Pin-Out (Part 1 of 2) Schematic Arria GX Device Description Type Signal Name Pin Number Transceiver transmit 1.5 V PCML...
  • Page 36 Note to Table 2–24: When the MAX II device is bypassed, the HSMA_JTAG_TDO signal is connected to Arria GX device pin V19. Table 2–25 shows the minimum power levels that the Arria GX development board guarantees from on-board power supplies. The power rails are delivered via designated pins on the HSMC interface.
  • Page 37 The top-left is a x8 PCIe female adapter (right-angle) and the top-right is an AMC header (type B) adapter. The lower two figures are Altera daughter card (PROTO1) adapters, which are typically 3” wide and can vary in length.

  • Page 38: Jtag Interface

    The default USB-Blaster driver that Quartus II software installs for JTAG programming and SignalTap debugging. For more information on the JTAG chain, refer to “JTAG Chain Configuration” on page 2–9. 2–28 Reference Manual Altera Corporation Arria GX Development Board October 2007...

  • Page 39: Power Supply

    DC input jack (12V_SWITCHER) or from a 12 V connection supplied by a PC (12V_PC_CONN). Figure 2–9 shows the power distribution system. Figure 2–9. Arria GX Development Board’s Power Distribution System Altera Corporation Reference Manual 2–29 October 2007...

  • Page 40: Temperature Sensor

    Sensor converter that measures small voltage changes across a temperature diode on the die of the Arria GX device. The device can be programmed to automatically turn on a cooling fan at a specified temperature. A stuffing resistor is available to turn the fan on regardless of the LM95235 setting.

  • Page 41: Heat Sink And Fan

    Heat Sink and The Dynatron SCP1 heat sink unit provides heat dissipation for the Arria GX device. The fan uses 190mA at 12 V and can dissipate 25 W of heat with no additional air flow in a lab-bench type environment. The 12 V is delivered through a two-pin 100-mil header.
  • Page 42 Heat Sink and Fan 2–32 Reference Manual Altera Corporation Arria GX Development Board October 2007...

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