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Altera EP2AGX45 Device Handbook

Arria ii series fpga development board. volume 1: device interfaces and integration
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This section provides a complete overview of all features relating to the Arria
device family, the industry's first cost-optimized 40 nm FPGA family. This section
includes the following chapters:
Chapter 1, Overview for the Arria II Device Family
■
Chapter 2, Logic Array Blocks and Adaptive Logic Modules in Arria II Devices
■
■
Chapter 3, Memory Blocks in Arria II Devices
■
Chapter 4, DSP Blocks in Arria II Devices
■
Chapter 5, Clock Networks and PLLs in Arria II Devices

Revision History

Refer to each chapter for its own specific revision history. For information on when
each chapter was updated, refer to the Chapter Revision Dates section, which appears
in this volume.
December 2010 Altera Corporation
Section I. Device Core for Arria II Devices
Arria II Device Handbook Volume 1: Device Interfaces and Integration
®
II

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  • Page 1: Revision History

    Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in this volume. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 2 I–2 Section I: Device Core for Arria II Devices Revision History Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 3 Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera.
  • Page 4 ■ Low cost, easy-to-use development kits featuring high-speed mezzanine ■ connectors (HSMC) ■ Emulated LVDS output support with a data rate of up to 1152 Mbps Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 5 Table 1–1 lists the Arria II device features. Table 1–1. Features in Arria II Devices Arria II GX Devices Arria II GZ Devices Feature EP2AGX45 EP2AGX65 EP2AGX95 EP2AGX125 EP2AGX190 EP2AGX260 EP2AGZ225 EP2AGZ300 EP2AGZ350 Total Transceivers 16 or 24 16 or 24...
  • Page 6 (7) The LVDS channel count does not include dedicated clock input pins and PLL clock output pins. (8) These numbers represent the accumulated LVDS channels supported in Arria II GX row and column I/O banks. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 7 C3, C4, I3, I4 C3, C4, I3, I4 C3, C4, I3, I4 EP2AGZ350 — — C3, C4, I3, I4 C3, C4, I3, I4 C3, C4, I3, I4 December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 8 1, 2, ×4, and ×8 General Purpose I/O, and Memory Interface High-Speed Differential I/O, High-Speed Differential I/O, General Purpose I/O, and General Purpose I/O, and Memory Interface Memory Interface Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 9 On-die power supply regulators for transmitter and receiver PLL charge pump ■ and voltage-controlled oscillator (VCO) for superior noise immunity Calibration circuitry for transmitter and receiver on-chip termination (OCT) ■ resistors December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 10 ■ For other protocols supported by Arria II devices, such as SONET/SDH, SDI, SATA and SRIO, refer to the Transceiver Architecture in Arria II Devices chapter. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 11 II software allows you to take advantage of MLABs, M9K, and M144K memory blocks by instantiating memory using a dedicated megafunction wizard or by inferring memory directly from VHDL or Verilog source code. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 12 For Arria II devices, calibrates OCT or driver impedance matching for single-ended I/O standards with one OCT calibration block on the I/O banks listed in Table 1–8. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 13 5 to 500 MHz to support both low-cost and high-end clock performance ■ FPGA fabric can use the unused transceiver PLLs to provide more flexibility December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 14 Arria II devices support all variants of the NIOS II processor ■ Nios II processors are supported by an array of software tools from Altera and ■ leading embedded partners and are used by more designers than any other configurable processor Configuration Features ■...
  • Page 15 Boundary-scan test (BST) architecture offers the capability to test pin connections ■ without using physical test probes and capture functional data while a device is operating normally December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 16 Updated Table 1–1, Table 1–2, and Table 1–3 ■ November 2009 Updated “Configuration Features” section ■ Updated Table 1–2. ■ June 2009 Updated “I/O Features” section. ■ February 2009 Initial release. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 17 Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera.
  • Page 18 Simple dual port SRAM MLAB Note to Figure 2–2: (1) You can use an MLAB ALM as a regular LAB ALM or configure it as a dual-port SRAM. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 19 LAB, memory block, DSP block, or IOE output DSP block, or IOE output ALMs ALMs Direct link Direct link interconnect interconnect to right to left Local Interconnect MLAB December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 20 Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect labclk0 syncload labclr1 labclk1 labclk2 labclkena0 labclkena1 labclkena2 labclr0 synclr or asyncload or labpreset Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 21 To general or adder1 local routing 6-Input LUT datae1 reg1 dataf1 To general or local routing Combinational/Memory ALUT1 reg_chain_out shared_arith_out carry_out December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 22 ALM outputs can also drive local interconnect resources. The LUT or adder can drive one output while the register drives another output. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 23 These LAB-wide signals are available in all ALM modes. For more information on the LAB-wide control signals, refer to “LAB Control Signals” on page 2–4. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 24 4 and 3, 3 and 3, 3 and 2, and 5 and 2. Normal mode provides complete backward-compatibility with 4-input LUT architectures. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 25 (1) If datae1 and dataf1 are used as inputs to a 6-input function, datae0 and dataf0 are available for register packing. (2) The dataf1 input is available for register packing only if the 6-input function is unregistered. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 26 Note to Figure 2–9: (1) If the 7-input function is unregistered, the unused eighth input is available for register packing. The second register, reg1, is not available. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 27 LAB. These signals can also be individually disabled or enabled per register. The Quartus II software automatically places any registers that are not used by the counter into other LABs. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 28 MLAB columns, the bottom half can be bypassed. For more information on carry chain interconnect, refer to “ALM Interconnects” on page 2–17. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 29 Another example is a correlator function that can use a large adder tree to sum filtered data samples in a given time frame to recover or de-spread data that was transmitted using spread-spectrum technology. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 30 Every other LAB column is top-half bypassable, while the other LAB columns are bottom-half bypassable. For more information on shared arithmetic chain interconnect, refer to “ALM Interconnects” on page 2–17. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 31 0 a sdata regout leout 0 b lelocal 1 aclr datain leout 1 a sdata regout leout 1 b reg_chain_out December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 32 (1) You can use the combinational or adder logic to implement an unrelated, un-registered function. For more information about register chain interconnect, refer to “ALM Interconnects” on page 2–17. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 33 Arria II LABs operate in high-performance mode or low-power mode. The Quartus II software automatically chooses the appropriate mode for the LAB, based on the design, to optimize speed versus leakage trade-offs. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 34 Modes”, “Normal Mode” sections. Added Figure 2–7 Figure 2–8. ■ Added “LAB Power Management Techniques” section. ■ June 2009 Updated Figure 2–6. February 2009 Initial Release. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 35 Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera.

  • Page 36: Memory Features

    Output registers Output registers Write and Read: Write: Falling clock edges. Write and Read: Rising clock Write/Read operation triggering Rising clock Read: Rising clock edges edges edges Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 37 All memory blocks have built-in parity bit support. The ninth bit associated with each byte can store a parity bit or serve as an additional data bit. No parity function is actually performed on the ninth bit. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 38 ABCD contents at a2 XXCD don't care: q (asynch) doutn ABXX ABCD ABFF FFCD ABCD ABFF FFCD ABCD ABFF FFCD ABCD doutn current data: q (asynch) Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 39 The default value for the address clock enable signal is low (disabled). December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 40 Figure 3–4. Address Clock Enable During Read Cycle Waveform inclock rdaddress rden addressstall latched address (inside memory) dout4 q (synch) doutn-1 doutn dout0 dout1 doutn dout0 dout1 dout4 q (asynch) dout5 Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 41 (inside memory) contents at a0 contents at a1 contents at a2 contents at a3 contents at a4 contents at a5 December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 42 (eccstatus[2..0]). The status flag can be either registered or unregistered. When registered, it uses the same clock and asynchronous clear signals as the output registers. When unregistered, it cannot be asynchronously cleared. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 43 Figure 3–8. ECC Block Diagram of the M144K Block SECDED SECDED Data Input Comparator Encoder Array Encoder Flag Error Generator Locator Status Flags Error Correction Block Data Output December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 44 3–9: (1) You can implement two single-port memory blocks in a single M9K and M144K blocks. For more information, refer “Packed Mode Support” on page 3–5. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 45 M144K block outputs delay the q output by one clock cycle. Figure 3–10. Timing Waveform for Read-Write Operations for M9K and M144K Blocks (Single-Port Mode) clk_a wrena rdena address_a data_a q_a (asynch) a1(old data) a0(old data) December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 46 ] byteena[] rd_addressstall wr_addressstall rdclock wrclock rdclocken wrclocken ecc_status (1) aclr Note to Figure 3–12: (1) Only available for Arria II GZ devices. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 47 MLABs only support a write-enable signal. Read-during-write behavior for the MLABs can be either a “don’t care” or “old data” value. The available choices depend on the configuration of the MLAB. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 48 Figure 3–14. Simple Dual-Port Timing Waveforms for MLABs wrclock wren wraddress an-1 data din-1 din4 din5 din6 rdclock rden rdaddress q (asynch) dout0 doutn-1 doutn Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 49 Because true dual-port RAM has outputs on two ports, its maximum width equals half of the total number of output drivers. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 50 Conflict resolution circuitry is not built into the Arria II memory blocks. You must handle address conflicts external to the RAM block. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 51 The size of a shift register (w × m × n) is determined by the input data width (w), the length of the taps (m), and the number of taps (n). You can cascade memory blocks to implement larger shift registers. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 52 (asynchronous) FIFOs are supported. For more information about implementing FIFO buffers, refer to the SCFIFO and DCFIFO Megafunctions User Guide. MLABs do not support mixed-width FIFO mode. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 53 The memory blocks support independent clock enables for both the read and write clocks. Asynchronous clears are available on data output latches and registers only. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...

  • Page 54: Design Considerations

    Therefore, you must implement conflict resolution logic, external to the memory block, to avoid address conflicts. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 55 Figure 3–20. MLABs Blocks Same Port Read-During Write: Don’t Care Mode clk_a address data_in FFFF AAAA XXXX wrena AAAA q(unregistered) FFFF A1(old data) A2(old data) A0(old data) q(registered) FFFF AAAA December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 56 “old data” at that address location. In don’t care mode, the same operation results in a “don’t care” or “unknown” value on the RAM outputs. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 57 Figure 3–24. MLABs Mixed-Port Read-During-Write: Don’t Care Mode clk_a wraddress rdaddress AAAA BBBB CCCC DDDD EEEE FFFF data_in wrena byteena_a AAAA AABB CCBB DDDD DDEE FFEE q_b(registered) December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 58 Mixed-port read-during-write is not supported when two different clocks are used in a dual-port RAM. The output value is unknown during a dual-clock mixed-port read-during-write operation. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...

  • Page 59: Power Management

    The Quartus II software automatically places any unused memory block in low power mode to reduce static power. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 60 Updated Figure 3–1, Figure 3–2, Figure 3–5, Figure 3–9, Figure 3–12, Figure 3–18, ■ Figure 3–19, and Figure 3–20 Added Figure 3–2, Figure 3–6, Figure 3–10, and Figure 3–13 ■ February 2009 Initial release Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 61 Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera.
  • Page 62 ■ Rich and flexible arithmetic rounding and saturation units Efficient barrel shifter support ■ Loopback capability to support adaptive filtering ■ Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 63 Figure 4–1. Overview of DSP Block Signals Control Output Half-DSP Block Data Input Data Output Half-DSP Block Data Full-DSP Block December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 64 You can configure the second-stage adders to provide the alternative functions shown in Equation 4–1 Equation 4–2 per half block. Equation 4–2. Four-Multiplier Adder Equation Z[37..0] = P [36..0] + P [36..0] Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 65 DSP block with the output register stage shown in Figure 4–4. Detailed examples are described in later sections. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 66 In addition to the independent multipliers and sum modes, you can use DSP blocks to perform shift operations. DSP blocks can dynamically switch between logical shift left/right, arithmetic shift left/right, and rotation operation in one clock cycle. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 67 DSP block resource efficiency and allows you to implement more multipliers in an Arria II device. The Quartus II software automatically places multipliers that can share the same DSP block resources in the same block. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...

  • Page 68: Table Of Contents

    (3) When the chainout adder is not in use, the second adder register banks are known as output register banks. (4) You must connect the chainin port to the chainout port of the previous DSP blocks; it must not be connected to general routings. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 69 Register scanouta Note to Figure 4–6: (1) The scanina signal originates from the previous DSP block, while the scanouta signal goes to the next DSP block. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 70 (1) The multiplier operand input word lengths are statically configured at compile time. (2) Available only on the A-operand. (3) Only one loopback input is allowed per half block. For details, refer to Figure 4–14 on page 4–21. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 71 Depending on your specifications, the output of the first-stage adder has the option to feed into the pipeline registers, second-stage adder, rounding and saturation unit, or the output registers. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 72 The dynamic rounding and saturation signals control the rounding and saturation logic unit, respectively. A logic 1 value on the round signal, saturate signal, or both enables the round logic unit, saturate logic unit, or both. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 73 The second-stage and output registers are triggered by the positive edge of the clock signal and are cleared on power up. The clock[3..0], ena[3..0], and aclr[3..0] DSP block signals control the output registers in the DSP block. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 74 ] datab_0[17..0] dataa_1[17..0] result_1[ ] datab_1[17..0] Half-DSP Block Note to Figure 4–7: (1) Block output for accumulator overflow and saturate overflow. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 75 Figure 4–8. 12-Bit Independent Multiplier Mode Shown for Half-DSP Block clock[3..0] signa ena[3..0] signb aclr[3..0] dataa_0[11..0] result_0[ ] datab_0[11..0] dataa_1[11..0] result_1[ ] datab_1[11..0] dataa_2[11..0] result_2[ ] datab_2[11..0] Half-DSP Block December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 76 DSP block. The rounding and saturation logic unit is supported for 18-bit independent multiplier mode only. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 77 Figure 4–10. 36-Bit Independent Multiplier Mode Shown for Half-DSP Block clock[3..0] signa ena[3..0] signb aclr[3..0] dataa_0[35..18] datab_0[35..18] dataa_0[17..0] datab_0[35..18] result[ ] dataa_0[35..18] datab_0[17..0] dataa_0[17..0] datab_0[17..0] Half-DSP Block December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 78 Figure 4–11. Double Mode Shown for a Half DSP Block clock[3..0] signa ena[3..0] signb aclr[3..0] dataa_0[35..18] datab_0[35..18] dataa_0[17..0] datab_0[35..18] result[ ] dataa_0[35..18] datab_0[17..0] dataa_0[17..0] datab_0[17..0] Half-DSP Block Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 79 ] dataa[53..36] datab[35..18] dataa[53..36] datab[17..0] dataa[35..18] 36 × 36 Mode datab[35..18] dataa[17..0] datab[35..18] dataa[35..18] datab[17..0] dataa[17..0] datab[17..0] Unsigned 54 × 54 Multiplier December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 80 A logic 1 value on the zero_loopback signal selects the zeroed data or disables the looped back data, and a logic 0 selects the looped back data. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 81 Two-multiplier adder mode supports the rounding and saturation logic unit. You can use pipeline registers and output registers in the DSP block to pipeline the multiplier-adder result, increasing the performance of the DSP block. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 82 Figure 4–15. Complex Multiplier Using Two-Multiplier Adder Mode clock[3..0] signa ena[3..0] aclr[3..0] signb (A × C) - (B × D) (Real Part) (A × D) + (B × C) (Imaginary Part) Half-DSP Block Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 83 Four-multiplier adder mode supports the rounding and saturation logic unit. You can use the pipeline registers and output registers within the DSP block to pipeline the multiplier-adder result, increasing the performance of the DSP block. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 84 <<18 dataB[18:35] result[ ] dataC[0:17] dataD[0:17] dataC[0:17] <<18 dataD[18:35] Half-DSP Block Note to Figure 4–17: (1) Block output for accumulator overflow and saturate overflow. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 85 0 enables accumulation by adding or subtracting the output of the DSP block (accumulator feedback) to the output of the multiplier and first-stage adder. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 86 32-bit word length. Two control signals, rotate and shift_right, together with the signa and signb signals, determine the shifting operation. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 87 LSR[32-N] Arithmetic Shift Left Signed Unsigned 0×AABBCCDD 0×0000100 0×BBCCDD00 ASL[N] Arithmetic Shift Right Signed Unsigned 0×AABBCCDD 0×0000100 0×FFFFFFAA ASR[32-N] Rotation ROT[N] Unsigned Unsigned 0×AABBCCDD 0×0000100 0×BBCCDDAA December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 88 001110 0100 ➱ ➱ 110111 1110 110111 1110 101101 ➱ 1011 101101 ➱ 1011 110110 ➱ 1110 110110 ➱ 1110 ➱ ➱ 110010 1101 110010 1100 Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 89 Likewise, the functionality of the saturation logic unit is in the format of: ∑ Result = SAT[ (A × B)], when used for an accumulation type of operation. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...

  • Page 90: Zero_Loopback

    Dynamically specifies whether the chainout value is zero. zero_chainout Dynamically specifies whether the loopback value is zero. zero_loopback rotation = 1, rotation feature is enabled rotate Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 91 Total Count per Half- and Full-DSP Blocks Software Support for Arria II Devices Altera provides two distinct methods for implementing various modes of the DSP block in a design: instantiation and inference. Both methods use the following Quartus II megafunctions: LPM_MULT ■...
  • Page 92 Updated Table 4–1 and Table 4–9 ■ November 2009 Updated Figure 4–9 ■ Minor text edit ■ June 2009 Updated Table 4–1 February 2009 Initial release Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 93 Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera.
  • Page 94 (1) There are 64 RCLKs in the EP2AGZ225 devices. There are 88 RCLKs in the EP2AGZ300 and EP2AGZ350 devices. (2) There are 50 PCLKs in EP2AGX45 and EP2AGX65 devices, where 18 are on the left side and 32 on the right side. There are 59 PCLKs in EP2AGX95 and EP2AGX125 device, where 27 are on the left side and 32 on the right side.
  • Page 95 (2) Because there are no dedicated clock pins on the left side of an Arria II GX device, GCLK[0..3] are not driven by any clock pins. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 96 Figure 5–3 Figure 5–4 show CLK pins and PLLs that can drive RCLK networks in Arria II devices. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 97 (1) A maximum of four signals from the core can drive into each group of RCLKs. For example, only four core signals can drive into RCLK[0..5] and another four core signals can drive into RCLK[54..63] at any one time. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 98 I/O pins, and internal logic can drive the PCLK networks. The number of PCLKs for each Arria II device are as follows: ■ EP2AGX45 and EP2AGX65 devices contain 50 PCLKs ■ EP2AGX95 and EP2AGX125 devices contain 59 PCLKs ■...
  • Page 99 For Arria II GZ devices, corner PLL outputs only span one quadrant, they cannot generate a dual-regional clock network. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 100 PLL outputs, and internal logic can drive the GCLK and RCLK networks. Table 5–2 through Table 5–5 on page 5–10 list the connectivity between dedicated clock pins and the GCLK and RCLK networks. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 101 — — — — — — — — — — — — GCLK[8..11] — — — — — — — — — — — — GCLK[12..15] December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 102 — — 59, 63] RCLK [44, 48, 52, 54, — — — — — — — — — — — — — — — 58, 62] Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 103 (1) For single-ended clock inputs, only the CLK<#>p pin has a dedicated connection to the PLL. If you use the CLK<#>n pin, a GCLK is used. (2) For the availability of the clock input pins in each device density, refer to the “Arria II Device Pin-Out Files” section of the Pin-Out Files for Altera Devices.
  • Page 104 — — — — RCLK[0..11] — — — — — — RCLK[12..31] — — — — — — RCLK[32..43] — — — — — — RCLK[44..63] Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 105 When selecting the clock source dynamically, you can either select two PLL outputs (such as C0 or C1), or a combination of clock pins or PLL outputs. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 106 You can choose from among these inputs with the CLKSELECT[1..0]signal. For the connections between the PLL counter outputs to the clock control block, refer to Table 5–12 on page 5–14. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 107 (.sof or .pof). You cannot dynamically control the clock. (2) The CLKn pin is not a dedicated clock input when used as a single-ended PLL clock input. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 108 (1) The R1 and R2 bypass paths are not available for PLL external clock outputs. (2) The select line is statically controlled by a bit setting in the configuration file (.sof or .pof). Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 109 .sof or .pof. The Quartus II software automatically sets the multiplexer select signals depending on the clock sources selected in your design. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 110 PLL or a pin-driven dedicated GCLK or RCLK. An internally generated global signal or general purpose I/O pin cannot drive the PLL. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 111 All Arria II PLLs have the same core analog structure and support features with minor differences in the features that are supported for Arria II GZ devices. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 112 (5) The smallest phase shift is determined by the voltage-controlled oscillator (VCO) period divided by eight. For degree increments, the Arria II device can shift all output frequencies in increments of at least 45°. Smaller degree increments are possible depending on the frequency and C counter value. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 113 ■ PLL_1 and PLL_3 of EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260 devices). You can only access one differential I/O pair or one single-ended pin at a time. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 114 1st pair—two single-ended I/O or one differential I/O ■ ■ 2nd pair—two single-ended I/O or one differential external feedback input (FBp/FBn) ■ 3rd pair—two single-ended I/O or one differential input Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 115 (FB) pin. Therefore, for single-ended I/O standards, the left and right PLLs only support external feedback mode. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 116 PLL clocking. However, external clock output pins can support a differential I/O standard that is only driven by a PLL. Regular I/O pins cannot drive the PLL clock input pins. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 117 PLL clock outputs are operating at the desired phase and frequency set in the Quartus II software. Altera recommends using the areset and locked signals in your designs to control and observe the status of your PLL. For more information about the PLL control signals, refer to the...
  • Page 118 PLL. If the PLL input is instead fed by a non-dedicated input (using the GCLK network), the output clock may not be perfectly aligned with the input clock. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 119 If you do not assign the PLL Compensation assignment, the Quartus II software automatically selects all pins driven by the compensated output of the PLL as the compensation target. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 120 Both the PLL internal and external clock outputs are phase-shifted with respect to the PLL clock input. Figure 5–22 shows an example waveform of the PLL clocks’ phase relationship in no-compensation mode. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 121 Register Clock Port Dedicated PLL Clock Outputs (1) Note to Figure 5–23: (1) The external clock output can lead or lag the PLL internal clock signals. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 122 PLL clock input or output pins. Figure 5–24. ZDB Mode in PLLs for Arria II GZ Devices inclk ÷n PLL_<#>_CLKOUT# ÷C0 CP/LF PLL_<#>_CLKOUT# ÷C1 fbout ÷m bidirectional I/O pin fbin Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 123 You must use the same I/O standard on the input clock, feedback input, and output clocks. Left and right PLLs support this mode when using single-ended I/O standards only. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 124 (the least common multiple of 33 and 66 MHz in the VCO range). Then the post-scale counters scale down the VCO frequency for each output port. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 125 C0 × C1 = 800. Post-scale counter cascading is set in the configuration file. You cannot accomplish post-scale counter cascading with PLL reconfiguration. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 126 800 MHz and fin e equals 156.25 ps. The PLL operating frequency, which is governed by the reference clock frequency and the counter settings, defines this phase shift. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 127 Arria II devices support dynamic phase-shifting of VCO phase taps only. The phase shift is reconfigurable any number of times and each phase shift takes about one SCANCLK cycle, allowing you to implement large phase shifts quickly. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 128 Automatic switchover with manual override—This mode combines modes 1 and 2. When clkswitch = 1, it overrides automatic clock switchover function. As long as the clkswitch signal is high, further switchover action is blocked. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 129 PLL may lose lock after the switchover is completed and requires time to relock. Altera recommends resetting the PLL with the areset signal to maintain the phase relationships between the PLL input and output clocks when you use clock switchover.
  • Page 130 (inclk0 and inclk1) frequencies with a frequency difference of more than 100% (2×). This feature is useful when the clock sources originate from multiple cards on the backplane, requiring a system-controlled Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 131 The clkswitch signal and automatic switch only work if the clock being switched to is available. If the clock is not available, the state machine waits until the clock is available. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 132 PLL propagates the stopping of the clock to the output more slowly than the high-bandwidth PLL. However, be aware that the low-bandwidth PLL also increases lock time. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 133 75 or 150 MHz, depending on the requirements of the device under test. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 134 (3) This figure shows the corresponding scan register for the K counter in between the scan registers for the charge pump and loop filter. The K counter is physically located after the VCO. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 135 PLL reconfiguration feature. Figure 5–36. PLL Reconfiguration Waveform for Arria II Devices SCANDATA SCANCLK SCANCLKENA Dn_old D0_old SCANDATAOUT CONFIGUPDATE SCANDONE ARESET December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 136 = 1 effectively equals: High-time count = 1.5 cycles ■ Low-time count = 1.5 cycles ■ Duty cycle = (1.5/3) % high-time count and (1.5/3)% low-time count ■ Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 137 The length of the scan chain varies for different Arria II GZ PLLs. The top and bottom PLLs have ten post-scale counters and a 234-bit scan chain, while the left and right PLLs have seven post-scale counters and a 180-bit scan chain. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 138 (3) The LSB for the C6 low-count value is the first bit shifted into the scan chain for the left and right PLLs. (4) The MSB for the loop filter is the last bit shifted into the scan chain. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 139 Arria II PLLs. Figure 5–39. Scan Chain Bit-Order Sequence for Post-Scale Counters in Arria II PLLs DATAIN rbypass rselodd DATAOUT December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 140 Table 5–18. loop_filter_r Bit Settings for Arria II Devices LFR[4] LFR[3] LFR[2] LFR[1] LFR[0] Decimal Value for Setting Table 5–19. loop_filter_c Bit Settings for Arria II Devices LFC[1] LFC[0] Decimal Value for Setting Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 141 PHASEUPDOWN I/O pin PLL on the rising edge of scanclk. circuit Logic array or Logic high enables dynamic phase shifting. reconfiguration PHASESTEP I/O pin circuit December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 142 2. Assert PHASESTEP for at least two SCANCLK cycles. Each PHASESTEP pulse allows one phase shift. 3. Deassert PHASESTEP. 4. Wait for PHASEDONE to go high. 5. Repeat steps through as many times as required to perform multiple phase-shifts. Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...
  • Page 143 SCANCLK cycle. For more information about the ALTPLL_RECONFIG MegaWizard Plug-In Manager interface, refer to the Phase Locked-Loops Reconfiguration (ALTPLL_RECONFIG) Megafunction User Guide. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration...
  • Page 144 Updated Figure 5–13 and Figure 5–14. ■ June 2009 Updated the “PLL Clock I/O Pins” and “PLL Reconfiguration Hardware Implementation” ■ sections. February 2009 Initial release Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation...

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