Texas Instruments LMK0482 Series Manual

1 Features
• JEDEC JESD204B Support
1
• Ultra-Low RMS Jitter
– 88 fs RMS Jitter (12 kHz to 20 MHz)
– 91 fs RMS Jitter (100 Hz to 20 MHz)
– –162.5 dBc/Hz Noise Floor at 245.76 MHz
• Up to 14 Differential Device Clocks from PLL2
– Up to 7 SYSREF Clocks
– Maximum Clock Output Frequency 3.1 GHz
– LVPECL, LVDS, HSDS, LCPECL
Programmable Outputs from PLL2
• Up to 1 Buffered VCXO/Crystal Output from PLL1
– LVPECL, LVDS, 2xLVCMOS Programmable
• Dual Loop PLLatinum™ PLL Architecture
• PLL1
– Up to 3 Redundant Input Clocks
– Automatic and Manual Switch-Over Modes
– Hitless Switching and LOS
– Integrated Low-Noise Crystal Oscillator Circuit
– Holdover mode when Input Clocks are Lost
• PLL2
– Normalized [1 Hz] PLL Noise Floor of
-227 dBc/Hz
– Phase Detector Rate up to 155 MHz
– OSCin Frequency-Doubler
– Two Integrated Low-Noise VCOs
• 50% Duty Cycle Output Divides, 1 to 32
(even and odd)
• Precision Digital Delay, Dynamically Adjustable
• 25 ps Step Analog Delay
• Multi-mode: Dual PLL, single PLL, and Clock
Distribution
• Industrial Temperature Range: –40 to 85°C
• Supports 105°C PCB Temperature (Measured at
Thermal Pad)
• 3.15-V to 3.45-V Operation
• Package: 64-Pin QFN (9.0 mm x 9.0 mm x 0.8
mm)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Sample &
Product
Buy
Folder
LMK0482x Ultra Low-Noise JESD204B Compliant
Clock Jitter Cleaner with Dual Loop PLLs
Tools &
Technical
Software
Documents
SNAS605AR – MARCH 2013 – REVISED DECEMBER 2015
2 Applications
• Wireless Infrastructure
• Data Converter Clocking
• Networking, SONET/SDH, DSLAM
• Medical / Video / Military / Aerospace
• Test and Measurement
3 Description
The LMK0482x family is the industry's highest
performance clock
JESD204B support.
The 14 clock outputs from PLL2 can be configured to
drive seven JESD204B converters or other logic
devices using device and SYSREF clocks. SYSREF
can be provided using both DC and AC coupling. Not
limited to JESD204B applications, each of the 14
outputs can be individually configured as high
performance outputs for traditional clocking systems.
The high performance combined with features like the
ability to trade off between power or performance,
dual VCOs, dynamic digital delay, holdover, and
glitchless analog delay make the LMK0482x family
ideal for providing flexible high performance clocking
trees.
Device Information
PART
NUMBER FREQUENCY
LMK04821 1930 to 2075 MHz
LMK04826B 1840 to 1970 MHz
LMK04828B 2370 to 2630 MHz
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
Crystal or
VCXO
Recovered
³GLUW\´ FORFN RU
clean clock CLKin0
Backup
Reference
LMK0482xB
Clock CLKin1
DCLKout0 &
DCLKout2
ADC
SDCLKout1 &
SDCLKout3
Support &
Community
LMK04821, LMK04826, LMK04828
conditioner with
(1)
VCO0
VCO1 FREQUENCY
2920 to 3080 MHz
VCO1 Div = ÷2 to ÷8
(÷2 = 1460 to 1540 MHz)
2440 to 2505 MHz
2920 to 3080 MHz
OSCout
LMX2581
PLL+VCO
DCLKout12
FPGA
SDCLKout13
DCLKout8 &
DCLKout10
SDCLKout9 &
SDCLKout11
DCLKout4,
DAC
SDCLKout5
DAC
Serializer/
Deserializer
JEDEC
0XOWLSOH ³FOHDQ´
clocks at different
frequencies