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a.
General
(refer
to Figure
15 for a detailed
block
diagram
of the A-to-D
cO""erter).
The analog-to-dig-
ital
converter
operates
using
a dual
slope
integration
technique
which has inherent
line
frequency
noise
re-
jection.
The *"*log
sign*1
is applied
t"
the integra-
tor
for one complete
line
frequency
cycle,
therefore
integrating
the line
frequency
noise.
me analog
sig-
nal
is the"
remove*
from the integrator
input.
The
voltage
on the integraeor
is then driven
to zero to
complete
the voltage-to-time
conversion.
The time
in-
terval
to reach a "zero
crossing"
is counted
and dis-
played
on the "Readaut"
in praportio"
e" the origi"al
analog
sign*,.
The sequence
is then repeated
for a
second reading.
(Refer
to the Timing
Diagram
shown
in Figure
9).
b.
The A-m-D
converter
is composed of nine major
circuits
which
perform
the analog-to-digital
conver-
sions
an* provide
Various
control
commands.
1.
Oscillator
or clock
2.
BCD counter
3.
Delay
Hold
b.
Program/Decoder
5.
I"tegr*tOr
6.
Nero
Crossing
Detector
7.
Buffer/Storage
Register
8.
Decoder/Driver
9.
Numerical
Readouf.
C.
Oscillator
or Clock.
The Oscillator
produces
pulses
at a rate
of 120 kilohertz
for Electrometer
using
60 HZ line
power.
(The 50 HZ units
have B pulse
race of 100 kilohertz).
d.
BCD Counter.
The BCD COULI~BT' counts
the Clock
pulses
with
a total
range of 5000 co""cs.
The Counter
ia composed of 4 i"di"idual
counters
designated
1, 10,
100, and 1000.
1.
The "I",
"IO",
and "100"
counters
have a ca-
pacity
of ten co""ts
each.
3.
The tot*1
capacity
of all
four
co""ters
is
5000 counts.
e,
Delay Hold.
The Delay Hold circuit
controls
the
DISPLAY RATE function
and external
Hold and Trigger
colmnan*a (refer
eo Figure
16).
1.
1t determines
the length
of time between A-ta-
D conversions
when the front
panel
DISPLAY RATE Con-
trol
is Bet to any position
other
charI MAX.
me
clock
is stopped
ac the beginning
of the ZERO (2)
period
for a time
determined
by the rotation
of the
DISPLAY RATE Control.
2.
It
ensures
chat when the Hold 2 is grounded
the conversion
in process
will
be cornpIeced
and new
data will
be stored
in the m,t,,ut
storage
register.
Then the clack
will
be inhibited
at the beginning
of
the ZERO period
(2).
The instrument
will
remain
in
this
condition
indefinitely
until
Hold 2 is released
24
or "ntil
Trigger
is shorted
to ground.
After
con-
"ersio",
ehe instrument
will
again
be inhibited
at
the beginning
af ehe period
(2).
3.
If
both Switches
s1 an* s2 are clased,
rile
conversion
cycle
works
in the foliuwing
manner.
a)
After
the previous
converSion
ihas been cm-
pleted,
etle leading
edge of the program comma**
(2)
resets
the flip-flop.
I"
this
new con*icim
q is high
and, therefore.
the clock
gives
110 out-
put.
b)
At
that
rime,
the ""ijunction
timer
begins
its
cycle
and, after
the appropriate
time.
pro-
duces a pulse
LhaL sets
the flip-flap.
This
changes g to a law state
and a new C"n"erSio,l
cycle
begins.
After
the reading
has bee" corn-
pleted,
the (2) camman* again
resets
the Elip-
flop
and the timer
again
issues
a "ew pulse
co
set the flip-flop.
i------------------L-
i.EW
H
-
I
I
e.
Program/Decoder.
The Program/Decoder
circuit
produces
evenr
commands to cantrol
the overall
se-
quence of events
for a complete
A-to-D
conversian.
8.
Integrator.
The 1ntegraeor
circuit
operation
is
composed of three
periods
(refer
to Figure
9).
I.
zero
Period.
luring
this
period
the intcgra-
tar amplifier
is zeroed
by ehe closure
of s~itcll
Sb.
Switches
S,,
s,,
an* s* *IYe open to prevent
integru-
tar charging
(refer
eo Figure
17).
2.
Integration
Period.
During
this
period,
switch
Sb, SC, and Sd are open.
Switch
s, is closed
to permit
charging
by the analog
voleage
for a per-
0410
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