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13. External MC040 type cycle (SRAM)
The following table should be placed after the table 6-11 on page 6-67.
14. Missing Note on Parity.
On page 6-71, section 6.13.3, the note below should be added after the note under the
definition of parity checking enable:
Parity is not supported with external assertion of DSACK or TA.
15. Error in note on CSNT40.
On page 6-72, the note on the top of the page states that SYNC bit must be set for CSNT40
function to take effect. This is not true. Regardless of the setting of SYNC bit CSNT40 will
take an effect.
16. Missing Statement on BACK40.
On page 6-72, the description of the BACK40, for the zero case, the following statement
should be added:
"The QUICC will assert TBI on an access to this memory area".
17. Error in Note at TRLXQ.
On page 6-72, the 3rd note under TRLXQ-Timing Relax:
"User should avoid setting both TRLXQ and CSNTQ = 1, when TCYC = 0. This combination
will result in a bus cycle without CS assertion." is not correct and should be removed.
18. Missing NOTE.
On page 6-74, bits 3 and 2 of the option register should have an asterisks. Also on the
bottom of the page the following note should be added.
8
Freescale Semiconductor, Inc.
External MC68040 Type bus
TCYC =
TSS40=0
0
2
1
3
2
4
3
5
4
6
5
7
6
8
...
15
17
MC68360 USER'S MANUAL ERRATA
For More Information On This Product,
Go to: www.freescale.com
cycle Length
TSS40=1
3
4
5
6
7
8
9
18
MOTOROLA
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