Motorola MC68360 User Manual page 20

Freescale Semiconductor, Inc.
3.3 V or 5.0 V 5.0V
Num. Characteristic 25.0 MHz 33.34MHz Unit
Min Max Min Max
115 R/W Low to CASx Asserted (Write) 52.5 ns
40
10. Typo on DRAM Page-Mode Page-Hit.
On page 10-31, Figure 10-23, address valid timing for the initial access is specification 6 not
6A.
Also on same figure the Specification 8 should be removed.
Also on the same figure Specification 106 was drawn to be referenced off of the rising edge
between S0 and S1. This is not correct. The correct reference clock edge is a rising edge
between S5 and S0.
11. Error in superscript.
On page 10-33, table 10-11, The superscript on specs 130, 132, 134, 135, 142 and 144
were not correct. Specs. 130 and 132 should have no superscripts at all. Specs 134 and 135
should have a superscript of 2 only. Specs 142, 143 and 144 should have a superscript of'
2' instead of '3'.
12. Typo on BGACK/BB Negation Specification.
On page 10-33 and 10-49 there are two specifications for the negation of BGACK/BB.
Specification 139 and specification 238 are not correct needed and should be deleted. The
Figures affected are 10-25, 10-26 for 030/360 external masters and Figure 10-39 on page
10-50 for 040 external masters.
13. Error in Figure.
On pages 10-34, and 10-35, the negation timing for BCLRO is not correct. In both figures
the negation of the signal BCLRO is shown to be at the rising edge of CLKO1 where BGACK
is asserted. The signal is instead negated at the rising edge of CLKO1 where BGACK is
negated.
Also on same figures the negation delay between BR and BG, specification 136, should be
removed from the figures.
14. Missing Note on Bus Request Negation.
On pages 10-34 and 10-35, the following note should be added:
User should note that the negation timing of bus request from a slave QUICC pin may not
meet the required input specification for the QUICC in master mode. Because of this the
20 MC68360 USER'S MANUAL ERRATA MOTOROLA
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