Pll Operation Start / Stop / Switching Procedure; Fc Setup (Pll Stop >>> Pll Start); Fc Setup (Conduct Pll >>> Pll Stop) - Toshiba TXZ+ TMPM4MNFYAFG Reference Manual

PLL operation start / stop / switching procedure

(1) fc setup (PLL stop >>> PLL start)
As an fc setup, the example of switching procedure from the PLL stop state to the PLL operation state is as
follows.
<< The state before switching >>
[CGPLL0SEL]<PLL0ON> =0
[CGPLL0SEL]<PLL0SEL> =0
[CGPLL0SEL]<PLL0ST> =0
[CGSYSCR]<MCKSEL> =00
<< The example of switching procedure >>
[CGSYSCR]<MCKSEL[1:0]> = 01 or 1*
1
[CGSYSCR]
2
<MCKSELGST><MCKSELPST> is read
[CGPLL0SEL]<PLL0SET[23:0]> =0xX
3
Wait 100 μs or more.
4
5 [CGPLL0SEL]<PLL0ON> =1
Wait 400 μs or more.
6
7 [CGPLL0SEL]<PLL0SEL> =1
8 [CGPLL0SEL]<PLL0ST> is read
Note1: 1 and 2 are executed when the ratio of the system clock should be changed.
Note2: 3 to 6 are unnecessary when the state before switching is [CGPLL0SEL]<PLL0ON> = 1.
When changing from the state where the PLL output clock is stable, it can be changed to the PLL
operation state by execution of only 7 and 8.
(2) fc setup (conduct PLL >>> PLL stop)
As an fc setup, the example of switching procedure from the PLL operation state to a PLL stop state is as follows.
<< The state before switching >>
[CGPLL0SEL]<PLL0ON> =1
[CGPLL0SEL]<PLL0SEL> =1
[CGPLL0SEL]<PLL0ST> =1
<< The example of switching sequence >>
1 [CGPLL0SEL]<PLL0SEL> =0
[CGPLL0SEL]<PLL0ST> is read
2
3 [CGPLL0SEL]<PLL0ON> =0
Stops the PLL operation for fsys.
Selects the setting of the PLL for fsys to "PLL is unused (f
Indicates the status of the PLL for fsys to "PLL is unused (f
Ratios of (High speed system clock vs Middle speed system clock) and
(High speed prescaler clock vs Middle speed system clock) are 1:1.
Ratios of (High speed system clock vs Middle speed system clock) and
(High speed prescaler clock vs High speed system clock) are changed.
Wait until they become the values set at Step 1.
A PLL multiplication value setup is chosen.
Latency time after a multiplication setup
PLL operation for fsys is carried out to an oscillation.
PLL output clock stable latency time
PLL selection for fsys is carried out to PLL use (f
It waits until the PLL selection status for fsys becomes PLL use (f
(=1).
Sets the PLL for fsys to oscillate.
Selects the PLL for fsys to "PLL is used (f
Indicates the status of the PLL for fsys to "PLL is used (f
Selects the PLL for fsys to "PLL is unused (f
Waits until the status of the PLL for fsys becomes "PLL is unused (f
(=0)".
Sets the PLL operation for fsys to stop.
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2022-06-24
Rev. 1.1