Allen-Bradley ControlLogix 5570 Reference Manual page 101

To create a UDT that is the same size in all types of projects, insert additional
data elements so that hidden padding bytes are not necessary.
The following sample UDT illustrates how UnusedDint1 and UnusedDint2
were added to create a UDT with the same size in a Logix Designer project,
version 26 or earlier compared to a Logix Designer project, version 27 or later.
Figure 18 - UDT Sample - Memory Allocation and Alignment OK
Table 17 illustrates how this data structure maps in all types of Logix 5000
controller projects:
Table 17 - Memory Map in All Project Types
Word Elements
0 Bools and 2
1 Profile (Real [3])
2
3
4 Interlock (Int)
5 UnusedDint1
6 MyLint (LINT)
7
8 Speed (REAL)
9 UnusedDint2
The concept is the same for nested UDTs. If the lower-level UDT is an 8-byte
type (that is, it contains at least one 8-byte data element), you must align it to
start at an 8-byte boundary.
Rockwell Automation Publication 1756-RM100F-EN-P - October 2018
Standard Application Conversion
Byte Mapping Table
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Chapter 5
64 Bit Boundaries
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SINT
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