Table of Contents
Advertisement
P C 1 0 4 C P U M o d u l e
P F M - 5 4 0 I
A.1 Programming
PFM-540I utilizes IT8712F-A chipset as its watchdog timer
controller.
Below are the procedures to complete its configuration and the
AAEON intial watchdog timer program is also attached based on
which you can develop customized program to fit your application.
Configuring Sequence Description
After the hardware reset or power-on reset, the IT8712F-A enters
the normal mode with all logical devices disabled except KBC. The
initial state (enable bit ) of this logical device (KBC) is determined
by the state of pin 121 (DTR1#) at the falling edge of the system
reset during power-on reset.
Appendix A Programming the Watchdog Timer A-2
Advertisement
Table of Contents
