SimCom SIM7000G User Manual page 34

Table 15: PCM timing parameters
Parameter Description
T(sync) PCM_SYNC cycle time
T(synch) PCM_SYNC high level time
T(syncl) PCM_SYNC low level time
T(clk) PCM_CLK cycle time
T(clkh) PCM_CLK high level time
T(clkl) PCM_CLK low level time
PCM_SYNC setup time high before falling edge
T(susync)
of PCM_CLK
PCM_SYNC hold time after falling edge of
T(hsync)
PCM_CLK
PCM_IN setup time before falling edge of
T(sudin)
PCM_CLK
PCM_IN
T(hdin)
PCM_CLK
T(pdout) Delay from PCM_CLK rising to PCM_OUT valid
Delay from PCM_CLK falling to PCM_OUT
T(zdout)
HIGH-Z
SIM7000 _Hardware Design _V1.00
Figure 23: Module to external codec timing
hold time after falling
Smart Machine Smart Decision
Min. Typ.
– 125
– 488
– 124.5
– 488
– 244
– 244
– 122
– 366
60 –
edge of
60 –
– –
– –
Max. Unit
– μs
– ns
– μs
– ns
– ns
– ns
– ns
– ns
– ns
– ns
60 ns
60 ns
2017-05-23