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NXP Semiconductors MSC8113 Reference Manual

NXP Semiconductors MSC8113 Reference Manual

Tri core 16-bit digital signal processor

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MSC8113 Reference Manual

Tri Core 16-Bit Digital Signal Processor

MSC8113RM

Rev 0, May 2008

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Page 1 MSC8113 Reference Manual Tri Core 16-Bit Digital Signal Processor MSC8113RM Rev 0, May 2008...
Page 2 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 Information in this document is provided solely to enable system and software 2100 East Elliot Road implementers to use Freescale Semiconductor products. There are no express or Tempe, Arizona 85284 implied copyright licenses granted hereunder to design or fabricate any integrated +1-800-521-6274 or...
Page 3 Direct Slave Interface (DSI) Hardware Semaphores Direct Memory Access (DMA) Controller Interrupt Processing Debugging Internal Peripheral Bus (IPBus) Time-Division Multiplexing (TDM) Interface Universal Asynchronous Receiver/Transmitter (UART) Timers General-Purpose Input/Output (GPIO) C Software Module Ethernet Controller Programming Reference MSC8113 Dictionary MSC8113 Boot Code Index...
Page 4 Direct Slave Interface (DSI) Hardware Semaphores Direct Memory Access (DMA) Controller Interrupt Processing Debugging Internal Peripheral Bus (IPBus) Time-Division Multiplexing (TDM) Interface Universal Asynchronous Receiver/Transmitter (UART) Timers General-Purpose Input/Output (GPIO) C Software Module Ethernet Controller Programming Reference MSC8113 Dictionary MSC8113 Boot Code Index...
Page 5: Table Of Contents
Other MSC8113 Documentation ........
Page 6 SIU Multiplexing..........4-8 MSC8113 Reference Manual, Rev. 0...
Page 7 Single Slave MSC8113 Configuration by System Bus Host ... . . 5-10 5.5.3 Multi-MSC8113 System Configuration ......5-10 5.5.4 Multiple MSC8113 Devices in a System With No EPROM .
Page 8 Modes ............9-34 MSC8113 Reference Manual, Rev. 0...
Page 9 SDRAM Power-On Initialization ....... . . 12-14 MSC8113 Reference Manual, Rev. 0...
Page 10 Bank Interleaving ..........12-17 12.2.6 BNKSEL Signals in Single-MSC8113 Bus Mode ....12-18 12.2.7 SDRAM Address Multiplexing (SDAM and BSMA) .
Page 11 Single MSC8113 Bus Mode ........
Page 12 Synchronous Single Write Using Dual Strobe Mode....14-18 14.3.4.2 Synchronous Single Write Using Single Strobe Mode ....14-19 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 13 DMA Transfer Programming........16-29 MSC8113 Reference Manual, Rev. 0...
Page 14 PIC Registers..........17-40 17.3.3.1 Edge/Level-Triggered Interrupt Priority Registers ....17-40 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 15 Tracing in the MSC8113 ........
Page 16 Framing Error ..........21-17 MSC8113 Reference Manual, Rev. 0...
Page 17 Routine ....... . . 24-13 MSC8113 Reference Manual, Rev. 0...
Page 18 MSC8113 Ethernet Controller ........
Page 19 Programming Sheets ..........A-8 MSC8113 Dictionary MSC8113 Boot Code MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 20 Contents MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 21: About This Book
The MSC8113 device is based on the StarCore SC140 DSP core. It addresses the challenges of the networking market. The benefits of the MSC8113 include not only a very high level of performance but also a product design that enables effective software development and integration.
Page 22: Before Using This Manual-Important Note
This manual is intended for software and hardware developers and applications programmers who want to develop products with the MSC8113. It is assumed that you have a working knowledge of DSP technology and that you may be familiar with Freescale products based on the Freescale DSP56000 or DSP56300 core.
Page 23: Notational Conventions And Definitions
For example, BRCGx refers to BRCG[1–8], and MxMR refers to the MAMR/MBMR/MCMR registers. On the MSC8113 device, the SC140 cores are 16-bit DSP processors. The following table shows the SC140 assembly language data types. For details, see the StarCore SC140 DSP Core Reference Manual (MNSC140CORE/D).
Page 24: Conventions For Registers
Organization Following is a summary and a brief description of the chapters of this manual: „ Chapter 1, MSC8113 Overview. Features, descriptive overview of main modules, configurations, and application examples. „ Chapter 2, SC140 Core Overview. Target markets, features, overview of development tools, descriptive overview of main modules.
Page 25 „ Chapter 6, Boot Program. Describes the bootloader program, which loads and executes source code that initializes the MSC8113 after it completes a reset sequence and programs its registers for the required mode of operation. This chapter covers selection of bootloader modes, normal sequence of events for bootloading a source program, and booting in a multi-processor environment.
Page 26 „ Chapter 17, Interrupt Processing. Discusses the three interrupt controllers that provide maximum flexibility in handling MSC8113 interrupts, enabling interrupts to be handled by the SC140 core internally, by an external host, or by a combination of the two; also discusses source priority schemes.
Page 27: Other Msc8113 Documentation
You can find the following documents on the Freescale Semiconductor web site listed on the back cover of this manual. „ MSC8113 Technical Data sheet (MSC8113). Details the signals, AC/DC characteristics, PLL/DLL performance issues, clock configuration and signal characteristics, package and pinout, and electrical design considerations of the MSC8113 device.
Page 28 MSC8113 Reference Manual, Rev. 0 xxviii Freescale Semiconductor...
Page 29: Msc8113 Overview
MSC8113 Overview The MSC8113 device is a highly integrated DSP that combines three StarCore SC140 cores with large internal memory spaces, an extended core, and several industry-standard peripherals and external interfaces to target highly computational DSP network and communication applications.
Page 30: Features
MSC8113 Overview 1.1 Features The tables in this section list the features of the MSC8113 device. Table 1-1. Extended SC140 Cores and Core Memories Feature Description Three SC140 cores: • Up to 4800 MMACS using 12 ALUs running at up to 400 MHz.
Page 31 − Extensive external memory-controller/bus-slave support. − Parity byte select pin, which enables a fast, glueless connection to RMW-parity devices (on system bus only). − Data pipeline to reduce data set-up time for synchronous devices. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 32 • Frame sync can be programmed as active low or active high. • Selectable delay (0–3 bits) between the Frame Sync signal and the beginning of the frame. • MSB or LSB first support. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 33 I/O ports. port • Each port can be programmed separately to serve up to two dedicated peripherals, and each port supports open-drain output mode. • Supports booting from a serial EEPROM C Software Module MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 34 SMII domain. • SMII features: − Convey complete MII information between the PHY and MAC. − Allow direct MAC-to-MAC communication in SMII mode. − Can generate an interrupt request line while receiving inter-frame segments. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 35 Distributed System Support • Networking support; data transfer between tasks running inside and outside the device using networking protocols. • Includes integrated device drivers for such peripherals as TDM, UART, and external buses. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 36 Feature Description • Host debug through single JTAG connector supports both processors. • MSC8103 as the MSC8113 host with both devices on the board. The MSC8103 system bus connects to the MSC8113 DSI. • Flash memory for stand-alone applications. • Communications ports: −...
Page 37: Architecture
Banks 0–7 Figure 1-1. MSC8113 Block Diagram Data is transferred to the MSC8113 device from either the system bus port, the DSI, the Ethernet, the TDM, the Ethernet interface. The SC140 core processes the data in the buffers and the result is transferred back to one of the ports.
Page 38: Extended Core
DMA controller to transfer large blocks of data from the external memory to the internal memory and also between the internal memories. In some applications, data is written from an external host directly to the MSC8113 M1 and M2 memories through the DSI interface while the SC140 handles the computational work in parallel.
Page 39: Sc140 Core
MAC operation per clock cycle, so a single core running at 400 MHz can perform 1600 MMACS. Having three such cores, the MSC8113 can perform up to 4800 MMACS per second. An address generation unit includes two address arithmetic units and one bit mask unit. There are also 16 address registers, of which eight can serve as base address registers.
Page 40: M1 Memory
16 fetch sets, each with an associated valid bit. The 2-bit index field of the address serves as an index to the line within the way. The line whose tag matches the tag field of the address is the selected line. MSC8113 Reference Manual, Rev. 0 1-12 Freescale Semiconductor...
Page 41 When the SC140 core is in Debug mode, its fetch unit is in Debug mode and all the cache arrays can be read. Note: For details, see Section 9.4, Instruction Cache (ICache). MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 1-13...
Page 42: Qbus System
QBus masters.The bus switch handles all data read above the QBus baseline, write operations when the write buffer is disabled, and atomic (read modify write) write operations. Read accesses of program (fetch) that are above the QBus baseline occur through the fetch unit. MSC8113 Reference Manual, Rev. 0 1-14 Freescale Semiconductor...
Page 43: Power Saving Modes
1.2.2 Power Saving Modes The MSC8113 device is a low-power CMOS design. Also, you can put unused modules into power saving modes. The TDM, DSI, timers, GPIO, GIC, UART, and Ethernet controller can be put into Stop mode, in which their clocks are frozen as described in Section 19.10, Stop Options.
Page 44: Extended Core Stop Mode
The address and data buses support synchronous, one-level pipelined transactions and non-pipelined SRAM-like accesses. Various applications can use this bus interface—for example, a system in which the MSC8113 uses a shared external memory. An external host can directly access the device internal memories and peripherals because the system bus is bridged to the internal local bus where the memories and peripherals are located.
Page 45: Memory Controller
For details, seeChapter 12, Memory Controller. 1.2.5 Direct Slave Interface (DSI) The DSI gives an external host direct access to the MSC8113 internal and external memory space, including internal memories and the registers of internal modules as well as access to the system bus.
Page 46: Direct Memory Access (Dma) Controller
Latencies that are typical during accesses to internal memories are greatly reduced by the DSI read prefetch mechanism. An external host addresses up to 16 MSC8113 devices using a single chip-select by which the most significant bits on the address bus identify the addressed MSC8113 device.
Page 47: Internal And External Bus Architecture
For details, see Chapter 16, Direct Memory Access (DMA) Controller. 1.2.7 Internal and External Bus Architecture The SC140 cores and other MSC8113 modules interconnect via a variety of bus and interface structures that provide great flexibility for transferring and storing data both within the MSC8113 device and with external devices.
Page 48 — Sliding Window mode enables accesses with a reduced number of address lines. — Chip ID decoding enables the use of one signal for multiple DSPs. — Broadcast signal enables parallel writes to multiple DSPs. — Big-endian, little-endian, and munged little-endian support. MSC8113 Reference Manual, Rev. 0 1-20 Freescale Semiconductor...
Page 49: Tdm Serial Interface
25 MHz, and the sync is configured as either input or output. Each of the two receive links supports up to 128 channels, and each transmit link supports up to 128 channels. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 1-21...
Page 50: Ethernet Controller
On the transmit side, the SC140 core prepares buffers in memory and prepares a descriptor ring that points to those buffers. The Ethernet controller reads these descriptors, reads the data from the buffers, and sends the data over the Ethernet. Enhanced pattern matching MSC8113 Reference Manual, Rev. 0 1-22 Freescale Semiconductor...
Page 51: Universal Asynchronous Receiver/Transmitter (Uart)
For details, see Chapter 21, UART. 1.2.11 Timers The MSC8113 device contains 32 identical general-purpose 16-bit timers divided into two 16-timer groups. Within a group, each timer functions independently or as part of a programmable cascade of two timers. Each timer is programmable as either one-shot or cyclic.
Page 52: Gpios
PLL divide ratio, signal configuration, and the DSI host endian mode. This configuration word is initialized by writing to it either from the system configuration source. When the MSC8113 is reset from the system bus, the configuration word is latched using a dedicated signal.
Page 53: Interrupt Scheme
SC140 DSP core EOnCE module and some external interrupts. The PIC also receives interrupts from the LIC, which in turn concentrates interrupts from the MSC8113 peripherals (TDMs, timers, DMA controller, UART, and virtual interrupts), the SIU, and other external interrupts, such the Ethernet interface.
Page 54: Internal Communication And Semaphores
The value of the IFMODE bits in the MIIGSK Configuration Register. 1.3 Internal Communication and Semaphores The MSC8113 device contains flexible mechanisms for communicating between SC140 cores and between an SC140 core and an external host. An SC140 core sends a message to another SC140 core either by accessing an agreed location (mailbox) in the shared M2 memory or by accessing any of the M1 memories and using an interrupt to indicate the access.
Page 55: Atomic Operations
If the read value equals its lock number, the semaphore belongs to that host and is essentially locked. An SC140 core/host/task releases the semaphore by simply writing 0. Note: For details, see Chapter 15, Hardware Semaphores. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 1-27...
Page 56 MSC8113 Overview MSC8113 Reference Manual, Rev. 0 1-28 Freescale Semiconductor...
Page 57: Sc140 Core Overview
(such as moves or other operations on addresses). At a clock speed of 400 MHz, the SC140 can therefore execute 1600 true DSP MIPS—1600 million multiply-accumulate operations per second (MMACS), concurrent with associated data movement functions and pointer updates. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 58: Architecture
The SC140 DSP core defines the PLL Control Registers 0–1 (PCTL[0–1]) for PLL and clock control. The MSC8113 does not use these registers in its design. In addition, the manual defines six debug modules and seven EE signal lines in the EOnCE module.
Page 59: Data Arithmetic Logic Unit (Data Alu)
Architecture The MSC8113 device uses only two of these modules (0 and 1) and two signals (EE0 and EE1). 2.1.1 Data Arithmetic Logic Unit (Data ALU) The Data ALU performs arithmetic and logical operations on data operands in the MSC8113.
Page 60: Data Registers
16-bit × 16-bit fractional or integer multiplication between two’s complement signed, unsigned, or mixed operands. The 32-bit product is right-justified and added to the 40-bit contents of one of the sixteen data registers. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 61: Bit-Field Unit (Bfu)
„ Two stack pointers (NSP, ESP), only one of which is active at a time (SP) „ Four offset registers (N[0–3]) „ Four modifier registers (M[0–3]) „ A Modifier Control Register (MCTL) „ Two Address Arithmetic Units (AAU) „ One Bit Mask Unit (BMU) MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 62 „ Add or subtract an immediate value to/from an AGU register „ Compare to or test an AGU register „ Logical and arithmetic shift operations on AGU registers „ Sign or zero-extend an AGU register „ Add with reverse carry MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 63: Stack Pointer Registers
Stack instructions use the ESP when the MSC8113 is in the Exception mode of operation, which it enters when exceptions occur. The NSP is used in Normal mode, while not servicing an exception.
Page 64: Enhanced On-Chip Emulation (Eonce)
„ Vector Base Address Register (VBA) 2.1.4 Enhanced On-Chip Emulation (EOnCE) The EOnCE module allows nonintrusive interaction with the MSC8113 and its peripherals so that you can examine registers, memory, or on-chip peripherals, define various breakpoints, and read the trace-FIFO. These interactions facilitate hardware and software development on the MSC8113 processor.
Page 65 The address register modification is performed by either of the two AAUs. „ Stack Pointer Registers (NSP, ESP). The MSC8113 has two stack pointer registers: the Normal Stack Pointer (NSP) and the Exception Stack Pointer (ESP). These 32-bit registers are used implicitly in all PUSH and POP instructions.
Page 66 The address arithmetic unit (AAU) supports linear, modulo, multiple wrap-around modulo, and reverse-carry arithmetic types for most address register indirect addressing modes. When the modulo arithmetic is activated, the contents of Mj specify the modulus. MSC8113 Reference Manual, Rev. 0 2-10 Freescale Semiconductor...
Page 67: Data Arithmetic Logic Programming Model
LSP portion of the register is written with the word operand, and the MSP portion and EXT are either zero-extended or sign-extended from the LSP. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 68: Program Control Unit Programming Model
Note: GP4 equals the inversion of the HRCW bit 13. 2.3 Instruction Set Overview The SC140 instruction set is divided into the following functional groups: „ Data ALU arithmetic „ AGU arithmetic MSC8113 Reference Manual, Rev. 0 2-12 Freescale Semiconductor...
Page 69 Integer multiply unsigned times unsigned; first source from upper portion second from lower IMPYSU Integer multiply signed times unsigned IMPYUU Integer multiply unsigned times unsigned Increment a data register (as integer data) MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 2-13...
Page 70 TFRT Conditional data register transfer if the T bit is set TSTEQ Test for equal to zero TSTGE Test for greater than or equal to zero TSTGT Test for greater than zero MSC8113 Reference Manual, Rev. 0 2-14 Freescale Semiconductor...
Page 71 AGU arithmetic shift left (32-bit) ASRA AGU arithmetic shift right (32-bit) CMPEQA AGU compare for equal CMPGTA AGU compare for greater than CMPHIA AGU compare for higher (unsigned) DECA AGU decrement register MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 2-15...
Page 72 Move unsigned long from memory MOVEU.W Move unsigned integer word from memory VSL.2F Viterbi shift left: specialized move to support Viterbi kernel VSL.2W Viterbi shift left: specialized move to support Viterbi kernel MSC8113 Reference Manual, Rev. 0 2-16 Freescale Semiconductor...
Page 73 Logical Exclusive OR on a 16-bit operand in memory Binary inversion of a 16-bit operand NOT.W Binary inversion of a 16-bit operand in memory Logical OR on a 16-bit operand OR.W Logical OR on a 16-bit operand in memory MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 2-17...
Page 74 Do enable short - set the “nth” loop counter and enable the loop as a short loop DOSETUPn Setup the “nth” hardware loop start address SKIPLS Test the active LC and skip the loop if LCn is equal or smaller than zero MSC8113 Reference Manual, Rev. 0 2-18 Freescale Semiconductor...
Page 75: Additional Programming Considerations
SC140 core to enter a freeze state that can only be released by reset. The SC140 illegal instruction trap does not provide 100 percent protection against illegal instruction execution. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 2-19...
Page 76 SC140 Core Overview MSC8113 Reference Manual, Rev. 0 2-20 Freescale Semiconductor...
Page 77 External Signals The MSC8113 external signals are organized into functional groups, as shown in Table 3-1 and Figure 3-1. Table 3-1 lists the functional groups, the number of signal connections in each group, and references the table that gives a detailed listing of multiplexed signals within each group.
Page 78: External Signals
Note: Power signals are: V DD , V DDH , V CCSYN , GND, GND H , and GND SYN . Reserved signals can be left unconnected. NC signals must not be connected. Figure 3-1. MSC8113 External Signals MSC8113 Reference Manual, Rev. 0...
Page 79: Power Signals
Input Reset Configuration Used during reset configuration sequence of the chip. A detailed explanation of its function is provided in the MSC8113 Reference Manual. This signal is sampled upon deassertion of PORESET. Note: When PORESET is deasserted, the MSC8113 also samples the following signals: •...
Page 80: Direct Slave Interface, System Bus, Ethernet, And Interrupt Signals
HRESET Input/ Hard Reset Output When asserted as an input, this signal causes the MSC8113 to enter the hard reset state. After the device enters a hard reset state, it drives the signal as an open-drain output. SRESET Input/ Soft Reset Output When asserted as an input, this signal causes the MSC8113 to enter the soft reset state.
Page 81 ETHRXD2 Input Ethernet Receive Data 2 In MII mode only, bit 2 of the Ethernet receive data. Reserved Input In RMII mode, this pin is reserved and can be left unconnected. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 82 ETHTXD2 Output Ethernet Transmit Data 2 In MII mode only, bit 2 of the Ethernet transmit data. Reserved Input In RMII mode, this pin is reserved and can be left unconnected. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 83 Indicates that the receive data is valid. ETHCRS_DV Input Ethernet Carrier Sense/Receive Data Valid In RMII mode, indicates that a carrier is detected and after the connection is established that the receive data is valid. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 84 Input Host Chip ID 0–2 With HCID3, carries the chip ID of the DSI. The DSI is accessed only if HCS is asserted and HCID[0–3] matches the Chip_ID, or if HBCS is asserted. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 85 Used as a strobe for host read accesses. Input Host Read/Write Select (in Asynchronous/Synchronous single mode) Host read/write select. HRDE Input Host Read Data Enable (In Synchronous dual mode) Indicates valid data for host read accesses. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 86 Address Bus Output When the MSC8113 is in external master bus mode, these pins function as the system address bus. The MSC8113 drives the address of its internal bus masters and responds to addresses generated by external bus masters. When the MSC8113 is in internal master bus mode, these pins are used as address lines connected to memory devices and are controlled by the MSC8113 memory controller.
Page 87 Bus Grant Output When the MSC8113 acts as an internal arbiter, it asserts this pin as an output to grant bus ownership to an external bus master. When an external arbiter is used, it asserts this pin as an input to grant bus ownership to the MSC8113.
Page 88 Data Bus Grant Output When the MSC8113 acts as an internal arbiter, it asserts this pin as an output to grant data bus ownership to an external bus master. When an external arbiter is used, it asserts this pin as an input to grant data bus ownership to the MSC8113.
Page 89 The DMA drives this output to acknowledge the DMA transaction on the bus. EXT_DBG2 Output External Data Bus Grant 2 The MSC8113 asserts this pin to grant data bus ownership to an external bus master. IRQ3 Input Interrupt Request 3 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140.
Page 90 The DMA drives this output to acknowledge the DMA transaction on the bus. EXT_DBG3 Output External Data Bus Grant 3 The MSC8113 asserts this pin to grant data bus ownership to an external bus master. IRQ5 Input Interrupt Request 5 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140.
Page 91 See the System Interface Unit (SIU) chapter in the MSC8113 Reference Manual for details on how to configure these pins. When used as the bus control arbiter, the MSC8113 can support up to three external bus masters. Each master uses its own set of Bus Request, Bus Grant, and Data Bus Grant signals (BR/BG/DBG, EXT_BR2/EXT_BG2/EXT_DBG2, and EXT_BR3/EXT_BG3/EXT_DBG3).
Page 92: Memory Controller Signals
External Signals 3.5 Memory Controller Signals Refer to the Memory Controller chapter in the MSC8113 Reference Manual for details on configuring these signals. Table 3-6. Memory Controller Signals Signal Name Type Description BCTL0 Output System Bus Buffer Control 0 Controls buffers on the data bus. Usually used with BCTL1. The exact function of this pin is defined by the value of SIUMCR[BCTLC].
Page 93 In systems that store data parity in a separate chip, this output is used as the byte-select for that chip. PSDAMUX Output System Bus SDRAM Address Multiplexer Controls the system bus SDRAM address multiplexer when the MSC8113 is in external master mode. PGPL5 Output System Bus UPM General-Purpose Line 5 One of six general-purpose output lines from the UPM.
Page 94: Gpio, Tdm, Uart, And Timer Signals
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, see Chapter 23, GPIO. CHIP_ID0 Input Chip ID 0 Determines the chip ID of the MSC8113 DSI. It is sampled on the rising edge of PORESET signal. IRQ4 Input Interrupt Request 4 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core.
Page 95 Each signal is configured as either input to or output from the counter. For details, see Chapter 22, Timers. CHIP_ID2 Input Chip ID 2 Determines the chip ID of the MSC8113 DSI. It is sampled on the rising edge of PORESET signal. IRQ6 Input Interrupt Request 6 One of the fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core.
Page 96 Output Ethernet Transmit Data 3 For MII mode only, bit 3 of the Ethernet transmit data. Reserved Output For RMII or SMII mode, this pin is reserved and can be left unconnected. MSC8113 Reference Manual, Rev. 0 3-20 Freescale Semiconductor...
Page 97 Ethernet Carrier Sense/Receive Data Valid In RMII mode, this signal indicates that a carrier is sense or that the receive data is valid. Input Not Connected For SMII mode, this signal must be left unconnected. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 3-21...
Page 98 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140. ETHMDC Output Ethernet Management Clock Used for the MDIO reference clock for MII, RMII, and SMII modes. MSC8113 Reference Manual, Rev. 0 3-22 Freescale Semiconductor...
Page 99 As an input to the DMA, DONE closes the channel much like a normal channel closing. See the MSC8113 Reference Manual chapters on DMA and GPIO for information on configuring the DRACK or DONE mode and pin direction.
Page 100 As an input to the DMA, DONE closes the channel much like a normal channel closing. Note: See the MSC8113 Reference Manual chapters on DMA and GPIO for information on configuring the DRACK or DONE mode and pin direction. DRACK2...
Page 101 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, see Chapter 23, GPIO. UTXD Output UART Transmit Data MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 3-25...
Page 102 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, see Chapter 23, GPIO. CHIP_ID3 Input Chip ID 3 Determines the chip ID of the MSC8113 DSI. It is sampled on the rising edge of PORESET signal. ETHTX_EN Output Ethernet Transmit Enable Enables the Ethernet transmit controller for MII and RMII modes.
Page 103: Dedicated Ethernet Signals
In SMII mode, used for the Ethernet receive data. 3.8 EOnCE Event and JTAG Test Access Port Signals The MSC8113 uses two sets of debugging signals for the two types of internal debugging modules: EOnCE and the JTAG TAP controller. Each internal SC140 core has an EOnce module, but they are all accessed externally by the same two signals .
Page 104: Reserved Signals
Asynchronously initializes the test controller; must be asserted during power up. 3.9 Reserved Signals Table 3-10. Reserved Signals Signal Name Type Signal Description TEST Input Test Used for manufacturing testing. You must connect this pin to GND. MSC8113 Reference Manual, Rev. 0 3-28 Freescale Semiconductor...
Page 105 Configuration Registers Local Bus Reset Configuration Local Bus (32-Bit Address) System Bus Peripherals Ethernet Interface Interface SRAMs Note: msbs = most significant bits; lsbs = least significant bits. Figure 4-1. SIU Block Diagram MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 106: System Interface Unit (Siu)
A maskable interrupt is generated when the counter is equals the value programmed in the alarm register. The time counter (TMCNT) is clocked by the TIMERSCLK clock. See Section 4.1.3, Time Counter (TMCNT). MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 107: Bus Monitors
To allow variation in system peripheral response times, SYPCR[BMT] defines the time-out period, whose maximum value can be 2,040 system bus clocks. The timing mechanism is clocked by the system bus clock divided by eight. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 108: Timers Clock
The TMCNTSC enables or disables the various timer functions and reports the interrupt source. Figure 4-4 shows a block diagram of TMCNT, which is described on page 4-27 in Section 4.2.1, System Configuration and Protection Registers. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 109: Periodic Interrupt Timer (Pit)
The PIT is unaffected by reads. Figure 4-5 shows a block diagram of the PIT. PISCR[PTE] PITC TIMERSCLK Clock 16-Bit Modulus PISCR[PS] Counter for PIT Disable Interrupt PISCR[PIE] Figure 4-5. PIT Block Diagram MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 110: Siu And General Software Watchdog Timers
SC140 cores. The primary core coordinates the overall system protection and detects situations in which other SC140 cores are not responding and their general watchdog timer is not functioning (either timer MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 111 Figure 4-7 shows how to meet this need in the SWT. On the general timers, it is met by programming the required timer period value. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 112: Siu Multiplexing
Section 17.1.2.5, LIC Interrupt Sources. 4.1.6 SIU Multiplexing Some functions share signal connections. The pinout of the MSC8113 is shown in Chapter 3, External Signals. The control of the functionality used on a specific connection is shown in Table 4-2.
Page 113 Chapter 25, Ethernet Controller. HD[59]/D[59]/ETHMDIO HD[60]/D[60]/ETHCOL Multiplexing between host port functions is selected by the DSI control HD[61–63]/D[61–63]/NC registers. See Chapter 14, Direct Slave Interface (DSI). All functions starting with ETH belong to the Ethernet block. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 114 Reset EBM NPQM — EXDD — — — — — ISPS — — — — Type Reset ISPS BCR contains configuration bits for various features and wait states on the system bus. MSC8113 Reference Manual, Rev. 0 4-10 Freescale Semiconductor...
Page 115: Siu Programming Model
60x-compatible system bus master. APD indicates how many cycles the MSC8113 should wait for ARTRY, but because ARTRY can be asserted (by other masters) only on cacheable address spaces, APD is considered only on...
Page 116 External Master Delay Disable The memory controller inserts one wait state Generally, the MSC8113 adds a delay of one clock cycle between the assertion of TS and the assertion of for each external master access to a region controlled by CS when an external master accesses an the memory controller.
Page 117 ISPS Internal Space Port Size MSC8113 acts as a 64-bit slave to external Defines the port size of the MSC8113 internal space masters access to its internal space. region as seen by external masters. Setting ISPS enables MSC8113 acts as a 32-bit slave to external a 32-bit master to access the MSC8113 internal space.
Page 118 Reset Boot PPC_ALRH defines the arbitration priority of MSC8113 bus masters 0–7. Priority field 0 has the highest priority. The content of each priority field is the index number one bus master. For information on MSC8113 bus master indexes, see the description of PPC_ACR[PRKM] in Table 4-4.
Page 119 Priority Field 12 Priority Field 13 Priority Field 14 Priority Field 15 Type Reset Boot PPC_ALRL defines the arbitration priority of MSC8113 bus masters 8–15. Priority field 0 has the highest priority. LCL_ACR Local Bus Arbiter Configuration Register — DBGD —...
Page 120 Reset Boot LCL_ALRH defines the arbitration priority for MSC8113 local bus masters 0–7. Priority field 0 has the highest priority. The content of each priority field is the index number one bus master. For information about the MSC8113 local bus master indexes see LCL_ACR[PRKM] in Table 4-5.
Page 121 Priority Field 15 Type Reset Boot LCL_ALRL defines the arbitration priority of MSC8113 local bus masters 8–15. Priority field 0 has highest priority. The reset value is the recommended arbitration priority configuration for most applications. SIUMCR SIU Module Configuration Register...
Page 122 000 MSC8113 boots from system external memory. 7–9 This field is copied by power on reset 001 MSC8113 boots from External host (DSI or Power PC). from BM as part of the reset 010 MSC8113 boots from TDM. configuration sequence. It reflects the 011 MSC8113 boots from UART.
Page 123 INT_OUT line as open-drain of full INT_OUT line is driven with full drive. drive. This field has effect only if the INTOUT configuration bit selects INT_OUT functionality. — Reserved. Write to zero for future compatibility. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 4-19...
Page 124 In the MSC8113, all 15 bits can be programmed. See Chapter 8, Memory Map, for details on the device’s internal memory map and to Chapter 5, Reset, for the available default initial ISB values depending on ISBSEL.
Page 125 PBME System Bus Monitor Enable System bus monitor is disabled. System bus monitor is enabled. LBME Local Bus Monitor Enable Local bus monitor is disabled. Local bus monitor is enabled. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 4-21...
Page 126 0xAA39. SWSR is written at any time, but it returns all zeros when read. For details, see Section 4.1.5. TESCR1 System Bus Transfer Error Status and Control Register 1 ISBE — — — Type Reset — — — Type Reset MSC8113 Reference Manual, Rev. 0 4-22 Freescale Semiconductor...
Page 127 Set when TEA is asserted due to the system bus monitor time-out. ISBE Internal Space Bus Error Indicates that TEA was asserted due to error on a transaction to MSC8113 internal memory space. TESCR2[REGS] indicates that the internal access is to the SIU Registers address space (address hit IMMR).
Page 128 — Reserved. Write to zero for future compatibility. 2–6 Local Bus Bridge Error An error occurred in a transaction from the MSC8113 system bus to the local bus bridge. The bridge is non-burstable. Parity Error on Byte 8–15 There are eight parity error status bits, one per 8-bit lane. A bit is set for the byte with a parity error.
Page 129 Reserved. Write to zero for future compatibility. Transfer Type 11–15 Indicates the transfer type of the local bus transaction that caused the TEA. Table 13-10 describes the transfer types. — Reserved. Write to zero for future compatibility. 16–31 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 4-25...
Page 130 KHz. See Section 4.1.2, Timers Clock. Time Counter Enable The time counter is disabled. Is not affected by soft or hard reset. The time counter is enabled. MSC8113 Reference Manual, Rev. 0 4-26 Freescale Semiconductor...
Page 131: Periodic Interrupt Registers
The periodic interrupt registers described in this section are listed as follows: „ Periodic Interrupt Status and Control Register (PISCR), page 4-28 „ Periodic Interrupt Timer Count Register (PITC), page 4-28 „ Periodic Interrupt Timer Register (PITR), page 4-29 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 4-27...
Page 132 When the counter is enabled, it continues counting using the previous value. PITC Periodic Interrupt Timer Count Register PITC Type Reset — Type Reset PITC contains the 16 bits to be loaded in a modulus counter. MSC8113 Reference Manual, Rev. 0 4-28 Freescale Semiconductor...
Page 133 Reset Description Periodic Interrupt Timing Count 0–15 Contains the current count remaining for the periodic timer. Writes have no effect on this field. — Reserved. Write to zero for future compatibility. 16–31 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 4-29...
Page 134 System Interface Unit (SIU) MSC8113 Reference Manual, Rev. 0 4-30 Freescale Semiconductor...
Page 135 Initiates the soft reset flow. The MSC8113 device detects an external assertion of reset SRESET only if it occurs while the MSC8113 is not asserting reset. SRESET is an (SRESET) open-drain output. Upon soft reset, SRESET is driven, the SC140 extended cores are reset, and system configuration is maintained.
Page 136: Power-On Reset (Poreset)
PORESET least 16 input clock cycles after MSC8113 reach their nominal values. Table 5-3 shows the MSC8113 configuration signals. These signals are sampled at the rising edge of , which determines different MSC8113 configuration features. PORESET Table 5-3. PORESET External Configuration Signals...
Page 137 Table 5-4 configuration bit, define the pin multiplexing of the on page 5-3. low part of the MSC8113 DSI/system data bus with the Ethernet. For details on how the DSI64 signal functions, refer to Section 14.5.2, Status Registers, on page 14-35).
Page 138: Reset Configuration
Reset configuration write through the 60x-compatible system bus. MSC8113 is a configuration master. Reset configuration write through the 60x-compatible system bus. MSC8113 is a configuration slave. If the HRCW is not written during 1024 CLKIN cycles, it gets a default value of all zeros. Note: Always ensure that a valid configuration is written to the HRCW through the system bus.
Page 139 SPLL lock. Figure 5-1. Reset Configuration Write Through the DSI, Timing Diagram Figure 5-2 shows how to program the MSC8113 HRCW to multiple MSC8113 devices through the DSI port. The HRCW can be written separately for each device using a common...
Page 140: Reset Configuration Through The System Bus
MSC8113 CNFGS RSTCONF PORESET configuration mode. If the value is “01” the MSC8113 acts as a configuration slave. If the value is “00” the MSC8113 acts as a configuration master. Immediately after is deasserted PORESET and the reset operation mode is designated as configuration master or slave, the MSC8113 starts the configuration process by asserting throughout internal power-on reset.
Page 141 HRCW is kept. See Section 5.3, Hard CLKIN Reset, on page 5-8. After configuration, the MSC8113 device halts until the SPLL locks. As described in Chapter 7, Clocks, the SPLL locks according to , which are sampled on deassertion, MODCK[1–2]...
Page 142: Hard Reset
A hard reset sequence is initiated externally when is asserted or internally when the HRESET MSC8113 detects a reason to start the hard reset sequence (a software watch dog timer or a bus monitor timer expires). In both cases, the MSC8113 continuously asserts HRESET SRESET throughout the hard reset sequence.
Page 143: Reset Configuration Writes Through The System Bus
PORESET RSTCONF Figure 5-4. The MSC8113 can then access the EPROM. The HRCW is assumed to reside in an EPROM connected to of the configuration master. Because the port size of this EPROM is unknown to the configuration master before the HRCWs are read, the configuration master reads the HRCW byte-by-byte only from locations that are independent of port size.
Page 144: Single Slave Msc8113 Configuration By System Bus Host
The sequence of reset configuration write through the system bus, which occurs during hard reset, supports a system that uses up to eight MSC8113 devices, each configured differently. It needs no additional glue logic for reset configuration. In a typical multi-MSC8113 system, one MSC8113 device acts as the configuration master and all other MSC8113 devices act as configuration slaves.
Page 145 RSTCONF D[0–31] as its HRCW. Then, the master continues to configure all MSC8113 devices in the system. The configuration master always reads eight HRCWs, regardless of the number of MSC8113 devices in the system. Figure 5-6 shows a multi-device configuration. In this system, the configuration master initially reads its own HRCW.
Page 146 Configuration Slave 1 HRESET MSC8113 D[0–31] PORESET CNFGS RSTCONF Configuration Slave 2 HRESET MSC8113 PORESET D[0–31] CNFGS RSTCONF Configuration Slave 7 MSC8113 HRESET PORESET D[0–31] CNFGS RSTCONF Figure 5-6. Configuring Multiple MSC8113 Devices MSC8113 Reference Manual, Rev. 0 5-12 Freescale Semiconductor...
Page 147: Multiple Msc8113 Devices In A System With No Eprom
5.5.4 Multiple MSC8113 Devices in a System With No EPROM In some cases, the configuration master capabilities of the MSC8113 cannot be used. This can happen, for example, if there is no EPROM in the system or if the EPROM is not controlled by an MSC8113.
Page 148 SC140 cores disabled. 9, Extended Core. ISPS Internal Space Port Size MSC8113 acts as a 64-bit slave to Defines the initial value of BCR[ISPS]. Setting external masters access to its internal ISPS enables a 32-bit master to access the space.
Page 149 No DLL bypass. Defines whether the DLL mechanism is disabled. DLL bypass. See Section 7.3, Clock Configuration. Note: The MSC8113 does not support DLL operation. Always write a 1 to this bit to configure the device correctly. MODCK[3–5] MODCK High Order Bits 28–30...
Page 150: Reset Status Registers
RSR[SWRS], RSR[ESRS], and RSR[EHRS] are all set after a software watchdog reset. All bits are cleared by writing a 1 (writing zero has no effect). RSR is memory-mapped into the MSC8113 SIU register map. Table 5-9. RSR Bit Descriptions...
Page 151: Boot Program
The boot program, which resides in the internal ROM, initializes the MSC8113 after it completes a reset sequence. The MSC8113 device can boot from an external host through the DSI or the 60x-compatible system ports, execute a user boot program located on an external memory device...
Page 152: Boot Basics
Boot Program 6.1 Boot Basics The boot program initializes the MSC8113 with default values shown in Table 6-2. Table 6-2. Default MSC8113 Initialization Values of the Boot Program Where Discussed Module or Register Initialized UPMC and the GPCM as required to support the MSC8113 Section 12.7, Internal SRAM and IPBus Peripherals...
Page 153: Booting From An External Memory Device
Booting From an External Memory Device 6.2 Booting From an External Memory Device The MSC8113 device boots from an external memory device on the system bus. The MSC8113 boot program retrieves an address from the external memory and jumps to that address.
Page 154: Booting From An External Host (Dsi Or System Bus)
System Bus Memory Map View Example, on page 8-4. The external host should poll the Valid bit (V) of the BR10 register. The valid bit is set when the MSC8113 boot code finishes the default initialization and the external host can access the internal resources, including internal memory.
Page 155: Initializing The Tdm Physical Layer
Booting From the TDM Interface 6.4.1 Initializing the TDM Physical Layer The boot master transmits messages to multiple MSC8113 devices on TDM channel 0. Each MSC8113 transmits back on a different TDM channel that equals the MSC8113 CHIP_ID as defined in the DCIR. The MSC8113configures the size and type (T1 or non T1) of the received and transmitted frame by synchronizing to the TDM Clock and Sync signals of the master boot device.
Page 156: Receiver Initialization
Figure 6-3. 16 bit Receive Frame Non-T1 Configuration For a T1 receive operation, the TDM0RDAT is sampled for eight consecutive clock cycles starting two clocks after each first clock on which the TDM3RSYN is detected high. See Figure 6-4. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 157: Transmitter Initialization
For a non-T1 transmit operation, 8-bit channels are transmitted on the TDM3TDAT signal in consecutive clock cycles starting on the negative edge of the first clock after which the TDM3TSYN is detected high. See Figure 6-5. Each MSC8113 transmits on a channel that equals its chip ID.
Page 158: Tdm Logical Layer Handshake
Boot Program TDM3TSYN is detected high. See Figure 6-6. Each MSC8113 transmits on a channel that equals its chip ID. One Cycle Sync Delay TDMxTCLK TDMxTSYN FA D0 Dn FA TDMxTDAT Channel N Channel 0 Channel 1 Channel N Channel 0...
Page 159 4 bytes Destination Address of Data Block. The destination address for the data field of the slave MSC8113 internal memory as determined by the MSC8113 memory map (SC140 Core 0). See Figure 8-1, SC140 Core View Memory Map Example, on page 8-3. Addresses 0x01076E00–01076FFF are reserved and cannot be used.
Page 160: Operation
MSC8113 slave devices, but their correctness is not guaranteed. Note: The MSC8113 slave device RN value is initialized to zero at the start of the TDM boot session. When the HCRC field is received with no error and the CRC field is received with error, corrupt data is written to the MSC8113 slave device memory.
Page 161 Send BTAM with RN RN==SN? and SCID with my CHIP-ID RN = RN+1 Send BTAM with RN and SCID with my CHIP-ID End Block flag End TDM boot session Figure 6-7. MSC8113 Logic Layer Algorithm MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 6-11...
Page 162 Sixth Block Data block is not written to device number 2 and 7. DCID = 0xFF DA = 0x02012000 EB=1 Figure 6-8. TDM Block Stream Structure Example from TDM Master Boot Device MSC8113 Reference Manual, Rev. 0 6-12 Freescale Semiconductor...
Page 163: Booting From A Uart Device
In a system that boots from a UART device, a UART boot master device writes blocks of code and data into the memories of multiple MSC8113 devices (see Figure 6-8) and according to the memory map shown in Figure 8-6. UART booting occurs in a two-layer protocol: a UART physical layer and a UART logical layer handshake (see Section 6.4.2, TDM Logical Layer...
Page 164: Booting From I²C Slave Memory Device
6.6 Booting from I²C Slave Memory Device In a system that boots from an I C slave memory device, when the MSC8113 boot program finishes its default initialization, it starts to retrieve blocks from an external I C-slave memory device such as a serial EPROM, using the I C SM (see Chapter 24, I²C Software Module) that is...
Page 165 If the CSE bit is set and the first block retrieve fails, a second retrieve is performed. If the second retrieve fails, all cores enter debug-halt mode. Note: For the field size, the most significant byte is at the lower address. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 6-15...
Page 166: Procedure Flow
All cores enter debug-halt mode Next Block Addr Prepare Sequential Next Block Address = 0? Next Block Addr Prepare Next Block Address = 0xFFFFFFFF? End I C boot procedure Figure 6-10. I C Boot Procedure Flow MSC8113 Reference Manual, Rev. 0 6-16 Freescale Semiconductor...
Page 167: I 2 C System
Figure 6-11 shows the system connectivity for I C devices. MSC8113 Serial Memory C Slave C Master ID=0x1010000 MSC8113 Serial Memory C Slave C Master ID=0x1010001 MSC8113 C Master Figure 6-11. I C Boot System Example MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 6-17...
Page 168 Boot Program MSC8113 Reference Manual, Rev. 0 6-18 Freescale Semiconductor...
Page 169: Clocks
Clocks The MSC8113 device has two main clocks, CORES_CLOCK and BUSES_CLOCK, both of which are synchronized and phase aligned. The CORES_CLOCK supplies a timing signal for the extended core, including: „ SC140 cores „ M1 and M2 memories „ Instruction cache „...
Page 170: Clock Generation
CLKIN CLKOUT BUSES_CLOCK of all the MSC8113 devices. Figure 7-1 shows the MSC8113 clock scheme. is generated by an external oscillator and is fed to the SPLL that divides and multiplies its CLKIN frequency according to the PLLRDF, PLLFDF, PLLODF, and the BUSDF factors as configured by the System Clock Mode Status Register SCMSR) (see Section 7.4, Clocks Programming...
Page 171: Board-Level Clock Distribution
(SDRAMs, for example). With this method, the CLKOUT each MSC8113 device connects through a zero-delay buffer to the clock input pin of its dedicated slave devices on the board. Figure 7-3 illustrates a system in which each of three MSC8113 devices connects to a dedicated SDRAM memory device on the board through the zero-delay buffers.
Page 172 CLKOUT MSC8113 device connects directly to the clock input pin of its dedicated slave devices. Figure 7-4 illustrates a system in which each of three MSC8113 devices connects to a dedicated SDRAM memory device on the board. The maximum load on must not exceed 10 pF.
Page 173: Multi-Master Mode Board-Level Clock Distribution
MSC8113 device connects through CLKOUT a zero-delay buffer, to the clock input pins of the shared slave devices on the board. Figure 7-6 illustrates a system in which three MSC8113 devices connect to the one shared SDRAM memory device on the board. Note: Clocks marked with the same number of parallel lines should use an equivalent buffer and route on the board.
Page 174 CLKIN CLKIN connects to the input port of all the MSC8113 devices on the board and all the shared slave CLKIN device clock input ports as shown in Figure 7-7. You must chose one of the clock configuration modes for which the BUSES_CLOCK ratio is 1:1 (modes 0, 7, 15, 19, 21, 23, or 28–31 in...
Page 175: Clock Configuration
7.3 Clock Configuration and the MODCK[3–5] bits of the Hard Reset Configuration Word (HRCW), MODCK[1–2] discussed in Section 5.6.1, map the MSC8113 clocks to one of the valid 27 configuration mode options. Each option determines the , BUSES_CLOCK, and CORES_CLOCK frequency CLKIN ratios.
Page 176 „ F frequency range: 20–133 MHz. „ F frequency range: 800–2000 MHz. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 177 200 MHz 50 MHz 100 MHz 400 MHz 100 MHz 40 MHz 200 MHz 40 MHz 80 MHz 400 MHz 80 MHz 33.33 MHz 200 MHz 33.33 MHz 66.67 MHz 400 MHz 66.67 MHz MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 178: Clocks Programming Model
SPLL Output Clock Division Factor SPLL PODF = 1 Signal SPLL PODF = 2 DLLDIS Configuration DLL Disable DLL enabled. Signal Note: DLL operation is not supported. DLL disabled. Always write a 1 to this bit. MSC8113 Reference Manual, Rev. 0 7-10 Freescale Semiconductor...
Page 179 Signal 0011 Bus DF = 4 0100 Bus DF = 5 0101 Bus DF = 6 0111 Bus DF = 8 1001 Bus DF = 10 All other combinations are not used. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 7-11...
Page 180 Clocks MSC8113 Reference Manual, Rev. 0 7-12 Freescale Semiconductor...
Page 181: Memory Map
Memory Map The memory map of the MSC8113 system is composed of the following address spaces: „ SC140 core internal address space. Each SC140 core can access its M1 memory and EOnCE registers. (see Table 8-2). A boot master accesses the SC140 core 0 internal address space through the I C, TDM, or UART interface.
Page 182 Figure 8-1 shows the SC140 view of the memory map immediately after boot for the case in which the IMMR[ISBSEL] field equals 0. This figure is an example only; the ISBSEL field value is programmable. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 183 9 or 11 as appropriate. Internal accesses outside that range but See Table 8-2. M1 Memory above address 0x01800000 are EOnCE modules controlled by the QBus Bank 3. 0x00000000 Figure 8-1. SC140 Core View Memory Map Example MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 184 Figure 8-3 shows the view of the memory map from a host accessing through the DSI. 0x001FFFFF External Memory Window 0x001F0000 0x001DFFFF System Registers 0x001C0000 0x001BFFFF IPBus 0x00180000 0x0017FFFF M1 and M2 0x00000000 Figure 8-3. Host Accessing through the DSI Memory Map MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 185 Figure 8-4. TDM View Memory Map Figure 8-5 shows the memory map as viewed by the DMA and the Ethernet controllers. 0xFFFFFFFF Bank 11 0x0217FFFF M1 and M2 0x02000000 Figure 8-5. DMA and Ethernet Controller Memory Map MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 186 Boot ROM 0x01000000 0x00FFFFFF See Table 8-3. LIC/PIC ICache EQBS (Core 0) 0x00F00000 0x00EFFFFF See Table 8-2. M1 Memory EOnCE modules (Core 0) 0x00000000 Figure 8-6. UART and TDM Boot Master Memory Map View MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 187 Boot ROM 0x01000000 0x00FFFFFF See Table 8-3. LIC/PIC ICache EQBS (Core 0) 0x00F00000 0x00EFFFFF See Table 8-2. M1 Memory EOnCE modules (Core 0) 0x00000000 Figure 8-7. I C Boot Master Memory Map View MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 188: Sc140 Core Internal Address Space
EDCA3 reference value A 00EFFE70 EDCA4_REFA EDCA4 reference value A 00EFFE74 EDCA5_REFA EDCA5 reference value A 00EFFE78–00EFFE7F Reserved 00EFFE80 EDCA0_REFB EDCA0 reference value B 00EFFE84 EDCA1_REFB EDCA1 reference value B 00EFFE88 EDCA2_REFB EDCA2 reference value B MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 189: Qbus Address Space
SC140 core. QBus bank 0 includes the PIC, the LIC, and the EQBS registers. QBus bank 1 includes the MQBus interface through which the SC140 core accesses the M2 memory and the MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 190 LIC Group B Interrupt Status Register 00F0AC70 LICBIESR LIC Group B Interrupt Error Status Register 00F0AC72–00F0FBFF Reserved 00F0FC00 ICCR ICache Control Register 00F0FC02 ICCMR ICache Command Register 00F0FC04–00F0FC0F Reserved 00F0FC10 LRUSR LRU Status Register MSC8113 Reference Manual, Rev. 0 8-10 Freescale Semiconductor...
Page 191: Mqbus Address Space
Each SC140 core accesses the shared M2 memory and the boot ROM through the MQBus, which is mapped on bank 1 of the QBus. The Base Address Register (QBUSBR1) has a reset value of MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 192: Sqbus Address Space
TDM0 TDM0 Receive Channel Parameters Register 0–255 4 each RCPR[0–255] 01F81400–01F817FF Reserved 01F81800–01F81FFF TDM0 Transmit Local Memory 01F82000–01F827FF Reserved 01F82800–01F82BFC TDM0 TDM0 Transmit Channel Parameters Register 0–255 4 each TCPR[0–255] 01F82C00–01F83F1F Reserved MSC8113 Reference Manual, Rev. 0 8-12 Freescale Semiconductor...
Page 193 Reserved 01F86800–01F86BFC TDM1 TDM1 Transmit Channel Parameters Register 0–255 4 each TCPR[0–255] 01F86C00–01F87F1F Reserved 01F87F20 TDM1TSR TDM1 Transmit Status Register 01F87F28 TDM1RSR TDM1 Receive Status Register 01F87F30 TDM1ASR TDM1 Adaptation Status Register MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 8-13...
Page 194 TDM2 Transmit Status Register 01F8BF28 TDM2RSR TDM2 Receive Status Register 01F8BF30 TDM2ASR TDM2 Adaptation Status Register 01F8BF38 TDM2TER TDM2 Transmit Event Register 01F8BF40 TDM2RER TDM2 Receive Event Register 01F8BF48 TDM2TNB TDM2 Transmit Number of Buffers MSC8113 Reference Manual, Rev. 0 8-14 Freescale Semiconductor...
Page 195 TDM3 Receive Event Register 01F8FF48 TDM3TNB TDM3 Transmit Number of Buffers 01F8FF50 TDM3RNB TDM3 Receive Number of Buffers 01F8FF58 TDM3TDBDR TDM3 Transmit Data Buffer Displacement Register 01F8FF60 TDM3RDBDR TDM3 Receive Data Buffer Displacement Register MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 8-15...
Page 196 FIFO Receive Panic Shutoff Register 01FB8078 FTXSTATR FIFO Transmit Status Register 01FB807C–-1FB808B Reserved 01FB808C FTXTHR FIFO Transmit Threshold Register 01FB8094 FTXSPR FIFO Transmit Space Available Register 01FB8098 FTXSR FIFO Transmit Starve Register MSC8113 Reference Manual, Rev. 0 8-16 Freescale Semiconductor...
Page 197 01FB8390–01FB8393 Reserved 01FB8394 RBPTR2 RxBD Pointer 2 01FB8398–01FB839B Reserved 01FB839C RBPTR3 RxBD Pointer 3 01FB83A0–01FB8403 Reserved 01FB8404 RBASE0 Receive Descriptor Base Address 0 01FB8408–01FB840B Reserved 01FB840C RBASE1 Receive Descriptor Base Address 1 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 8-17...
Page 198 RXPF Receive PAUSE Frame Packet Counter 01FB86B8 RXUO Receive Unknown OP Code Counter 01FB86BC RALN Receive Alignment Error Counter 01FB86C0 RFLR Receive Frame Length Error Counter 01FB86C4 RCDE Receive Code Error Counter MSC8113 Reference Manual, Rev. 0 8-18 Freescale Semiconductor...
Page 199 01FB8814 IADDR5 Individual Address Register 5 01FB8818 IADDR6 Individual Address Register 6 01FB881C IADDR7 Individual Address Register 7 01FB8820–01FB887F Reserved 01FB8880 GADDR0 Group Address Register 0 01FB8884 GADDR1 Group Address Register 1 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 8-19...
Page 200 01FB8974–01FB8977 Reserved 01FB8978 PATTRB3 Pattern Attributes 3 Register 01FB8980 PMD4 Pattern Match Data 4 01FB8984–01FB8987 Reserved 01FB8988 PMASK4 Pattern Mask 4 Register 01FB898C–01FB898F Reserved 01FB8990 PCNTRL4 Pattern Control 4 Register 01FB8994–01FB8997 Reserved MSC8113 Reference Manual, Rev. 0 8-20 Freescale Semiconductor...
Page 201 Pattern Control 9 Register 01FB8A34–01FB8A37 Reserved 01FB8A38 PATTRB9 Pattern Attributes 9 Register 01FB8A40 PMD10 Pattern Match Data 10 01FB8A44–01FB8A47 Reserved 01FB8A48 PMASK10 Pattern Mask 10 Register 01FB8A4C–01FB8A4F Reserved 01FB8A50 PCNTRL10 Pattern Control 10 Register MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 8-21...
Page 202 Pattern Mask 15 Register 01FB8AEC–01FB8AEF Reserved 01FB8AF0 PCNTRL15 Pattern Control 15 Register 01FB8AF4–01FB8AF7 Reserved 01FB8AF8 PATTRB15 Pattern Attributes 15 Register 01FB8B00–01FB8BF7 Reserved 01FB8BF8 DATTR Default Attribute Register 01FB8C00–01F8FFF Reserved 01FB9000 MIIGSK_CFGR MIIGSK Configuration Register MSC8113 Reference Manual, Rev. 0 8-22 Freescale Semiconductor...
Page 203 Pin Special Options Register 01FBC228–01FBCFFF Reserved 01FBD000 SCIBR SCI Baud Rate Register 01FBD008 SCICR SCI Control Register 01FBD010 SCISR SCI Status Register 01FBD018 SCIDR SCI Data Register 01FBD020–01FBD027 Reserved 01FBD028 SCIDDR SCI Data Direction Register MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 8-23...
Page 204 01FBF0A0 TCMPA4 Timer Compare Register of Timer A4 01FBF0A8 TCMPA5 Timer Compare Register of Timer A5 01FBF0B0 TCMPA6 Timer Compare Register of Timer A6 01FBF0B8 TCMPA7 Timer Compare Register of Timer A7 MSC8113 Reference Manual, Rev. 0 8-24 Freescale Semiconductor...
Page 205 Timer Count Register of Timer A12 01FBF1E8 TCNRA13 Timer Count Register of Timer A13 01FBF1F0 TCNRA14 Timer Count Register of Timer A14 01FBF1F8 TCNRA15 Timer Count Register of Timer A15 01FBF200–01FBF37F Reserved MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 8-25...
Page 206 01FBF500 TCRB0 Timer Control Register of Timer B0 01FBF508 TCRB1 Timer Control Register of Timer B1 01FBF510 TCRB2 Timer Control Register of Timer B2 01FBF518 TCRB3 Timer Control Register of Timer B3 MSC8113 Reference Manual, Rev. 0 8-26 Freescale Semiconductor...
Page 207: Local Bus Address Space
The local bus address space comprises internal devices. The memory controller identifies banks 9–11 for these devices and generates chip selects and other signals for accessing these banks. The following resources reside on the local bus: MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 8-27...
Page 208 02EB7FFF 020B8000– 022B8000– 0248000– 026B8000– 02CB8000– 02EB8000– ICC0 ICache Core 0 16 K 020BBFFF 022BBFFF 024BFFF 026BBFFF 02CBBFFF 02EBBFFF 020BC000– 022BC000– 024C000– 026BC000– 02CBC000– 02EBC000– Reserved 020BFFFF 022BFFFF 024FFFF 026BFFFF 02CBFFFF 02EBFFFF MSC8113 Reference Manual, Rev. 0 8-28 Freescale Semiconductor...
Page 209 02383F28 02583F28 02783F28 02D83F28 02F83F28 TDM0RSR TDM0 Receive Status Register 02183F30 02383F30 02583F30 02783F30 02D83F30 02F83F30 TDM0ASR TDM0 Adaptation Status Register 02183F38 02383F38 02583F38 02783F38 02D83F38 02F83F38 TDM0TER TDM0 Transmit Event Register MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 8-29...
Page 210 02783FC8 02D83FC8 02F83FC8 TDM0TDBS TDM0 Transmit Data Buffer Size 02183FD0 02383FD0 02583FD0 02783FD0 02D83FD0 02F83FD0 TDM0RDBS TDM0 Receive Data Buffer Size 02183FD8 02383FD8 02583FD8 02783FD8 02D83FD8 02F83FD8 TDM0TFP TDM0 Transmit Frame Parameters MSC8113 Reference Manual, Rev. 0 8-30 Freescale Semiconductor...
Page 211 02F87F48 TDM1TNB TDM1 Transmit Number of Buffers 02187F50 02387F50 02587F50 02787F50 02D87F50 02F87F50 TDM1RNB TDM1 Receive Number of Buffers 02187F58 02387F58 02587F58 02787F58 02D87F58 02F87F58 TDM1TDBDR TDM1 Transmit Data Buffer Displacement Register MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 8-31...
Page 212 TDM1RIR TDM1 Receive Interface Register 02187FF8 02387FF8 02587FF8 02787FF8 02D87FF8 02F87FF8 TDM1GIR TDM1 General Interface Register 02188000– 02388000– 02588000– 02788000– 02D88000– 02F88000– TDM2 Receive Local 021887FF 023887FF 025887FF 027887FF 02D887FF 02F887FF Memory MSC8113 Reference Manual, Rev. 0 8-32 Freescale Semiconductor...
Page 213 02F8BF70 TDM2TIER TDM2 Transmit Interrupt Enable Register 0218BF78 0238BF78 0258BF78 0278BF78 02D8BF78 02F8BF78 TDM2RIER TDM2 Receive Interrupt Enable Register 0218BF80 0238BF80 0258BF80 0278BF80 02D8BF80 02F8BF80 TDM2TDBST TDM2 Transmit Data Buffer Second Threshold MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 8-33...
Page 214 0278D7FF 02D8D7FF 02F8D7FF 0218D800– 0238D800– 0258D800– 0278D800– 02D8D800– 02F8D800– TDM3 Transmit Local 0218DFFF 0238DFFF 0258DFFF 0278DFFF 02D8DFFF 02F8DFFF Memory 0218E000– 0238E000– 0258E000– 0278E000– 02D8E000– 02F8E000– Reserved 0218E7FF 0238E7FF 0258E7FF 0278E7FF 02D8E7FF 02F8E7FF MSC8113 Reference Manual, Rev. 0 8-34 Freescale Semiconductor...
Page 215 0278FF98 02D8FF98 02F8FF98 TDM3RDBFT TDM3 Receive Data Buffer First Threshold 0218FFA0 0238FFA0 0258FFA0 0278FFA0 02D8FFA0 02F8FFA0 TDM3TCR TDM3 Transmit Control Register 0218FFA8 0238FFA8 0258FFA8 0278FFA8 02D8FFA8 02F8FFA8 TDM3RCR TDM3 Receive Control Register MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 8-35...
Page 216 023B8048 025B8048 027B8048 02DB8048 02FB8048 FRXSTATR FIFO Receive Status Register 021B804C 023B804C 025B804C 027B804C 02DB804C 02FB804C FRXCTRLR FIFO Receive Control Register 021B8050 023B8050 025B8050 027B8050 02DB8050 02FB8050 FRXALAR FIFO Receive Alarm Register MSC8113 Reference Manual, Rev. 0 8-36 Freescale Semiconductor...
Page 217 OSTBD Out-of-sequence TxBD Register 021B82B4 023B82B4 025B82B4 027B82B4 02DB82B4 02FB82B4 OSTBDP Out-of-sequence Tx Data Buffer Pointer Register 021B82B8 023B82B8 025B82B8 027B82B8 02DB82B8 02FB82B8 OS32TBDP Out-of-sequence 32 Bytes Tx Data Buffer Pointer Register MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 8-37...
Page 218 Reserved 021B8403 023B8403 025B8403 027B8403 02DB8403 02FB8403 021B8404 023B8404 025B8404 027B8404 02DB8404 02FB8404 RBASE0 Receive Descriptor Base Address 0 021B8408– 023B8408– 025B8408– 027B8408– 02DB8408– 02FB8408– Reserved 021B840B 023B840B 025B840B 027B840B 02DB840B 02FB840B MSC8113 Reference Manual, Rev. 0 8-38 Freescale Semiconductor...
Page 219 02DB853C 02FB853C IFSTATR Interface Status Register 021B8540 023B8540 025B8540 027B8540 02DB8540 02FB8540 MACSTADDR MAC Station Address Part 1 Register 021B8544 023B8544 025B8544 027B8544 02DB8544 02FB8544 MACSTADDR MAC Station Address Part 2 Register MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 8-39...
Page 220 027B86C0 02DB86C0 02FB86C0 RFLR Receive Frame Length Error Counter 021B86C4 023B86C4 025B86C4 027B86C4 02DB86C4 02FB86C4 RCDE Receive Code Error Counter 021B86C8 023B86C8 025B86C8 027B86C8 02DB86C8 02FB86C8 RCSE Receive Carrier Sense Error Counter MSC8113 Reference Manual, Rev. 0 8-40 Freescale Semiconductor...
Page 221 023B8720 025B8720 027B8720 02DB8720 02FB8720 TXCF Transmit Control Frame Counter 021B8724 023B8724 025B8724 027B8724 02DB8724 02FB8724 TOVR Transmit Oversize Frame Counter 021B8728 023B8728 025B8728 027B8728 02DB8728 02FB8728 TUND Transmit Undersize Frame Counter MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 8-41...
Page 222 027B88FF 02DB88FF 02FB88FF 021B8900 023B8900 025B8900 027B8900 02DB8900 02FB8900 PMD0 Pattern Match Data 0 021B8904 023B8904 025B8904 027B8904 02DB8904 02FB8904 Reserved 021B8908 023B8908 025B8908 027B8908 02DB8908 02FB8908 PMASK0 Pattern Mask 0 Register MSC8113 Reference Manual, Rev. 0 8-42 Freescale Semiconductor...
Page 223 02DB898C 02FB898C Reserved 021B8990 023B8990 025B8990 027B8990 02DB8990 02FB8990 PCNTRL4 Pattern Control 4 Register 021B8994 023B8994 025B8994 027B8994 02DB8994 02FB8994 Reserved 021B8998 023B8998 025B8998 027B8998 02DB8998 02FB8998 PATTRB4 Pattern Attributes 4 Register MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 8-43...
Page 224 02DB8A24 02FB8A24 Reserved 021B8A28 023B8A28 025B8A28 027B8A28 02DB8A28 02FB8A28 PMASK9 Pattern Mask 9 Register 021B8A2C 023B8A2C 025B8A2C 027B8A2C 02DB8A2C 02FB8A2C Reserved 021B8A30 023B8A30 025B8A30 027B8A30 02DB8A30 02FB8A30 PCNTRL9 Pattern Control 9 Register MSC8113 Reference Manual, Rev. 0 8-44 Freescale Semiconductor...
Page 225 027B8AA8 02DB8AA8 02FB8AA8 PMASK13 Pattern Mask 13 Register 021B8AAC 023B8AAC 025B8AAC 027B8AAC 02DB8AAC 02FB8AAC Reserved 021B8AB0 023B8AB0 025B8AB0 027B8AB0 02DB8AB0 02FB8AB0 PCNTRL13 Pattern Control 13 Register 021B8AB4 023B8AB4 025B8AB4 027B8AB4 02DB8AB4 02FB8AB4 Reserved MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 8-45...
Page 226 MIIGSK Receive RIFBR Inter-Frame Bits Register 021B9018 023B9018 025B9018 027B9018 02DB9018 02FB9018 MIIGSK_ MIIGSK Expected Receive ERIFBR Inter-Frame Bits Register 021B901C 023B901C 025B901C 027B901C 02DB901C 02FB901C MIIGSK_ MIIGSK SMII Interrupt IEVENT Event Register MSC8113 Reference Manual, Rev. 0 8-46 Freescale Semiconductor...
Page 227 025BC138 027BC138 02DBC138 02FBC138 HSMPR7 Hardware Semaphore Register 7 021BC140– 023BC140– 025BC140– 027BC140– 02DBC140– 02FBC140– Reserved 021BC1FF 023BC1FF 025BC1FF 027BC1FF 02DBC1FF 02FBC1FF 021BC200 023BC200 025BC200 027BC200 02DBC200 02FBC200 PODR Pin Open-Drain Register MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 8-47...
Page 228 023BE05F 025BE05F 027BE05F 02DBE05F 02FBE05F 021BE060 023BE060 025BE060 027BE060 02DBE060 02FBE060 DEXTBAR DSI External Sliding Window Base Address Register 021BE068– 023BE068– 025BE068– 027BE068– 02DBE068– 02FBE068– Reserved 021BE7FF 023BE7FF 025BE7FF 027BE7FF 02DBE7FF 02FBE7FF MSC8113 Reference Manual, Rev. 0 8-48 Freescale Semiconductor...
Page 229 Timer Compare Register of Timer A0 021BF088 023BF088 025BF088 027BF088 02DBF088 02FBF088 TCMPA1 Timer Compare Register of Timer A1 021BF090 023BF090 025BF090 027BF090 02DBF090 02FBF090 TCMPA2 Timer Compare Register of Timer A2 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 8-49...
Page 230 Timer Control Register of Timer A5 021BF130 023BF130 025BF130 027BF130 02DBF130 02FBF130 TCRA6 Timer Control Register of Timer A6 021BF138 023BF138 025BF138 027BF138 02DBF138 02FBF138 TCRA7 Timer Control Register of Timer A7 MSC8113 Reference Manual, Rev. 0 8-50 Freescale Semiconductor...
Page 231 Timer Count Register of Timer A10 021BF1D8 023BF1D8 025BF1D8 027BF1D8 02DBF1D8 02FBF1D8 TCNRA11 Timer Count Register of Timer A11 021BF1E0 023BF1E0 025BF1E0 027BF1E0 02DBF1E0 02FBF1E0 TCNRA12 Timer Count Register of Timer A12 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 8-51...
Page 232 Timer Configuration Register of Timer B8 021BF448 023BF448 025BF448 027BF448 02DBF448 02FBF448 TCFRB9 Timer Configuration Register of Timer B9 021BF450 023BF450 025BF450 027BF450 02DBF450 02FBF450 TCFRB10 Timer Configuration Register of Timer B10 MSC8113 Reference Manual, Rev. 0 8-52 Freescale Semiconductor...
Page 233 Timer Compare Register of Timer B13 021BF4F0 023BF4F0 025BF4F0 027BF4F0 02DBF4F0 02FBF4F0 TCMPB14 Timer Compare Register of Timer B14 021BF4F8 023BF4F8 025BF4F8 027BF4F8 02DBF4F8 02FBF4F8 TCMPB15 Timer Compare Register of Timer B15 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 8-53...
Page 234 Timer Count Register of Timer B2 021BF598 023BF598 025BF598 027BF598 02DBF598 02FBF598 TCNRB3 Timer Count Register of Timer B3 021BF5A0 023BF5A0 025BF5A0 027BF5A0 02DBF5A0 02FBF5A0 TCNRB4 Timer Count Register of Timer B4 MSC8113 Reference Manual, Rev. 0 8-54 Freescale Semiconductor...
Page 235: System Bus Address Space
027BF7A0– 02DBF7A0– 02FBF7A0– Reserved 021BFFFF 023BFFFF 025BFFFF 027BFFFF 02DBFFFF 02FBFFFF 8.7 System Bus Address Space The system bus address space includes devices residing on the on-device or off-device system bus, as follows: MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 8-55...
Page 236 Memory Map „ The MSC8113 system registers are located on the system bus. These registers are mapped within a contiguous block of 128 KB of memory. The base address for this block is programmed as shown in Section 4.2, SIU Programming Model. The SC140 cores and external hosts access these registers through either the system bus or the DSI.
Page 237 0F010128 0FF10128 Base Register Bank5 F001012C F0F1012C FF01012C FFF1012C 0F01012C 0FF1012C Option Register Bank5 F0010130 F0F10130 FF010130 FFF10130 0F010130 0FF10130 Base Register Bank6 F0010134 F0F10134 FF010134 FFF10134 0F010134 0FF10134 Option Register Bank6 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 8-57...
Page 238 FFF101A0 0F0101A0 0FF101A0 LURT Local Bus-Assigned UPM Refresh Timer F00101A4 F0F101A4 FF0101A4 FFF101A4 0F0101A4 0FF101A4 LSRT Local Bus-Assigned SDRAM Refresh Timer F00101A8 F0F101A8 FF0101A8 FFF101A8 0F0101A8 0FF101A8 IMMR Internal Memory Map Register MSC8113 Reference Manual, Rev. 0 8-58 Freescale Semiconductor...
Page 239 0F010718 0FF10718 DCHCR6 DMA Channel 6 Configuration Register F001071C F0F1071C FF01071C FFF1071C 0F01071C 0FF1071C DCHCR7 DMA Channel 7 Configuration Register F0010720 F0F10720 FF010720 FFF10720 0F010720 0FF10720 DCHCR8 DMA Channel 8 Configuration Register MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 8-59...
Page 240 F0F10C88 FF010C88 FFF10C88 0F010C88 0FF10C88 SCMSR System Clock Mode Register F0010C90 F0F10C90 FF010C90 FFF10C90 0F010C90 0FF10C90 Reset Status Register F0010C94– F0F10C94– FF010C94– FFF10C94– 0F010C94– 0FF10C94– Reserved F001FFFF F0F1FFFF FF01FFFF FFF1FFFF 0F01FFFF 0FF1FFFF MSC8113 Reference Manual, Rev. 0 8-60 Freescale Semiconductor...
Page 241: Dsi Address Map
TDM0RDBFT TDM0 Receive Data Buffer First Threshold 183FA0 TDM0TCR TDM0 Transmit Control Register 183FA8 TDM0RCR TDM0 Receive Control Register 183FB0 TDM0ACR TDM0 Adaptation Control Register 183FB8 TDM0TGBA TDM0 Transmit Global Base Address MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 8-61...
Page 242 TDM1RGBA TDM1 Receive Global Base Address 187FC8 TDM1TDBS TDM1 Transmit Data Buffer Size 187FD0 TDM1RDBS TDM1 Receive Data Buffer Size 187FD8 TDM1TFP TDM1 Transmit Frame Parameters 187FE0 TDM1RFP TDM1 Receive Frame Parameters MSC8113 Reference Manual, Rev. 0 8-62 Freescale Semiconductor...
Page 243 TDM2 Transmit Frame Parameters 18BFE0 TDM2RFP TDM2 Receive Frame Parameters 18BFE8 TDM2TIR TDM2 Transmit Interface Register 18BFF0 TDM2RIR TDM2 Receive Interface Register 18BFF8 TDM2GIR TDM2 General Interface Register 18C000–18C7FF TDM3 Receive Local Memory 18C800–18CFFF Reserved MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 8-63...
Page 244 Reserved 1B8010 IEVENT Interrupt Event Register 1B8014 IMASK Interrupt Mask Register 1B8020 ECNTRL Ethernet Control Register 1B8024 MINFLR Minimum Frame Length Register 1B8028 Pause Time Value Register 1B802C DMACTRL DMA Control Register MSC8113 Reference Manual, Rev. 0 8-64 Freescale Semiconductor...
Page 245 Out-of-sequence 32 Bytes TxBD Insert Index/Length Register 1B82CC–1B82FF Reserved 1B8300 RCTRL Receive Control Register 1B8304 RSTAT Receive Status Register 1B8308–1B830B Reserved 1B830C RBDLEN RxBD Data Length 1B8310–1B8323 Reserved 1B8324 CRBPTRL Current RxBD pointer 1B8328–1B833F Reserved MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 8-65...
Page 246 Transmit and Receive 65- To 127-byte Frame Counter 1B8688 TR255 Transmit and Receive 128- To 255-byte Frame Counter 1B868C TR511 Transmit and Receive 256- To 511-byte Frame Counter 1B8690 TR1K Transmit and Receive 512- To 1023-byte Frame Counter MSC8113 Reference Manual, Rev. 0 8-66 Freescale Semiconductor...
Page 247 Transmit Control Frame Counter 1B8724 TOVR Transmit Oversize Frame Counter 1B8728 TUND Transmit Undersize Frame Counter 1B872C TFRG Transmit Fragments Frame Counter 1B8730 CAR1 Carry Register One 1B8734 CAR2 Carry Register Two MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 8-67...
Page 248 1B8934–1B8937 Reserved 1B8938 PATTRB1 Pattern Attributes 1 Register 1B8940 PMD2 Pattern Match Data 2 1B8944–1B8947 Reserved 1B8948 PMASK2 Pattern Mask 2 Register 1B894C–1B894F Reserved 1B8950 PCNTRL2 Pattern Control 2 Register 1B8954–1B8957 Reserved MSC8113 Reference Manual, Rev. 0 8-68 Freescale Semiconductor...
Page 249 Pattern Control 7 Register 1B89F4–1B89F7 Reserved 1B89F8 PATTRB7 Pattern Attributes 7 Register 1B8A00 PMD8 Pattern Match Data 8 1B8A04–1B8A07 Reserved 1B8A08 PMASK8 Pattern Mask 8 Register 1B8A0C–1B8A0F Reserved 1B8A10 PCNTRL8 Pattern Control 8 Register MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 8-69...
Page 250 1B8AAC–1B8AAF Reserved 1B8AB0 PCNTRL13 Pattern Control 13 Register 1B8AB4–1B8AB7 Reserved 1B8AB8 PATTRB13 Pattern Attributes 13 Register 1B8AC0 PMD14 Pattern Match Data 14 1B8AC4–1B8AC7 Reserved 1B8AC8 PMASK14 Pattern Mask 14 Register 1B8ACC–1B8ACF Reserved MSC8113 Reference Manual, Rev. 0 8-70 Freescale Semiconductor...
Page 251 Hardware Semaphore Register 2 1BC118 HSMPR3 Hardware Semaphore Register 3 1BC120 HSMPR4 Hardware Semaphore Register 4 1BC128 HSMPR5 Hardware Semaphore Register 5 1BC130 HSMPR6 Hardware Semaphore Register 6 1BC138 HSMPR7 Hardware Semaphore Register 7 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 8-71...
Page 252 1BF028 TCFRA5 Timer Configuration Register of Timer A5 1BF030 TCFRA6 Timer Configuration Register of Timer A6 1BF038 TCFRA7 Timer Configuration Register of Timer A7 1BF040 TCFRA8 Timer Configuration Register of Timer A8 MSC8113 Reference Manual, Rev. 0 8-72 Freescale Semiconductor...
Page 253 1BF170 TCRA14 Timer Control Register of Timer A14 1BF178 TCRA15 Timer Control Register of Timer A15 1BF180 TCNRA0 Timer Count Register of Timer A0 1BF188 TCNRA1 Timer Count Register of Timer A1 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 8-73...
Page 254 1BF488 TCMPB1 Timer Compare Register of Timer B1 1BF490 TCMPB2 Timer Compare Register of Timer B2 1BF498 TCMPB3 Timer Compare Register of Timer B3 1BF4A0 TCMPB4 Timer Compare Register of Timer B4 MSC8113 Reference Manual, Rev. 0 8-74 Freescale Semiconductor...
Page 255 1BF5D0 TCNRB10 Timer Count Register of Timer B10 1BF5D8 TCNRB11 Timer Count Register of Timer B11 1BF5E0 TCNRB12 Timer Count Register of Timer B12 1BF5E8 TCNRB13 Timer Count Register of Timer B13 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 8-75...
Page 256 Local Bus DMA Transfer Error RQNUM 1D006D–1D00FF Reserved 1D0100 Base Register Bank0 1D0104 Option Register Bank0 1D0108 Base Register Bank1 1D010C Option Register Bank1 1D0110 Base Register Bank2 1D0114 Option Register Bank2 MSC8113 Reference Manual, Rev. 0 8-76 Freescale Semiconductor...
Page 257 Reserved 1D01A8 IMMR Internal Memory Map Register 1D01AC–1D021F Reserved 1D0220 TMCNTSC Time Counter Status and Control Register 1D0222–1D0223 Reserved 1D0224 TMCNT Time Counter Register 1D0228–1D022B Reserved 1D022C TMCNTAL Time Counter Alarm Register MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 8-77...
Page 258 DMA External Mask Register 1D0794–1D07FF Reserved 1D0800–1D0BFF DCPRAM DMA Channel Parameter RAM 1024 1D0C00–1D0C87 Reserved 1D0C88 SCMSR System Clock Mode Register 1D0C90 Reset Status Register 1D0C94–1EFFFF Reserved 1F0000–1FFFFF External memory access offset MSC8113 Reference Manual, Rev. 0 8-78 Freescale Semiconductor...
Page 259: Pseudo Command Address Space
4-6. — Read data not valid. „ Data stored in the internal memories is accessed by the extended core as big-endian. „ Bytes within registers can be accessed unless specified otherwise. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 8-79...
Page 260 Memory Map MSC8113 Reference Manual, Rev. 0 8-80 Freescale Semiconductor...
Page 261: Extended Core
Extended Core Each MSC8113 SC140 core is embedded in an extended core system that enhances the power of the SC140 core and provides a simple interface to each SC140 core. The extended core system includes: „ SC140 core „ M1 memory (224 KB) „...
Page 262: Sc140 Dsp Core
Note: See Chapter 2, SC140 Core Overview for details on the SC140 core. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 263: Extended Core Memory (M1)
The four 24-bit address memory ports include: „ P (program) 128-bit data read. „ Xa (data) 64-bit read and write. „ Xb (data) 64-bit read and write. „ L (data) 64-bit read and write. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 264: Memory Organization
(see Figure 9-4). This interleaving makes efficient use of the two data buses and minimizes memory contentions. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 265 Module 7 line 15 line 7 line 1017 Module 1 line 9 line 1 line 1016 Module 0 line 8 line 0 Group I/O Xa-Bus Xb-Bus P-Bus L Port Figure 9-4. Memory Interleaving MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 266: Memory Contention And Priority
„ Misaligned data. When the address on the data buses (Xa or Xb) is misaligned with the data size, a misaligned data exception occurs and is generated internally. IRQ13 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 267: Extended Qbus System
IRQ11 9.3 Extended QBus System The EQBS is the SC140 extended core interface to the MSC8113 system through the QBus. The module handles the SC140 core and the instruction cache requests, bringing the data on the QBus. As Figure 9-5 shows, the EQBS consists of a bus switch, a write buffer, a fetch unit, a control unit, and the banks to handle the communication with the slaves and all EQBS registers.
Page 268: Architecture
Upon detecting a read from an address held in the write buffer, the write buffer flushes all its contents and only then execute the read. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 269: Fetch Unit
“miss” access occurs. The prefetch phase greatly improves cache performance in a system running a program with sequential code because in the next access to the code area, the data is probably already in the cache. The prefetch occurs in two phases: MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 270 The fetch unit can stop an incomplete prefetch access. If a prefetch is executing and a new P access that is a “miss” is waiting on the SC140 core buses, the fetch unit stops the prefetch immediately and puts the new miss on the QBus. MSC8113 Reference Manual, Rev. 0 9-10 Freescale Semiconductor...
Page 271: Qbus Execution Order
This ensures that system register updates are not delayed in the write buffer. „ Bank 1 can be used to put any slave or interface on the QBus. In the MSC8113 it is used for M2 (shared) memory.
Page 272: Bank Registers
DSP peripherals on the QBus, Icache Zero-wait state mode base0 = 0x00F0 registers and bank registers mask0 = 0xFFFF Bank 1 In the MSC8113 it is used for M2 Acknowledge mode base1 = 0x0100 (shared) memory mask1 = 0xFF80 Note:...
Page 273 Table 9-3. Example Bank Address and Mask Register Values Base Register Mask Register Bank Size Address Range for a Match 0x001F 0xFFFF 64 KB 0x001F0000–0x001FFFFF 0x001C 0xFFFC 256 KB 0x001C0000–0x001FFFFF MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 9-13...
Page 274: Reservation Process
„ The master sends a signal to assert that the atomic transaction (read-modify-write) is valid on the bus. „ The slave asserts a result signal when the atomic operation succeeds. This result signal is duplicated for each bank. MSC8113 Reference Manual, Rev. 0 9-14 Freescale Semiconductor...
Page 275: Setting A Data Area
32 MB xxxxxxx10000000000000000 xxxxxx000000000000000000 xxxxxx100000000000000000 64 MB xxxxx0000000000000000000 128 MB xxxxx1000000000000000000 xxxx00000000000000000000 256 MB xxxx10000000000000000000 xxx000000000000000000000 512 MB xxx100000000000000000000 xx0000000000000000000000 1 GB xx1000000000000000000000 x00000000000000000000000 2 GB x10000000000000000000000 000000000000000000000000 4 GB 100000000000000000000000 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 9-15...
Page 276 1 is the immediate area. Size 0 Area Size 1 Area Data Area 1 (reverse) Base 1 Area Data Area 0 Base 0 Area Figure 9-8. Reverse Area Inside an Area MSC8113 Reference Manual, Rev. 0 9-16 Freescale Semiconductor...
Page 277: Instruction Cacheable Area
The steps in defining this area are as follows: Write the base address in 32-bit representation. 32 MB is written as 00000010000000000000000000000000. Based on the size (256 KB), choose line 3 in the table. The size_bit = 0. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 9-17...
Page 278: Eqbs Programming Model
„ Instruction Cacheable Area Base Register (ICABR), page 9-20 „ Instruction Fetch Unit Configuration Register (IFUR), page 9-20 „ Write Buffer Software Flush Register (WBFR), page 9-21 „ Write Buffer Control Register (WBCR), page 9-21 MSC8113 Reference Manual, Rev. 0 9-18 Freescale Semiconductor...
Page 279 = 0xFF80 The mask value of the bank. with a write to the register. mask2 = 0xFFFF 2. Do not access an external read or write one cycle after writing to the register. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 9-19...
Page 280 The base address for the area defining the cacheable area. The range below the 16 MB address (0x00000000–0x00FFFFFF) is defined as not cacheable. IFUR Instruction Fetch Unit Configuration Register 0x00F0FF60 — — — — — — — — — — — PFOFF — SIZE Type Reset Boot MSC8113 Reference Manual, Rev. 0 9-20 Freescale Semiconductor...
Page 281 Disable write buffer operation. buffer is disabled, all write execute through the bus switch. — Reserved. Write to zero for future compatibility. 4–5 0x3ff Watchdog Count 6–15 Value for watch dog count. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 9-21...
Page 282 Indicates whether the size is 256 bytes or not. Size is 256 bytes. BASE Base Address 15–8 See Section 9.3.7, Setting a Data Area, on 24–31 The area base address. page 9-15. MSC8113 Reference Manual, Rev. 0 9-22 Freescale Semiconductor...
Page 283 Contains a different number for each process version. ECVer 0x52 Extended Core Version 8–15 Contains a different number for each extended core version. FLBACR0 FlyBy Address Control Register 0x00F0FFF4 FLBSA[20–5] Type Reset FLBSA[4–0] — Type Reset MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 9-23...
Page 284: Instruction Cache (Icache)
PBus XA-Bus XB-Bus Figure 9-9. MSC8113 ICache System The MSC8113 ICache has the following features: „ 16 KB of memory „ 16-way associativity „ 4 indexes, so the ICache has a total of 64 lines. „ 16 fetch sets for each line. Each fetch set is 16 bytes.
Page 285 Each of the three extended cores in the MSC8113 has its own ICache. Each of these ICache memories optimizes access to its instruction storage area by using a specialized indexing system.
Page 286 „ If the upper 22 bits of the address match the tag and index in a cache line, but the VALID bit for the fetch set position is clear, code is transferred from memory to the SC140 core and written into the cache. MSC8113 Reference Manual, Rev. 0 9-26 Freescale Semiconductor...
Page 287 Configuration allows a trade-off between efficient use of the system bus and burdening the QBus with transactions that the SC140 core may not need. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 9-27...
Page 288: Icache Attributes
Extended Core 9.4.1 ICache Attributes The diagram in Figure 9-11 gives a logical view of the MSC8113 ICache. Valid Bits Memory ..TAG 0 Line 0 ..TAG 1 Line 1 ..
Page 289: Debugging
16 bits of the contents of the resource to which it belongs. To read the ICache status, the SC140 core performs a read from a specific memory address. The contents of MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 290 Reload (way0, index1, tag bits [15–0]) Read tag array status 1: 16 bits, line: way 0, index1, tag bits [15–0] Reload (way0, index1, tag bits [21–16] (padded)) (More tag array status reads) MSC8113 Reference Manual, Rev. 0 9-30 Freescale Semiconductor...
Page 291 ICache is not in Debug mode, the command is discarded. An exception flag in the ICache is raised for a PIC to use, and the interrupt takes effect only in systems with the cache connected to the PIC. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 9-31...
Page 292: Multi-Task Support
In the fixed allocation mechanism, the OS reserves a cache space for each task. When a new task resumes operation, it works only with the cache space allocated for it, meaning that each task should change the lower and upper boundaries of the cache space. MSC8113 Reference Manual, Rev. 0 9-32 Freescale Semiconductor...
Page 293: Icache Programming Model
Through the programming interface, you can set cache modes, send commands to the ICache, and read ICache registers. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 9-33...
Page 294: Modes
„ Clear line. Clear all valid bits for a specific tag (line = {way[3–0],index[1–0]}, unlike lines for reads). For breakpoint insertion. „ Initialize status registers. Perform an initial load to the different cache status registers. MSC8113 Reference Manual, Rev. 0 9-34 Freescale Semiconductor...
Page 295: Reads
(an exception flag is raised). There must be at least one execution set between the time when the debug mode bit is turned on and the time when the first debug MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 9-35...
Page 296: Icache Registers
Cache in debug mode. — Reserved. Write to zero for future compatibility. Cache Lock Mode Cache not locked. Enables/disables cache locking. Cache locked. On/Off Bit Cache disabled. Enables/disables the iCache. Cache enabled. MSC8113 Reference Manual, Rev. 0 9-36 Freescale Semiconductor...
Page 297 LRU for the specified index and a 1 indicates that the line is the LRU for that index. TASR Tag Array Status Register 0x00F0FC12 TS[15–0] Type Reset MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 9-37...
Page 298: Programmable Interrupt Controller (Pic)
9.5 Programmable Interrupt Controller (PIC) The MSC8113 PIC is a peripheral module that serves the signals received from MSC8113 peripherals and GPIOs. The PIC is memory-mapped to the SC140 and is accessed via the SC140 QBus. The PIC includes 32 inputs for signals and...
Page 299: Extended Core Power Saving Modes
QBus, PIC, LIC, and MQBus and SQBus controllers are functional. The extended core exits Wait mode when there is an interrupt or a reset or when the MSC8113 device enters Debug mode by either a JTAG DEBUG_REQUEST command or assertion of...
Page 300 Extended Core MSC8113 Reference Manual, Rev. 0 9-40 Freescale Semiconductor...
Page 301: Mqbus And M2 Memory
Local Bus SC140 Extended Core SC140 Extended Core EQBS EQBS MQBus QBus QBus MQBS SQBS SQBS MQBS MQBus Arbiter SQBS MQBS QBus EQBS SC140 Extended Core Figure 10-1. M2 Memory and MQBus System MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 10-1...
Page 302: Mqbus Arbitration Model
(high priority) waiting for execution, the current request is upgraded to high priority so that the arbitration latency for the program miss access is reduced. In addition, MSC8113 Reference Manual, Rev. 0 10-2 Freescale Semiconductor...
Page 303: M2 Memory
(or eight) wait state accesses are rare. Because there are three SC140 cores in the MSC8113, the MQBus may be occupied and one SC140 core access may require more than six (or eight) wait states. However, an application that carefully considers memory allocation and wisely uses the ICache significantly reduces the miss ratio of all three SC140 cores, reducing the number of miss accesses to M2 memory.
Page 304 MQBus and M2 Memory MSC8113 Reference Manual, Rev. 0 10-4 Freescale Semiconductor...
Page 305 It can access the M1 memory of another extended core. Moreover, an SC140 core can access other devices on the system. For example, it can configure the DMA controller of yet another MSC8113 device on the system or directly access the M1 and M2 memories of that device.
Page 306: System Bus Interface
Using the global bit described in Section 9.3.9, EQBS Programming Model, on page 9-18, the signal on the system bus is asserted. This signal typically indicates that the MSC8113 device is writing to a cacheable area. The off-device data cache uses this signal to flag a corrupted entry.
Page 307: Reservation Operation In The Sqbus Arbiter
„ A system bus burst write of 32 bytes or less (24 or 16 bytes) to one of the 32 bytes that have the same most significant bits as the reserved address (ignoring the last five bits). MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 308 SQBus MSC8113 Reference Manual, Rev. 0 11-4 Freescale Semiconductor...
Page 309: Memory Controller
Memory Controller The MSC8113 memory controller serves two purposes: „ It supports a glueless interface to external memory and peripheral devices on the external system bus. „ It enables interfacing with the IPBus peripherals and internal memories through the internal local bus.
Page 310 Memory Controller Figure 12-1 shows the MSC8113 dual-bus architecture. MSC8113 External Master System Bus System SC140 Cores Master Interface A[0–31] System Address Bus[0–31] System Address Bus Interface 60x-compatible System Bus D[0–63] System Data Bus [0–63] System Data Bus Interface GPCM...
Page 311: Basic Architecture
„ Each external memory bank can be controlled by an external memory controller or bus slave. The memory controllers functionality minimizes the need for glue logic in MSC8113-based systems. In Figure 12-3, is used with the 16-bit boot EPROM with BR0[MS] defaulting to select the GPCM.
Page 312 Local Bus BR11[MS] General-Purpose Chip-Select Machine Figure 12-2. Memory Controller Machine Selection MSC8113 EPROM Address Address POE/PGPL2 GPCM PWE[0–3]/PBS[0–3] Data Data DRAM Address UPMA CAS[0–3] PGPLx Data Figure 12-3. Simple System Configuration MSC8113 Reference Manual, Rev. 0 12-4 Freescale Semiconductor...
Page 313 ( ) can be assigned to either UPMA or UPMB. In the CS[0–7] MSC8113 device, one internal bank on the local bus uses the UPMC to access the internal memories ( CS11 Each UPM is a programmable RAM-based machine. It toggles the memory controller external signals as programmed in RAM when an internal or external master initiates any external read or write access.
Page 314 Figure 12-6 shows a memory controller access in the non 60x-compatible mode and demonstrates the validity period of each group of signals involved in the access, as well as the relationships between the various groups. MSC8113 Reference Manual, Rev. 0 12-6 Freescale Semiconductor...
Page 315 MEMC Controlled Signals Note: The MEMC address is either BADDR and/or external latched address controlled by ALE and/or multiplexed address controlled by PSDMAMUX. Figure 12-7. Timing Diagram for MEMC Access in 60x-Compatible Mode MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-7...
Page 316: Address And Address Space Checking
2. Also, using RMW parity on a bank with a 32-bit port size requires that the system bus be placed in strict 60x mode by setting BCR[ETM] to 0. See Section 4.2, SIU Programming Model. MSC8113 Reference Manual, Rev. 0 12-8 Freescale Semiconductor...
Page 317: Transfer Error Acknowledge (Tea) Generation
The memory controller asserts the transfer error acknowledge signal ( ) (if enabled) in the following cases: „ An unaligned or burst access is attempted to internal MSC8113 space (registers). „ Any SC140 core or an external master attempts a burst access to the local bus address space.
Page 318: Atomic Bus Operation
64 bits (8 bytes) of data is transferred. Because the MSC8113 device memories can have port sizes smaller than 64 bits, there is a need for a partial data valid indication. The memory controller uses...
Page 319: Ecc/Parity Byte-Select (Ppbs)
Programming Model. 12.1.10 Data Pipelining Multiple-MSC8113 systems that use data checking, such as parity, face a timing problem when synchronous memories, such as SDRAM, are used. Because these devices can output data every cycle and because the data checking requires additional data set-up time, the timing constraints are extremely hard to meet.
Page 320: 60X-Compatible Mode
(60x-Compatible Mode), on page 12-83. 12.1.12 External Memory Controller Support The MSC8113 device has an option to allocate specific banks (address spaces) to be controlled by an external memory controller or bus slave while retaining all the bank properties: port size, data check, atomic operation, and data pipelining.
Page 321: Sdram Machine
To understand the operation of the Memory Controller SDRAM machine, you must be familiar with SDRAM devices protocol and behavior. The MSC8113 device provides an SDRAM interface (machine) only for the system bus. The machine provides the necessary control functions and signals for JEDEC-compliant SDRAM devices.
Page 322: Supported Sdram Configurations
Memory Controller 12.2.1 Supported SDRAM Configurations The MSC8113 memory controller supports any SDRAM configuration, but all SDRAM devices on the same bus must have the same port size and timing parameters. 12.2.2 SDRAM Power-On Initialization At system reset, initialization software must set up the programmable parameters in the memory controller banks registers (ORx, BRx, PSDMR).
Page 323 0 enables the signal. For either definition, a 1 disables the byte lane and a 0 enables the byte lan The Memory Address (MA[0–11]) signals in this figure are driven by the MSC8113 A[19–28], PSDA10, and A17 signals, respectively.
Page 324: Jedec-Standard Sdram Interface Commands
Burst type must be chosen according to the 60x cache wrap (sequential). Although some SDRAMs provide burst lengths of 1, 2, 4, 8, or a page, the MSC8113 supports only a 4-beat burst for a 64-bit port and an 8-beat burst for a 32-bit port. The MSC8113 does not support burst lengths of 1, 2, and a page for SDRAMs.
Page 325: Bank Interleaving
The most-significant address bits are the bank select for the SDRAM, thus allowing interleaving only on bank boundaries. Bank-based interleaving is activated by clearing PSDMR[PBI]. See Section 12.2.14.2, SDRAM Configuration Example (Bank-Based Interleaving), on page 12-31. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-17...
Page 326: Bnksel Signals In Single-Msc8113 Bus Mode
BNKSEL 12.2.7 SDRAM Address Multiplexing (SDAM and BSMA) In single MSC8113 mode, the lower bits of the address bus connect to the device address port, and the memory controller multiplexes the row/column and the internal banks select lines, according to PSDMR[SDAM] and PSDMR[BSMA]. Table 12-5 shows how PSDMR[SDAM] settings affect address multiplexing.
Page 327 In this case A[16–18] are driven both on and on A[5–7] BNKSEL[0–2] A[16–18] „ The SDRAM device inputs BA. In this case, the lines can be connected either to A[16–18] BNKSEL[2–0] MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-19...
Page 328: Sdram Read/Write Transactions
PSRT. This represents the time period required between refreshes. The value of PSRT depends on the specific SDRAM devices and the operating frequency of the MSC8113 bus. This value should allow for a potential collision between memory accesses and refresh cycles.
Page 329 „ Activate to Read/Write Interval. Controlled by PSDMR[ACTTORW], defines the earliest timing for a command after an command. READ WRITE ACTIVATE PSDRAS PSDCAS Col. MA[0–11] PSDDQM Data ACTTORW = 2 ACTIVATE WRITE Command Command Figure 12-11. ACTTORW = 2 (2 Clock Cycles) MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-21...
Page 330 SDRAM. It is always PRECHARGE related to the CL parameter. Last Data Out ACTIVATE READ DEACTIVATE LDOTOPRE = 2 PSDRAS PSDCAS Column MA[0–11] PSDDQM Data Figure 12-13. LDOTOPRE = 2 (–2 Clock Cycles) MSC8113 Reference Manual, Rev. 0 12-22 Freescale Semiconductor...
Page 331 ACTIVATE REFRESH PSDRAS PSDCAS A8=1 MA[0–11] PSDDQM PRETOACT = 3 RFRC = 4 (6 clocks) Auto refresh Activate command Precharge Bank A if needed Figure 12-15. RFRC = 4 (6 Clock Cycles) MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-23...
Page 332 PSDMR[BUFCMD] should be set so the memory controller adds one cycle for each SDRAM command. PSDAMUX CMD strobes ACTIVATE READ (without CS) Column MA[0–11] Command Set-up Cycle Command Set-up Cycle Figure 12-17. BUFCMD = 1 MSC8113 Reference Manual, Rev. 0 12-24 Freescale Semiconductor...
Page 333: Sdram Signals: General Interface Timing
PSDCAS Column MA[0–11] PSDDQM Data Figure 12-19. SDRAM Single-Beat Read, Page Hit, CL = 3 PSDRAS PSDCAS Column MA[0–11] PSDDQM Data Figure 12-20. SDRAM Two-Beat Burst Read, Page Closed, CL = 3 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-25...
Page 334 Figure 12-21. SDRAM Four-Beat Burst Read, Page Miss, CL = 3 PSDRAS PSDCAS Column MA[0–11] PSDDQM Data Figure 12-22. SDRAM Single-Beat Write, Page Hit PSDRAS PSDCAS Column MA[0–11] PSDDQM Data Figure 12-23. SDRAM Three-Beat Burst Write, Page Closed MSC8113 Reference Manual, Rev. 0 12-26 Freescale Semiconductor...
Page 335 Figure 12-24. SDRAM Read-after-Read Pipeline, Page Hit, CL = 3 PSDRAS PSDCAS Column1 Column2 MA[0–11] PSDDQM Data Figure 12-25. SDRAM Write-after-Write Pipelined, Page Hit PSDRAS PSDCAS Column1 Column2 MA[0–11] PSDDQM Data Figure 12-26. SDRAM Read-after-Write Pipelined, Page Hit MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-27...
Page 336: Sdram Signals: Refresh Timing
The mode data is the address value during a mode-set cycle. It is driven by the memory controller, in single MSC8113 mode, according to PSDMR[CL]. In 60x-compatible mode, software must drive the correct value on the address lines. Figure 12-28 shows the actual value.
Page 337: Sdram Configuration Examples
„ Each device has four internal banks, 12 row address lines, and 10 column address lines For page-based interleaving, the address bus is partitioned as shown in Table 12-7. Table 12-7. 60x Address Bus Partition A[0–5] A[6–17] A[18–19] A[20–29] A[30–31] msb of start address Bank select Column MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-29...
Page 338 PSRT and MPTPR, which should be programmed according to the device refresh requirements. Table 12-10. Register Settings (Page-Based Interleaving) Register Settings Base address EMEMC 11 = 32-bit port size ATOM DECC 010 = SDRAM system bus MSC8113 Reference Manual, Rev. 0 12-30 Freescale Semiconductor...
Page 339: Sdram Configuration Example (Bank-Based Interleaving)
A[17–28] contain a value of 001 and, because the internal bank selects are multiplexed over A[15–16] PSDMR[BSMA] must contain a value of 010 (only the lower two bank select lines are used). MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-31...
Page 340 RFEN LDOTOPRE from device data sheet SDAM from device data sheet BSMA EAMUX SDA10 BUFCMD RFRC from device data sheet from device data sheet PRETOACT from device data sheet MSC8113 Reference Manual, Rev. 0 12-32 Freescale Semiconductor...
Page 341: General-Purpose Chip-Select Machine (Gpcm)
12-9. Additional control is available in 60x-compatible mode (system bus only) via the external address latch enable ( signal. Figure 12-30 shows a simple connection between an SRAM ALE) device with a 32-bit port and the MSC8113. In the example, the SRAM connects to the system bus. MSC8113 32-Bit Wide SRAM 128 KB PWE[0–3]...
Page 342: Gpcm Signals: Timing Configuration
„ Simultaneous with the external address „ One quarter of a clock cycle later „ One half of a clock cycle later MSC8113 Reference Manual, Rev. 0 12-34 Freescale Semiconductor...
Page 343 See the discussion of the Bus Configuration Register (BCR) in Section 4.2, SIU Programming Model. Figure 12-31 shows a basic connection between the MSC8113 and an external peripheral device. Here, (the strobe output for the memory access) directly connects to the...
Page 344: Chip-Select And Write Enable Deassertion Timing
Memory Controller 12.3.1.2 Chip-Select and Write Enable Deassertion Timing Figure 12-33 shows a basic connection between the MSC8113 device and a static memory device. Here, directly connects to the of the memory device. The signals connect to the respective signal in the memory device, where each corresponds to a different data byte.
Page 345: Relaxed Timing
ORx[TRLX] is provided for memory systems that require more relaxed timing between signals. When ORx[TRLX] = 1 and ORx[ACS] ≠ 00, an additional cycle between the address and strobes is inserted by the MSC8113 memory controller. See Figure 12-36 and Figure 12-37. Clock...
Page 346: Output Enable (Poe) Timing
When ORx[TRLX] = 1, the number of wait states inserted by the memory controller is defined by 2 × SCY or a maximum of 30 wait states. MSC8113 Reference Manual, Rev. 0 12-38 Freescale Semiconductor...
Page 347 Figure 12-38. GPCM Relaxed-Timing Write (ACS = 10, SCY = 0, CSNT = 1, TRLX = 1) Clock Address PSDVAL BCTL0 Data Figure 12-39. GPCM Relaxed-Timing Write (ACS = 00, SCY = 0, CSNT = 1, TRLX = 1) MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-39...
Page 348: Extended Hold Time On Read Accesses
12-17. See Figure 12-40 through Figure 12-43 for timing examples. Table 12-17. TRLX and EHTR Combinations ORx[TRLX] ORx[EHTR] Number of Hold Time Clock Cycles Clock Address PSDVAL BCTL0 Data Figure 12-40. GPCM Read Followed by Read (ORx[29–30] = 00, Fastest Timing) MSC8113 Reference Manual, Rev. 0 12-40 Freescale Semiconductor...
Page 349 1-cycle hold time allowed Figure 12-41. GPCM Read Followed by Read (ORx[29–30] = 01) Clock Address PSDVAL BCTL0 Data Hold Time Long hold time allowed Figure 12-42. GPCM Read Followed by Write (ORx[29–30] = 01) MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-41...
Page 350: Gpcm Signals: External Access Termination
Figure 12-43. GPCM Read Followed by Read (ORx[29–30] = 10) 12.3.2 GPCM Signals: External Access Termination The GPCM supports external access termination using , which the MSC8113 synchronizes PGTA and samples internally. If the sampled signal is asserted during a GPCM data phase (second cycle or later), it is converted to , which terminates the current GPCM access.
Page 351 ORx[SCY]. Assertion of before the defined cycle length will also terminate the access. PGTA Clock Address BCTL0 csnt=1 (and scy!=0) Data PGTA PSDVAL SCY clock cycle Figure 12-45. Internal Termination of GPCM Access MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-43...
Page 352: Boot Chip-Select Operation
Boot chip-select operation allows address decoding for a boot ROM before system initialization. signal is the boot chip-select output; its operation differs from the other external chip-select outputs on system reset. When the MSC8113 internal core begins accessing memory at system reset, is asserted for every address in the boot address range, unless an internal register is accessed.
Page 353: User-Programmable Machines (Upms)
12.4 User-Programmable Machines (UPMs) If you are familiar with the MPC8xx UPM, you should first read Section 12.4.7, Differences Between MPC8xx UPM and MSC8113 UPM, on page 12-82. Table 12-19 lists the UPM interface signals on the system bus. Table 12-19. UPM Interface Signals...
Page 354: Requests
12-47 shows the start addresses of these patterns in the UPM RAM, according to cycle type. commands (MxMR[OP] = 11), however, can initiate patterns starting at any of the 64 UPM RAM words. MSC8113 Reference Manual, Rev. 0 12-46 Freescale Semiconductor...
Page 355: Memory Access Requests
8 data acknowledges; an 8-bit device requires 32. See Section 12.1.8, Partial Data Valid Indication (PSDVAL), on page 12-10. The MSC8113 device defines two additional transfer sizes: bursts of 128 bits (16 bytes) and 192 bits (24 bytes). The UPM treats these accesses as back-to-back, single-beat transfers.
Page 356: Upm Refresh Timer Requests
PSDVAL Table 12-21). Otherwise, a bus time-out may occur. 12.4.1.4 Exception Requests When the MSC8113 under UPM control initiates an access to a memory device, the external device may assert . The UPM provides a mechanism by which memory control SRESET signals can meet the timing requirements of the device without losing data.
Page 357: Programming The Upms
The state of the external signals may change (if specified in the RAM array) at any positive edge , or (there is a propagation delay specified in Section 2, Hardware Specifications, of the MSC8113 Data sheet). However, only the signal corresponding to the currently accessed bank is manipulated by the UPM pattern when it runs. The signal assertion and deassertion timing is also specified for each cycle in the RAM word.
Page 358: Ram Array
PGPL2 PGPL3 PGPL4 PGPL5 CS[0–7, 11] PGPL0 PGPL1 Note: For details, see the discussion of the byte-select (BS) signals and the general-purpose (PGPL) signals on page 12 Figure 12-51. RAM Array and Signal Generation MSC8113 Reference Manual, Rev. 0 12-50 Freescale Semiconductor...
Page 359: Ram Words
The final value of the BS lines depends on the The value of the BS lines at the rising values of BRx[PS], TSZ, and A[29–31] for the edge of T2 is one. access. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-51...
Page 360 The value of the PGPL3 line at the rising Defines the state of PGPL3 during phase 3–4. edge of T3 is zero. The value of the PGPL3 line at the rising edge of T3 is one. MSC8113 Reference Manual, Rev. 0 12-52 Freescale Semiconductor...
Page 361 See the discussion of the repeat execution of The current RAM word is executed the current RAM word on page 12-58. twice. The current RAM word is executed three times. The current RAM word is executed four times. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-53...
Page 362 The current RAM word allows a branch at the exception start address (EXS) at a fixed to the exception pattern after the current address in the RAM array. When the MSC8113 cycle if an exception condition is device under UPM control begins accessing a detected.
Page 363 (see TODT bit description) and the next access is to the same bank, the execution of the next UPM pattern is held off for the number of clock cycles specified in MxMR[DSx]. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-55...
Page 364 Similarly, indicates that D[0–7] BS[[1] contains valid data, indicates that contains valid data, and D[8–15] BS[2] D[16–23] BS[3] indicates that contains valid data during a cycle, and so forth. D[24–31] MSC8113 Reference Manual, Rev. 0 12-56 Freescale Semiconductor...
Page 365 A dash (—) denotes a byte-select (BS) is not used. An “A” denotes a byte-select is used. Address state is the calculated address for port size data tenure. The initial value is the address tenure A[29-31]. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-57...
Page 366 — When LOOP and REDO are both set, the loop mechanism works as usual, and the line is repeated according to the REDO function. — LAST and REDO should not both be set. — REDO should not be used within an exception routine. MSC8113 Reference Manual, Rev. 0 12-58 Freescale Semiconductor...
Page 367: Last Word (Last)
The data is sampled by the internal master on the next rising edge as required by the MSC8113 bus. This feature lets you speed up the memory interface by latching data one-half clock early, which can be useful during burst reads.
Page 368: Disable Timer Mechanism (Todt)
(c12 and C) and the WAEN value (‘1’) are frozen until PGPL1 is recognized as deasserted. WAEN is typically set before the line that contains UTA PUPMWAIT = 1. MSC8113 Reference Manual, Rev. 0 12-60 Freescale Semiconductor...
Page 369: Extended Hold Time On Read Accesses
Read Accesses, on page 12-40. CLKOUT c9 c10 c11 c13 c14 PGPL1 PSDVAL WAEN PUPMWAIT Word n Word n+1 Word n+2 Wait Wait Word n+3 Figure 12-55. Wait Mechanism Timing for Internal and External Synchronous Masters MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-61...
Page 370: Dram Configuration Example
ATOM DECC 100 = UPMA 11111111000000000 = 16 MB BCTLD EHTR MAMR BSEL 0 = 60x bus GPL_x4DIS RFEN RL Fx As needed WLFx As needed TLFx As needed As needed G0CLx MSC8113 Reference Manual, Rev. 0 12-62 Freescale Semiconductor...
Page 371: Interface Examples
User-Programmable Machines (UPMs) 12.4.6 Interface Examples Connecting the MSC8113 to a DRAM device requires a detailed examination of the timing diagrams representing the possible memory cycles that must be performed when accessing this device. This section presents timing diagrams for various UPM configurations.
Page 372 The RAM array of the UPM can then be written through use of the MxMR[OP] = 01. Figure 12-47 shows the first locations addressed by the UPM, according to the different services required by the DRAM. MSC8113 Reference Manual, Rev. 0 12-64 Freescale Semiconductor...
Page 373 Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RSS+1 RSS+2 Figure 12-57. Single-Beat Read Access to FPM DRAM MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-65...
Page 374 Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 WSS+1 WSS+2 Figure 12-58. Single-Beat Write Access to FPM DRAM MSC8113 Reference Manual, Rev. 0 12-66 Freescale Semiconductor...
Page 375 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RBS+1 RBS+2 RBS+3 RBS+4 RBS+5 RBS+6 RBS+7 RBS+8 Figure 12-59. Burst Read Access to FPM DRAM (No LOOP) MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-67...
Page 376 Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RBS+1 RBS+2 Figure 12-60. Burst Read Access to FPM DRAM (LOOP) MSC8113 Reference Manual, Rev. 0 12-68 Freescale Semiconductor...
Page 377 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 WBS+1 wBS+2 WBS+3 WBS+4 WBS+5 WBS+6 WBS+7 WBS+8 Figure 12-61. Burst Write Access to FPM DRAM (No LOOP) MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-69...
Page 378 Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 PTS+1 PTS+2 Figure 12-62. Refresh Cycle (CBR) to FPM DRAM MSC8113 Reference Manual, Rev. 0 12-70 Freescale Semiconductor...
Page 379 Bit 22 redo1 Bit 23 loop Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 Figure 12-63. Exception Cycle MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-71...
Page 380 Select between PGPL4 and Wait = Wait, data sampled at clock negative edge MAMR[GPL_x4DIS] Burst inhibit device ORx[BI] The timing diagram in Figure 12-64 shows how the burst-read access in Figure 12-59 can be reduced. MSC8113 Reference Manual, Rev. 0 12-72 Freescale Semiconductor...
Page 381 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RBS+1 RBS+2 RBS+3 RBS+4 Figure 12-64. FPM DRAM Burst Read Access (Data Sampling on Falling Edge of CLKIN) MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-73...
Page 382: Edo Interface Example
RD/WR A[0–9] A[0–9] Figure 12-65. MSC8113/EDO Interface Connection to the System Bus (64-Bit Port Size) Table 12-30 shows the programming of the register field to support the configuration shown in Figure 12-65. The example assumes a frequency of 66 MHz and that the device needs a CLKOUT 1,024-cycle refresh every 10 µs.
Page 383 Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RSS+1 RSS+2 RSS+3 RSS+4 Figure 12-66. Single-Beat Read Access to EDO DRAM MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-75...
Page 384 Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 WSS+1 WSS+2 WSS+3 Figure 12-67. Single-Beat Write Access to EDO DRAM MSC8113 Reference Manual, Rev. 0 12-76 Freescale Semiconductor...
Page 385 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 WSS+1 WSS+2 REDO1 REDO2 REDO3 WSS+3 Figure 12-68. Single-Beat Write to EDO DRAM, REDO Inserts Three Wait States MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-77...
Page 386 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RBS+1 RBS+2 RBS+3 RBS+4 RBS+5 RBS+6 RBS+7 RBS+8 RBS+9 RBS+ Figure 12-69. Burst Read Access to EDO DRAM MSC8113 Reference Manual, Rev. 0 12-78 Freescale Semiconductor...
Page 387 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 WBS+ WBS+ WBS+ WBS+ WBS+ WBS+ WBS+ WBS+ WBS+ Figure 12-70. Burst Write Access to EDO DRAM MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-79...
Page 388 Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 PTS+1 PTS+2 PTS+3 PTS+4 Figure 12-71. Refresh Cycle (CBR) to EDO DRAM MSC8113 Reference Manual, Rev. 0 12-80 Freescale Semiconductor...
Page 389 Bit 23 loop Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 Figure 12-72. Exception Cycle for EDO DRAM MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-81...
Page 390: Differences Between Mpc8Xx Upm And Msc8113 Upm
„ TODT signal. The disable timer control (TODT) and LAST bit in the RAM array word must be set together. Otherwise, TODT is ignored. „ Refresh timer value is in a separate register. In the MSC8113, the refresh timer value has moved to the system bus Assigned UPM Refresh Timer Register (PURT), which can serve multiple UPMs.
Page 391: Hierarchical Bus Interface Example
Assume that one of the SC140 cores initiates a system bus read cycle that addresses the DSI of another MSC8113. The programmer cannot predict when the SC140 core can latch valid data because the internal local bus of another MSC8113 may be occupied (by the DMA controller, for example).
Page 392: Strict 60X-Compatible External Masters
Memory Controller 12.6.1 Strict 60x-Compatible External Masters Any 60x-compatible devices that use a 64-bit data bus can access the MSC8113 internal registers and local bus. These devices can also use memory controller services under the following restrictions, which apply only to system bus-assigned memory banks accessed by the external device: „...
Page 393: Address Incrementing For External Bursting Masters
) and control signals to the memory devices. In low bus frequencies, the additional cycle which is used for external master access address decoding can be eliminated by setting the BCR[EXDD] bit (see Table 4-3). MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-85...
Page 394 Compare Access Figure 12-73. External Master Access (GPCM) The memory controller asserts for each data beat as to indicate data beat termination on PSDVAL write transactions and data valid on read transactions. MSC8113 Reference Manual, Rev. 0 12-86 Freescale Semiconductor...
Page 395 External Master Support (60x-Compatible Mode) Figure 12-74 shows an interconnection in which a 60x-compatible external master and the MSC8113 can share access to a 1MB 64-bit port SDRAM device. Note that the address multiplexer is controlled by , while the address latch is controlled by .
Page 396 2 AACK addr 1 addr 2 PSDAMUX addr 2 - column addr 1 addr 1 - column DATA PSDVAL SDRAS SDCAS Page Miss Page Hit Figure 12-75. 60x-Compatible Mode SDRAM Access MSC8113 Reference Manual, Rev. 0 12-88 Freescale Semiconductor...
Page 397 External Master Support (60x-Compatible Mode) Figure 12-76 shows an interconnection in which a 60x-compatible external master and the MSC8113 can share access to an external 1 MB 64-bit port device using the UPM memory controller machines. Note that while the address latch controlled by...
Page 398 2 BADDR 0x10 0x18 DATA D1_0 D1_1 D1_2 D1_3 PSDVAL PGPL0 BCTL0 BCTL1 Note: PGPL0 is a general-purpose line using as an indicator for burst accesses. Figure 12-77. 60x-Compatible Mode UPM Access MSC8113 Reference Manual, Rev. 0 12-90 Freescale Semiconductor...
Page 399 External Master Support (60x-Compatible Mode) Figure 12-78 shows an interconnection in which a 60x-compatible external master and the MSC8113 can share access to an external 1 MB 64-bit port device using the GPCM memory controller machines. Note that the address latch controlled by latches A[0–31]...
Page 400: Internal Sram And Ipbus Peripherals Support
12.7.1 UPM Programming Example — Internal SRAM The SRAM is accessed via the UPMC on the local bus. The code below is an example of UPM programming. In this example, the notation is based on the following: MSC8113 Reference Manual, Rev. 0 12-92 Freescale Semiconductor...
Page 401 #$90051258,d7 ; move.l d7,MCMR ; move.l #$00000040,d7 ; move.l d7,MDR ; move.w #$0,(r5) ; move.l #$00000045,d7 ; move.l d7,MDR ; move.w #$0,(r5) ; ;; -------------- WRITE BURST ------------------------------------- move.l #$90051260,d7 ; MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-93...
Page 402: Gpcm Programming Example, Ipbus Peripherals
Data can be transferred between internal memories using DMA Flyby mode. In this mode, the DMA controller, and not the memory controller, effects the transfer. For details on DMA flyby mode, refer to Chapter 16, Direct Memory Access (DMA) Controller. MSC8113 Reference Manual, Rev. 0 12-94 Freescale Semiconductor...
Page 403: Memory Controller Programming Model
• the PS field has value of BPS (reset) in BR0 and 00 in BR[1–7]; • the EMEMC field has value of EXMC (reset) in BR0 and 0 in BR[1–7]; • the V field has value 1 in BR0 and 0 in BR[1–7]. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-95...
Page 404 BRx[BA] is used with ORx[AM]. Note: After system reset, BR0[BA] is 0b11111110000000000. — Reserved. Write to zero for future compatibility. 17–18 MSC8113 Reference Manual, Rev. 0 12-96 Freescale Semiconductor...
Page 405 AACK, TA, slave) on the system bus. and PSDVAL. Note: After a system reset, the BR0[EMEMC] is set to the value of the EXMC field from the HRCW. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-97...
Page 406 Read-after-write-atomic (RAWA). RAWA. Writes to the address space handled by the Write-after-read-atomic (WARA). memory controller bank cause the MSC8113 to lock Reserved the bus for the exclusive use of the master. The lock is released when the master performs a read operation from this address space.
Page 407 ROWST depends on PSDMR[PBI]. 0100 A8 0110 A9 1000 A10 1010 A11 1100 A12 1110 A13 Other values are reserved. For PSDMR[PBI] = 1: 0000 A0 0001 A1 1100 A12 1101–1111 Reserved MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-99...
Page 408 SDRAM device connected to the chip-select line. IBID should be set in 60x-compatible mode if the SDRAM device is not connected to the BNKSEL signals. — — Reserved. Write to zero for future compatibility. 28–31 MSC8113 Reference Manual, Rev. 0 12-100 Freescale Semiconductor...
Page 409 CS is output a quarter of a clock after the Note: After a system reset, OR0[ACS] is 11. address lines. The boot sequence writes 00 to CS is output half a clock after the address OR9[ACS]. lines. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-101...
Page 410 Four idle clock cycles are inserted. Note: After a system reset, the OR0[EHTR] is cleared. The boot sequence clears Eight idle clock cycles are inserted. OR9[EHTR]. — — Reserved. Write to zero for future compatibility. MSC8113 Reference Manual, Rev. 0 12-102 Freescale Semiconductor...
Page 411 The bank does not support burst accesses. accesses. The UPMx executes burst Note: The boot sequence clears OR11[BI]. accesses as series of single accesses. — — Reserved. Write to zero for future compatibility. 24–28 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-103...
Page 412 Precharge all banks, used in SDRAM data on the low bits of the address initialization. during the access. Activate bank (for debug purpose). Read/write (for debug purpose). MSC8113 Reference Manual, Rev. 0 12-104 Freescale Semiconductor...
Page 413 PSDA10 during an command, when SDRAM is selected, ACTIVATE to control the memory access. Note: See Section 12.2.14.1, SDRAM Configuration Example (Page-Based Interleaving), on page 12-29 for details. For PSDMR[PBI] = 1: MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-105...
Page 414 Note that PSDMR[EAMUX] can also be set in any case of delays on the address lines, such as address buffers. MSC8113 Reference Manual, Rev. 0 12-106 Freescale Semiconductor...
Page 415 Machine A/B/C Mode Registers BSEL RFEN — G0CLx GPL_x4DIS RLFx Type Reset RLFx WLFx TLFx Type Reset Note: The boot sequence sets the MCMR to 0x80011240 (see Section 12.7.1). MxMR configures the UPMs. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-107...
Page 416 Address Line Line lines. The address output is controlled by the contents of the UPMx RAM array. This field is A[16–31] A[8–23] useful when the MSC8113 connects to DRAM A[16–31] A[7–22] devices requiring row and column addresses A[16–31] A[6–21] multiplexed on the same lines. See Section A[16–31]...
Page 417 0010 The loop executes 2 times. in the UPMx executes for a burst- or single-beat write pattern. 1111 The loop executes 15 times. Note: The boot sequence sets MCMR[WLFx] to 0010. 0000 The loop executes 16 times. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-109...
Page 418 Memory Data 0–31 The data to be read from or written into the RAM array when a command is WRITE READ supplied to the UPM. Memory Address Register Type Reset Type Reset MSC8113 Reference Manual, Rev. 0 12-110 Freescale Semiconductor...
Page 419 ) and a required refresh rate (RefreshRate) of 15.6 µs, given MPTPR[PTP] = 32, the PURT value should be 10 decimal, which is the next lower integer value. PSRT System Bus Assigned SDRAM Refresh Timer PSRT Type Reset MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 12-111...
Page 420 Indicates the source of an error that causes assertion of on the local bus. See the discussion of the Local Bus Transfer Error Status and Control Register 1 (L_TESCR1) in Section 4.2, SIU Programming Model. MSC8113 Reference Manual, Rev. 0 12-112 Freescale Semiconductor...
Page 421: System Bus
13.1 System Bus Signals This section describes the external signals of the MSC8113 system bus. It describes the individual signals, showing behavior when a signal is asserted and deasserted, when the signal is an input and an output, and the differences in how signals work in external-master or internal-only configurations.
Page 422 Figure 13-1 shows the grouping of the MSC8113 system bus signal configuration, as well as pin numbers. Chapter 3, External Signals describes the MSC8113 external signals in greater detail.
Page 423: Address Arbitration
Address Arbitration. Deasserted. Indicates that the MSC8113 device is not requesting the address bus. The MSC8113 may have no bus operation pending. It may be parked, or the ARTRY input may have been asserted on the previous bus clock cycle.
Page 424 Asserted. Indicates that external device is the address bus master. Deasserted. Indicates that the address bus may be available for use by the MSC8113 (see BG). The MSC8113 also tracks the state of ABB on the bus from the TS and AACK inputs. (See section on address arbitration phase.) Timing Comments Assertion.
Page 425: Address Start
32 bits. Timing Comments Assertion/Deassertion. Must be valid (driven by other device) on the same cycle that TS is asserted; sampled by the MSC8113 only on this cycle. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 426: Address Transfer Attribute
TT[0–4] signals and transfer type encoding. See Section n, Transfer type signals (TT[0–4]). The transfer type signals define the nature of the transfer requested Output: (Read or Write). Table 13-10 describes the MSC8113 action as master, slave, and snooper.. State Meaning Asserted/Deasserted. Specifies the type of transfer in progress.
Page 427 The MSC8113 uses four 32-bit burst transactions for transferring cache blocks. For these transactions, TSIZ[0–3] are encoded as 0b0010, TBST is asserted, and address bits A[27–28] determine which 32...
Page 428: Address Transfer Termination
MSC8113 must retry the preceding address tenure and immediately deassert BR (if asserted). If the associated data tenure has started, the MSC8113 also aborts the data tenure immediately, even if the burst data has been received. If the MSC8113 is not the address bus master, this input...
Page 429: Data Arbitration
Deasserted. Indicates that the MSC8113 must hold off its data tenures. Timing Comments Assertion. Occurs any time to indicate that the MSC8113 is free to take data bus mastership. It is not sampled until TS is asserted. Deassertion. Occurs at any time to indicate the MSC8113 cannot assume data bus mastership.
Page 430: Data Transfer
Output The D[0–63] signals have the same meanings in both internal-only mode and external master mode. Note: The MSC8113 device has either a 32-bit or a 64-bit external port for the system bus. Output State Meaning The data bus holds eight byte lanes assigned as shown below.
Page 431 Output The DP[0–7] signals have the same meanings in both internal-only mode and external master mode. Note: The MSC8113 has either a 32-bit or a 64-bit external port for the system bus. Output State Meaning Asserted/Deasserted. Represents odd parity for each of eight bytes of data write transactions.
Page 432: Data Transfer Termination
See Section 13.2.4.5, Port Size Data Bus Transfers and PSDVAL Termination. Deasserted. (During DBB) indicates that, until PSDVAL is asserted, the MSC8113 must continue to drive the data for the current write or must wait to sample the data for reads. Timing Comments Assertion.
Page 433 Section 13.2.4.3, Data Bus Transfers and Normal Termination. Deasserted. (During assertion of DBB) indicates that, until TA is asserted, the MSC8113 must continue to drive the data for the current write or must wait to sample the data for reads.
Page 434: 60X-Compatible Bus Protocols
System Bus 13.2 60x-Compatible Bus Protocols This section describes the general 60x protocol for a 64-bit data bus. In the MSC8113 this protocol is true under the following conditions: „ The system bus has a 32-bit or 64-bit external data bus port. The internal part of the system bus is a 64-bit data bus.
Page 435 60x-Compatible Bus Protocols MSC8113 Latch and A[0–31] DRAM Mux TT[0–4] TSIZ[0–3] TBST AACK ARTRY Memory Control Signals D[0–63] DP[0–7] Figure 13-2. Single-MSC8113 Bus Mode MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 13-15...
Page 436: 60X-Compatible Bus Mode
13.2.1.2 60x-Compatible Bus Mode The 60x-compatible bus mode includes one or more potential external masters (for example, ASIC DMA controllers, high-end PowerQUICC II devices, and/or additional MSC81XXs). Figure 13-3 shows how an external processor attaches to the MSC8113. MSC8113 A[0–31] TT[0–4]...
Page 437: System Bus Protocols
Figure 13-4 shows a single-beat data transfer of up to 256 bits. Notice that the MSC8113 supports port sizes of 8, 16, 32 and 64 bits and requires the additional bus signal,...
Page 438: Arbitration Phase
„ Preference among devices is determined at the request level. The MSC8113 device supports 16 levels of bus requests (see Section 4.2.1). „ When no bus device requests the address bus, the MSC8113 device parks the device selected in the arbiter configuration register on the bus.
Page 439: Address Pipelining And Split-Bus Transactions
These benefits are most fully realized in shared-memory, multiple-master implementations in which bus bandwidth is critical to system performance. External arbitration, as provided by the MSC8113 device, is required in systems with multiple devices sharing the system bus. The MSC8113 uses the signal to control pipelining.
Page 440: Address Arbitration
In addition to the external signals, there are internal request and grant signals for the MSC8113 internal devices. Bus accesses are prioritized, with programmable priority. When an MSC8113 internal master needs the system bus, it asserts the internal bus request along with the request level.
Page 441: Address Pipelining
The MSC8113 pipelines data bus operations in strict order with the associated address operations. Figure 13-6 shows how address pipelining allows address tenures to overlap the associated data tenures.
Page 442: Address Transfer Attribute Signals
TT1 can be interpreted as a read-versus-write indicator for the bus. The MSC8113 can use a reduced mode in which only TT1 is an external signal. This mode is used in configurations with all external masters supporting TT1 only mode. The MSC8113 builds the complete transfer type internally.
Page 443 The basic coherency size of the bus is 32 bytes for the processor. Data transfers that cross an aligned 32-byte boundary must present a new address to the bus at that boundary for proper snoop operation or must operate as non-coherent with respect to the MSC8113. Note: In case of a 60x-compatible bus error or a local bus error, the TC and TT fields are captured in the SIU TESCR1 or L_TESRC1 registers, respectively.
Page 444: Burst Ordering During Data Transfers
13.2.3.5 Effect of Alignment on Data Transfers Table 13-14 lists the aligned transfers that can occur to and from the MSC8113. These are transfers in which the data is aligned to an address that is an integer multiple of the size of the data.
Page 445 A misaligned memory address is not aligned to the size of the data being transferred. For example, it could be 4 bytes read from an odd byte address. The MSC8113 processor bus interface supports misaligned transfers within a 4-byte (32-bit aligned) boundary, as shown in Table 13-15.
Page 446: Effect Of Port Size On Data Transfers
The MSC8113 system bus has either a 32-bit or a 64-bit external data bus port. The internal part of the system bus is a 64-bit data bus. The MSC8113 local bus has a 64-bit internal data bus. The bus requires that the portion of the data bus allocated for a transfer to or from a particular port size be fixed.
Page 447 — — — — — — OP5 OP5 — — — — — — — — — — — — — — — — — — — — — — OP7 OP7 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 13-27...
Page 448 OPx: These lanes are read or written during that bus transaction. OP0 is the MSB of a 2-byte operand and OP7 is the LSB. — Denotes a byte not required during that read cycle. MSC8113 Reference Manual, Rev. 0 13-28 Freescale Semiconductor...
Page 449 60x-Compatible Bus Protocols Table 13-17 lists data transfer patterns for write cycles for accesses initiated by the MSC8113 device. Table 13-17. Data Bus Contents for Write Cycles Address Transfer Data Bus Pattern Size State TSIZ[0–3] A[29–31] 0–7 8–15 16–23 24–31 32–39...
Page 450: 60X-Compatible System Bus Mode-Size Calculation
In single-MSC8113 bus mode, these address and size calculations are internal and do not constrain the system. In 60x-compatible bus mode, the external slave or master must determine the new address and size.
Page 451: Extended Transfer Mode
OP1 OP2 OP3 — OP1 OP1 Table 13-20 lists the patterns of the extended data transfer for write cycles when the MSC8113 initiates an access. The 16-byte and 24-byte transfers are always 8-byte aligned and use a maximum 64-bit port size.
Page 452 Byte 2 Bytes Byte 3 Bytes 2 Bytes 2 Bytes Byte 2 Bytes 4 Bytes Stop 6 Bytes Byte 5 Bytes Byte 2 Bytes 2 Bytes Byte 2 Bytes 4 Bytes Stop MSC8113 Reference Manual, Rev. 0 13-32 Freescale Semiconductor...
Page 453: Address Transfer Termination
ARTRY tenure, the MSC8113 ignores the first data beat. If it is a read operation, the MSC8113 does not forward data internally to the MSC8113 internal storage. This retry mechanism allows the memory system to begin operating in parallel with the bus snoopers, provided external devices do not present data sooner than the bus cycle before all snoop responses can be determined and asserted on the bus.
Page 454: Address Tenure Timing Configuration
To maintain the one-level pipeline, is not asserted for a AACK pipelined address tenure until the current data tenure ends. The MSC8113 device also delays asserting until no more address retry conditions can occur. The earliest the MSC8113 can...
Page 455: Pipeline Control
AACK ARTRY Figure 13-8. Retry Cycle 13.2.3.12 Pipeline Control The MSC8113 device supports the following two modes: „ One-level pipeline mode. To maintain the one-level pipeline, is not asserted for a AACK pipelined address tenure until the current data tenure ends. In 60x-compatible bus mode, a two-level pipeline depth can occur (for example, when an external 60x-bus slave does not support one-level pipelining).
Page 456: Data Tenure Operations
System Bus 13.2.4 Data Tenure Operations This section describes the operation of the MSC8113 device during the data bus arbitration, transfer, and termination phases of the data tenure. 13.2.4.1 Data Bus Arbitration The beginning of an address transfer, marked by the assertion of transfer start (...
Page 457: Data Bus Transfers And Normal Termination
60x-Compatible Bus Protocols cannot be enabled when the MSC8113 is in 60x-compatible bus mode and a device that uses is connected to the bus. This restriction is necessary because MSC8113 in data streaming mode may leave asserted after the last of a transaction, thus violating the strict bus protocol.
Page 458: Effect Of Artry Assertion On Data Transfer And Arbitration
13.2.4.5 Port Size Data Bus Transfers and PSDVAL Termination The MSC8113 device transfers data via data ports of 8, 16, 32 and 64 bits, as shown in Section 13.2.3.3, Address Transfer Attribute Signals, on page 13-22. Single-beat transaction sizes can be 8, 16, 32, 64, 128, and 192 bits;...
Page 459 8-byte sets are transferred in eight beats. CLKOUT ADDR + ATTR AACK PSDVAL D[0–31] Figure 13-10. 128-Bit Extended Transfer to 32-Bit Port Size CLKOUT ADDR + ATTR AACK PSDVAL D[0–31] Figure 13-11. Burst Transfer to 32-Bit Port Size MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 13-39...
Page 460: Data Bus Termination By Assertion Of Tea Signal
System Bus 13.2.4.6 Data Bus Termination by Assertion of TEA Signal If a device initiates an unsupported transaction, the MSC8113 device signals an error by asserting . This occurs because the assertion of is sampled by the device only during the data tenure of the bus transaction.
Page 461: Direct Slave Interface (Dsi)
Direct Slave Interface (DSI) The direct slave interface (DSI) gives an external host direct access to the MSC8113 device and external memory. It provides the following slave interfaces to an external host: „ Asynchronous interface giving the host single accesses (with no external clock).
Page 462 It can therefore read data that is not up-to-date. To reduce latency for accesses to the MSC8113 internal or external address space, writes by the DSI are done via the write buffer. Write accesses to the DSI registers bypass the write buffer;...
Page 463: Data Bus
The specific signal used depends on the configured access mode (that is, Asynchronous Dual Strobe mode write, Asynchronous Single Strobe mode read or write, Synchronous Dual Strobe mode write, or Synchronous Single Strobe mode read or write, respectively). For details, see Section 14.3.1 and Section 14.3.2. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 14-3...
Page 464: Dcr[Bem] Bit Access Considerations
14.1.2 DCR[BEM] Bit Access Considerations For 32-bit mode, you must consider the following cases: „ DCR[BEM] bit is set. When the MSC8113 memory space (Bank 11), external memory, or a register space (Bank 9 or the system registers) is accessed, address bit is decoded.
Page 465 When one of the MSC8113 register spaces is accessed (Bank 9 or the system registers), address bit is decoded. HA29 — A write access to the MSC8113 registers writes the 32 msbs or 32 lsbs, indicated by value. HA29 • If...
Page 466: Address Bus
Direct Slave Interface (DSI) 14.2 Address Bus One of two DSI main addressing modes is determined during the MSC8113 boot sequence. Both modes allow two address space access Internal and External. The DCR[SLDWA] bit (see page 14-29) defines the addressing mode: „...
Page 467 A[15–28] = Host Address bits HA[15–28] Access to External Memory address space. A[29–31] = See page 14-4 and page 14-5. Access to Internal address space. Figure 14-2. Sliding Window Mode Address Construction MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 14-7...
Page 468: Full Address Addressing Mode
Access to Internal address space. External 32 address A[0–31]: A[0–15] = DEXTBAR[EXTBAVAL] A[16–28] = Host Address bits HA[16–28] A[29–31] = See Section 14.1.2. Access to External Memory address space. Figure 14-3. Full Address Mode Address Construction MSC8113 Reference Manual, Rev. 0 14-8 Freescale Semiconductor...
Page 469 Table 14-3. DCR[ADREN] Description of Decoding External Window A[0–7] A[8] A[9] A[10] A[11–28] A[29–31] [ADREN] Size 0b0001 2 MB HA[11–28] See Section 14.1.2. 0b0010 4 MB 0b0011 8 MB HA[10] HA[9] 0b0100 16 MB HA[8] MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 14-9...
Page 470: Host Chip Id Signals (Hcid[0-3])
DCIR[CHIPID] value. This decoding enables the HCID[0–3] host to use one chip select signal to access each of up to sixteen MSC8113 devices. You can write a new value to the DCIR after the reset sequence ends.
Page 471: Host Access Modes And Timings
HRDS/HRDE HWBS[0–3/7]/HWBE[0–3/7] HDBS[0–3/7]/HDBE[0–3/7] Single Strobe Mode Dual Strobe Mode Figure 14-5. DSI Access Modes, Write Access HRDS/HRDE HDBS[0–3/7]/HDBE[0–3/7] HWBS[0–3/7]/HWBE[0–3/7] Single Strobe Mode Dual Strobe Mode: Figure 14-6. DSI Accessing Modes, Read Access MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 14-11...
Page 472: Synchronous Versus Asynchronous Access Mode
Bits shown as x can be 1 or 0. Addresses 29–31 have a value of 0 because bursts should be 64-bit aligned. However, in munged Little-Endian mode, in 32-bit mode, HA29 must be equal to 1, but is interpreted internally as 0. MSC8113 Reference Manual, Rev. 0 14-12...
Page 473: Dsi Access Modes
„ Drive high. DCR[HTAAD] = 1 and DCR[HTADT] ≠ 00. The DCR[HTADT] value indicates the amount of time to drive . This mode requires a pull-up resistor on MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 14-13...
Page 474 DSI stops driving the signal before it accesses the next device. When the DCR[HTAAD] bit is set and the next access is to the same MSC8113 device, the host must not start a consecutive access before the signal is actively driven high by the previous access.
Page 475: Asynchronous Write Using Single Strobe Mode
DSI stops driving the signal before it accesses the next device. When the DCR[HTAAD] bit is set and the next access is to the same MSC8113 device, the host must not start a consecutive access before the signal is actively driven high by the previous access.
Page 476: Asynchronous Read Using Dual Strobe Mode
DSI stops driving the signal before it accesses the next device. When the DCR[HTAAD] bit is set and the next access is to the same MSC8113, the host must not start consecutive access before the previous access deasserts don’t care valid value don’t care...
Page 477: Asynchronous Read Using Single Strobe Mode
DSI stops driving the signal before it accesses the next device. When the DCR[HTAAD] bit is set and the next access is to the same MSC8113, the host must not start consecutive access before the previous access deasserts don’t care...
Page 478: Synchronous Mode Operation
HCLKIN next rising edge of . The host can start its next access to the same MSC8113 immediately HCLKIN in the next rising edge without deasserting between accesses.
Page 479: Synchronous Single Write Using Single Strobe Mode
HCLKIN If the next access is not to the same MSC8113, then, to prevent contention on , the host must wait to access the next device until the previous DSI stops driving . There is no error condition to prevent this contention.
Page 480: Synchronous Single Read Using Dual Strobe Mode
1 in the next cycle. It stops being driven on the HCLKIN next rising edge of . The host can start its next access to the same MSC8113 device HCLKIN immediately in the next rising edge without deasserting between accesses.
Page 481: Synchronous Single Read Using Single Strobe Mode
MSC8113 immediately in the next rising edge without deasserting HCLKIN between accesses. If the next access is not to the same MSC8113, then, to prevent contention on , the host must wait to access the next device until the previous DSI stops driving HCLKIN valid value don’t care...
Page 482: Synchronous Burst Write Using Dual Strobe Mode
After the last beat of the access, is driven to logic 1 and stops being driven on the next rising edge of . The host can start its next access to the same MSC8113 immediately HCLKIN in the next rising edge without deasserting between accesses.
Page 483: Synchronous Burst Write Using Single Strobe Mode
After the last beat of the access, is driven to logic 1 and stops being driven on the next rising edge of . The host can start its next access to the same MSC8113 immediately HCLKIN in the next rising edge without deasserting between accesses.
Page 484: Synchronous Burst Read Using Dual Strobe Mode
MSC8113 device immediately in the next rising edge without deasserting HCLKIN between accesses. If the next access is not to the same MSC8113, to prevent contention on the host must wait to access the next device until the previous DSI stops driving the signal.
Page 485: Synchronous Burst Read Using Single Strobe Mode
MSC8113 device immediately in the next rising edge without deasserting HCLKIN between accesses. If the next access is not to the same MSC8113, to prevent contention on the host must wait to access the next device until the previous DSI stops driving the signal.
Page 486: Broadcast Accesses
HWBS[0–7] HDBS[0–7] minimum length of time, as defined in the MSC8113 Technical Data sheet in Section 2.7, AC Timings. „ In Synchronous mode single access, the host must wait one cycle before terminating the access.
Page 487: Dsi Configuration
Dual Strobe mode immediately after reset. Note: The next access to the DSI must not be performed before the MSC8113 device is out of reset (see Chapter 5, Reset). The following DSI operating modes are configured during reset: „...
Page 488: Stop Mode
14.4.2 DSI Reset During Host Access If the MSC8113 completes a reset sequence during a host access to the DSI, then the DSI operation is undefined. It is therefore advisable that the host abort this access or at least use the MSC8113 to be aware that such a reset occurred.
Page 489: Dsi Programming Model
DCR, the host must allow five internal clock cycles between the end of the write access and any other DSI access. During that time the signals must be HWBS[0–3/7 HDBS[0–3/7] HWBE[0–3/7] HDBE[0–3/7] HRDS HRDE deasserted (held high). MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 14-29...
Page 490 11 HTA is driven for 1.5–2.5 internal bus three drive time options are provided. HTADT is clock cycles. valid only for asynchronous accesses. See Section 14.3.3. — Reserved. Write to zero for future compatibility. MSC8113 Reference Manual, Rev. 0 14-30 Freescale Semiconductor...
Page 491 Used at Sliding Window Mode, the value written in address space. EXTACC represent internal/external access. See Figure Access is to the external address 14-2, Sliding Window Mode Address Construction, on space. page 14-7 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 14-31...
Page 492 DSI configuration registers or perform a read access to the DSI to empty the write FIFO. If a host on the DSI updates these registers, all registers must be written one after the other, without any access to a different memory region in between. MSC8113 Reference Manual, Rev. 0 14-32 Freescale Semiconductor...
Page 493 DSI to empty the write FIFO. If a host on the DSI updates these registers, all the registers must be written one after the other, with no access to a different memory region in between. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 494 (during which time, signal must be deasserted. DSI Disable Register DSISTP DSIDIS — R/W from IPBus. Read-only from host side Type Reset — Type R/W from IPBus. Read-only from host side Reset MSC8113 Reference Manual, Rev. 0 14-34 Freescale Semiconductor...
Page 495: Status Registers
Chapter 5, Reset. PPCLE Munged Little-Endian mode True Little Endian host. Stores the value of the PPCLE bit in the HRCW. For PowerPC Little Endian host. details, see Chapter 5, Reset. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 14-35...
Page 496 Indicates whether an overflow has occurred. Writing 1 to this Overflow occurred. bit clears it. See Section 14.3.5, Broadcast Accesses, on page 14-26. — Reserved. Write to zero for future compatibility. 1–31 MSC8113 Reference Manual, Rev. 0 14-36 Freescale Semiconductor...
Page 497: Hardware Semaphores
Hardware Semaphores The MSC8113 hardware semaphores (HS) hold eight coded hardware semaphores. A coded hardware semaphore provides a simple way to achieve a “lock” operation via a single write access, eliminating the need for such sophisticated read-modify-write mechanisms as the reservation.
Page 498 A non-zero value ≠ 0 Semaphore is locked with lock code indicates the current lock code. indicated by its current value. It is writable only to zero. MSC8113 Reference Manual, Rev. 0 15-2 Freescale Semiconductor...
Page 499: Direct Memory Access (Dma) Controller
Direct Memory Access (DMA) Controller The MSC8113 multi-channel DMA system supports up to sixteen time-multiplexed channels and buffer alignment by hardware. The DMA controller connects to both the system bus and local bus and functions as a bridge between both buses. Transactions run simultaneously on both buses.
Page 500 System Bus Interrupt System External Memory System Channels Interface Parameter FIFO Request Arbiter Channel Group Local Interface Local Bus 8 M1 4 M1 Flyby Memories Counters Memory Figure 16-1. DMA System Diagram MSC8113 Reference Manual, Rev. 0 16-2 Freescale Semiconductor...
Page 501: Dma Signals: Requestor Interface
The peripheral can deassert its current request and assert a new request if needed. When a peripheral is using the DRACK signal option, it should not assert DONE MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 16-3...
Page 502: Peripheral Access Timing
Figure 16-2 illustrates the timing for a peripheral with a level-triggered request and expiration timer, without the use of the protocol. DRACK MSC8113 Reference Manual, Rev. 0 16-4 Freescale Semiconductor...
Page 503 EXP_TIMER DACK ADDR DATA PSDVAL Expiration timer starts counting when peripheral receives DACK. DMA samples level DREQ as a new request when expiration time ends. Figure 16-2. Level-Triggered Request and Expiration Timer MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 16-5...
Page 504 The DMA controller synchronizes the DREQ input. To achieve the shortest latency between the DREQ assertion and the request sampling, the DREQ should be asserted at the beginning of the clock. Figure 16-4. Level-Triggered Request, Asynchronous , DRACK Signals DREQ MSC8113 Reference Manual, Rev. 0 16-6 Freescale Semiconductor...
Page 505 DONE signal not later than one cycle after the DACK signal is deasserted. DONE should be asserted for at least one clock. Figure 16-6. Sequential Assertion of DACK and DONE Signals MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 16-7...
Page 506: Dma Operating Modes: Transfer Types
Direct Memory Access (DMA) Controller 16.2 DMA Operating Modes: Transfer Types The MSC8113 DMA controller supports all combinations of data transfers between external memory, internal memories, and external peripherals. Typical transfers are as follows: „ External memory to or from an external peripheral in normal mode „...
Page 507 Signals: Requestor Interface. Note: DMA channels are coupled in pairs (0 and 1, 2 and 3, up to 14 and 15). Do not use two coupled channels simultanously for flyby or single access transactions. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 16-9...
Page 508: Application Examples
Controller Local Bus Local Bus Local Bus (24-Bit Address/ 64-Bit Data) (32-Bit Address/64-Bit Data) Internal Read Channel Memory Write Channel Figure 16-7. External Memory to an External Peripheral on the System Bus MSC8113 Reference Manual, Rev. 0 16-10 Freescale Semiconductor...
Page 509: External Peripheral To Internal Memory
Peripheral Bridge Controller Control Memory Controller Local Bus Local Bus Local Bus (24-Bit Address/ 64-Bit Data) (32-Bit Address/64-Bit Data) Internal Memory Read Channel Write Channel Figure 16-8. External Peripheral to Internal Memory MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 16-11...
Page 510: External Peripheral To External Peripheral
Bridge Controller Control Memory Controller Local Bus (24-Bit Address/ Local Bus Local Bus 64-Bit Data) (32-Bit Address/64-Bit Data) Internal Memory Read Channel Write Channel Figure 16-9. External Peripheral to an External Peripheral MSC8113 Reference Manual, Rev. 0 16-12 Freescale Semiconductor...
Page 511: External Memory And External Memory On The System Bus
Memory Bridge Controller Control Memory Controller Local Bus Local Bus Local Bus (24-Bit Address/ 64-Bit Data) (32-Bit Address/64-Bit Data) Internal Memory Read Channel Write Channel Figure 16-10. External Memory to External Memory MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 16-13...
Page 512: External Memory To Internal Memory On The System Bus
Peripheral Bridge Controller Control Memory Controller Local Bus Local Bus Local Bus (24-Bit Address/ (32-Bit Address/64-Bit Data) 64-Bit Data) Internal Memory Read Channel Write Channel Figure 16-11. External Memory to Internal Memory MSC8113 Reference Manual, Rev. 0 16-14 Freescale Semiconductor...
Page 513: Internal Memory To Internal Memory
Peripheral Bridge Controller Control Memory Controller Local Bus (24-Bit Address/ Local Bus Local Bus 64-Bit Data) (32-Bit Address/64-Bit Data) Internal Memory Read Channel Write Channel Figure 16-12. Internal Memory to Internal Memory MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 16-15...
Page 514: Flyby Transfer From External Peripheral To External Memory
Controller Bridge Control Memory Controller Local Bus Local Bus Local Bus (24-Bit Address/ 64-Bit Data) (32-Bit Address/64-Bit Data) Internal Memory Read/Write Channel Figure 16-13. Flyby Transfer From External Peripheral to External Memory MSC8113 Reference Manual, Rev. 0 16-16 Freescale Semiconductor...
Page 515: Flyby Transfers Between Internal Memories, M2 And M1
Controller Bridge Control Memory Controller Local Bus Local Bus (24-Bit Address/ (32-Bit Address/64-Bit Data) 64-Bit Data) Flyby Memory Memory Counter Read/Write Channel Figure 16-14. Flyby Transfer Between Internal Memories, M2 and M1 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 16-17...
Page 516: Transfers Between Internal Memories M1 And M1 (Flyby Mode)
Buffer Descriptor Attributes Transfer Size field (BD_ATTR[TSZ]) and decrements the Buffer Descriptor Size (DCPRAM[BD_SIZE]), accordingly. The address can be incremented or frozen. When the BD_SIZE reaches zero, the channel does one of the following: MSC8113 Reference Manual, Rev. 0 16-18 Freescale Semiconductor...
Page 517 BD_SIZE[bdptr] == BD_BSIZE[bdptr];/* initial BD_size */ /* Not continuous buffer */ if (CONT[bdptr] == 1){ /* Chained buffer, size and address are determined according to new channel */ if (NBD[bdptr] != bdptr) bdptr=NBD; else Close_buffer, gen_interrupt; MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 16-19...
Page 518 Make sure that the ISR clears the DSTR as soon as possible. You can read the DCHCR after the interrupt is processed to determine whether another buffer was completed or if the DMA channel is still active. MSC8113 Reference Manual, Rev. 0 16-20 Freescale Semiconductor...
Page 519: Simple Buffer
Non-continuous mode: the channel is closed when the size reaches zero Increment address after request is serviced NO_INC Maximum transfer size is one burst Read buffer BD_BSIZE Buffer base size of cyclic buffer — MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 16-21...
Page 520: Cyclic Buffer
Increment address after request is serviced When the size reaches zero, the next request calls buffer 4 Maximum transfer size is one burst Read buffer BD_BSIZE Buffer base size of cyclic buffer 0x200 MSC8113 Reference Manual, Rev. 0 16-22 Freescale Semiconductor...
Page 521: Incremental Buffer
Continuous mode. Do not shut down the channel when size reaches zero NO_INC Increment address after request is serviced Next request calls Buffer 0 when size reaches zero Read buffer BD_BSIZE — Buffer base size of cyclic buffer MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 16-23...
Page 522: Chained Buffer
Do not generate interrupt when the buffer ends. The channel generates the interrupt. CONT Non-continuous mode. The channel is closed when the size reaches zero NO_INC Increment address after request is serviced MSC8113 Reference Manual, Rev. 0 16-24 Freescale Semiconductor...
Page 523: Complex Buffers-Dual Cyclic Buffers
BD 1. Buffer 0 starts at address 0x1000 and transfers 0x200-byte blocks. Buffer 1 starts at address 0x2000 and also transfers 0x200-byte blocks. BD 0 BD 1 0x1000 0x2000 0x11F8 0x21F8 Interrupt Interrupt Figure 16-20. Dual Cyclic Buffers MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 16-25...
Page 524: Data Transfers
In Figure 16-21, BD 1-BD 4 are chained buffers belonging to the read channel while BD 0 is a simple buffer belonging to the write channel, generating an interrupt at the end of the transfer. MSC8113 Reference Manual, Rev. 0 16-26 Freescale Semiconductor...
Page 525 Non-continuous mode: the channel is closed when the size reaches zero NO_INC Do not increment address after request is serviced Maximum transfer size is two bytes Write buffer BD_BSIZE — Buffer base size of cyclic buffer MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 16-27...
Page 526 NO_INC Increment address after request is serviced When size reaches zero, next request calls Buffer 1 Maximum transfer size is two bytes Read buffer BD_BSIZE Buffer base size of cyclic buffer MSC8113 Reference Manual, Rev. 0 16-28 Freescale Semiconductor...
Page 527: Dma Transfer Programming
? Configure DPCR, SIUMCR, GPIO Registers Configure DCPRAM for each buffer Set DCHCR[ACTV] bit of empty channel (odd DCHCRx) Set DCHCR[ACTV] bit of fill channel (even DCHCRx) Figure 16-22. DMA Configuration Flow MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 16-29...
Page 528: Dma Priority Type
The pointer hand indicates the current active channel (the markers on the clock) used by the local bus and the system bus. When the transfer is complete for a selected channel, the clock hand moves on to the next channel. MSC8113 Reference Manual, Rev. 0 16-30 Freescale Semiconductor...
Page 529 „ If a channel requests service, but the hand already passed it in the current round, it is served during the next round. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 16-31...
Page 530: Dma Arbitration Device Level Considerations
DMA_1 activity to wait due to the pending low priority access by DMA_2. and the ongoing TDM access. Solution: Assign the TDM a lower priority than DMA_2 to prevent the situation in the scenario from occurring. MSC8113 Reference Manual, Rev. 0 16-32 Freescale Semiconductor...
Page 531: Dma Data Transfer Examples
Termination of the destination (write) channel proceeds as follows: The DMA controller ignores any further requests from the peripheral. Tasks in progress — bus data phase, bus address phase, and pending phase — are flushed. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 16-33...
Page 532: Dma Programming Model
The channels involved in the transfer must be configured for the given task via the DMA registers. This section describes the DMA registers in detail. „ DMA Channel Configuration Registers (DCHCR[0–15]), page 16-35 „ DMA Pin Configuration Register (DPCR), page 16-38 MSC8113 Reference Manual, Rev. 0 16-34 Freescale Semiconductor...
Page 533: Configuration Registers
The DMA controller can also modify the BDPTR and ACTV fields. To avoid a conflict with the DMA logic and to avoid overwriting the DMA modifications, use byte access to these fields while the channel is active. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 16-35...
Page 534 When the DMA channel handles an internal request, the FLY bit must be cleared. — — Reserved. Write to zero for future compatibility. MSC8113 Reference Manual, Rev. 0 16-36 Freescale Semiconductor...
Page 535 The lowest channel has the highest priority. Note: When working with Round-Robin priority (DPCR[AM] = 1), these bits must be cleared for all channels. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 16-37...
Page 536 If the DMA access and an external access occur at the same time, the DMA hardware waits one clock until the external transaction terminates. Figure 16-26 depicts the structure of the DCPRAM. MSC8113 Reference Manual, Rev. 0 16-38 Freescale Semiconductor...
Page 537 A 32-bit parameter that describes the attributes of the channel handling this buffer. See Table 16-10. 96–127 BD_BSIZE Buffer base size Holds the base size of the buffer. if used, program BD_SIZE with a value greater than 0. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 16-39...
Page 538 4-13 and the PPC_ALRL System Bus 10 Arbitrate for bus mastership with DMA high Arbitration-Level Register (PPC_ALRL) on priority request (bus requestor 10). page 4-15. 11 Reserved. — Undefined Reserved. Write to zero for future compatibility. 7–8 MSC8113 Reference Manual, Rev. 0 16-40 Freescale Semiconductor...
Page 539 TC[0–2] value is 110. Indicates the TC code to be associated with the TC[0–2] value is 111. transaction generated by the DMA controller. Refer to Table 13-11Transfer Code Encoding, on page 13>-22. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 16-41...
Page 540: Dma Status And Interrupt Registers
If set, a bit associated with a channel indicates that interrupt service is required. A bit is cleared by writing a one to it. Writing zero does not affect a bit value. It is possible to clear several bits at a time. DSTR is cleared at reset. MSC8113 Reference Manual, Rev. 0 16-42 Freescale Semiconductor...
Page 541: Bus Error Registers
The DCHCR[ACTV] bit is deasserted by the hardware for all channels configured to service the other bus, guaranteeing memory coherency. The registers associated with bus errors are described in the sections that follow. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 16-43...
Page 542 (DCHCRx) in Section 16.4, DMA Programming Model, on page 16-34. — Reserved. Write to zero for future compatibility. 5–7 Note: Reserved. Write to zero for future compatibility. MSC8113 Reference Manual, Rev. 0 16-44 Freescale Semiconductor...
Page 543 PDMTEA holds the system address accessed during a DMA transfer error on the system bus. The LDMTEA holds the system address accessed during a DMA transfer error on the local bus. Both registers are undefined at reset. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 16-45...
Page 544 Direct Memory Access (DMA) Controller MSC8113 Reference Manual, Rev. 0 16-46 Freescale Semiconductor...
Page 545: Interrupt Processing
Interrupt Processing The MSC8113 interrupt system is optimized for a multi-processing environment and performs the following functions: „ Maximizes the localization of interrupt handling by each SC140 core using two interrupt controllers: PIC and LIC. „ Enables global distribution for important interrupt sources to all the SC140 cores.
Page 546 INT_OUT INT_OUT NMI_OUT outputs of the MSC8113 that enable several output signals to connect to the same input signal in the target device. can also be configured to have a full drive for fast deassertion time on INT_OUT a point-to-point connection, by setting the SIUMCR[INTODC] control bit.
Page 547 Group A Group B 3 IRQ, 3 NMI Local Interrupt Controller (LIC) EOnCE IRQ NMIR SC140 Programmable VAB[0–5] Interrupt Controller Core RIPL[0–2] (PIC) VAB_EN Extended Core 0 Figure 17-1. MSC8113 Interrupt Block Diagram MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 17-3...
Page 548: Architecture
Interrupt Processing 17.1 Architecture This section focuses on the three interrupt controllers in the MSC8113 interrupt structure: „ Global interrupt controller (GIC) „ Local interrupt controller (LIC) „ Programmable interrupt controller (PIC) 17.1.1 Global Interrupt Controller The GIC performs the following functions: „...
Page 549 Virtual Status Register TCMNT (VISR) Ethernet UART [1-15] Ctlr 0, 8, 16, 24 GCIER Enable/Disable GICR GISR Level/Edge Status INT_OUT IRQ[8–15], Ethernet GEIER Enable/Disable all except Ethernet Figure 17-2. GIC Block Diagram MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 17-5...
Page 550: Int_Out Generation
Reserved — Reserved Reserved — UART UART Interrupt TMCNT Time Counter Periodic Interrupt Timer DMA global interrupt IRQ15 IRQ15 Signal IRQ14 IRQ14 Signal IRQ13 Signal IRQ13 IRQ12 IRQ12 Signal IRQ11 IRQ11 Signal MSC8113 Reference Manual, Rev. 0 17-6 Freescale Semiconductor...
Page 551: Nmi Or Nmi_Out Generation
The SC140 core that services the interrupt may clear this status bit by writing a value of one to it, or it may ignore this bit and work locally on its LIC. The LIC MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 552: Virtual Nmi Generation
„ Deassert GIC stop request by clearing SCR[GIC_STC] in the IPBus master. „ Clear all pending interrupts in the GISR by writing 0xFFFFFFFF to the register. „ Re-enable interrupt sources in GEIER or GCIER as required. MSC8113 Reference Manual, Rev. 0 17-8 Freescale Semiconductor...
Page 553: Local Interrupt Controller (Lic)
LIC. The LIC has the following functions: „ 64 interrupt input lines divided into two groups of 32 interrupts. In the MSC8113 device, these groups are separated into Group A interrupts and Group B interrupts. „ All interrupt sources are synchronized, and their polarity is hardwired to the actual source polarity.
Page 554 DMA Status and Interrupt Registers). — Typically, the interrupt mapping is divided among the interrupt sources as DMA, TDM Tx, TDM Rx, and TDM Error, but any other combination is valid, depending on the application. MSC8113 Reference Manual, Rev. 0 17-10 Freescale Semiconductor...
Page 555: Resolving Lic Interrupts By The Sc140 Cores
LIC interrupt source is mapped to this PIC input. At the end of this set up, each PIC-mappable input from the LIC has an associated updated 32-bit mask value. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 17-11...
Page 556: Level Interrupt Mode
Level mode interrupts should be used in case an interrupt at the LIC input represents a sum of interrupt sources at the peripheral, since this configuration does not enable proper edge detection. MSC8113 Reference Manual, Rev. 0 17-12 Freescale Semiconductor...
Page 557: Edge Interrupt Mode
TDM0 Receive Error (sum of TDM receive error detections). TDM0RSTE TDM0 Receive Second Threshold Event. TDM0 Receive First Threshold Event. TDM0RFTE TDM0TXER TDM0 Transmit Error (sum of TDM transmit error detections). TDM0TSTE TDM0 Transmit Second Threshold Event. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 17-13...
Page 558 DMA channel 6 interrupt DMA channel 7 interrupt DMA7 TIMER0A Timer Block A Timer 0 Compare Flag TIMER1A Timer Block A Timer 1 Compare Flag TIMER2A Timer Block A Timer 2 Compare Flag MSC8113 Reference Manual, Rev. 0 17-14 Freescale Semiconductor...
Page 559 Timer Block A Timer 12 Compare Flag Timer Block A Timer 13 Compare Flag TIMER13A TIMER14A Timer Block A Timer 14 Compare Flag TIMER15A Timer Block A Timer 15 Compare Flag UART UART Tx & Rx Interrupt (global) MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 17-15...
Page 560 Timer Counter (global) IRQ1 signal (global) IRQ1 VIRQ16 Virtual Interrupt Number 16 VIRQ17 Virtual Interrupt Number 17 Virtual Interrupt Number 18 VIRQ18 Virtual Interrupt Number 19 VIRQ19 VIRQ20 Virtual Interrupt Number 20 MSC8113 Reference Manual, Rev. 0 17-16 Freescale Semiconductor...
Page 561: Programmable Interrupt Controller (Pic)
The MSC8113 PIC is a peripheral module that serves the signals received from MSC8113 peripherals and I/O lines. The PIC is memory-mapped to the SC140 and is accessed via the SC140 QBus. The PIC includes 32 inputs for signals and...
Page 562: Peripheral Bus (Qbus) Interface
„ An IPL[2–0] signal indicating the priority of the „ An entry in the predefined VAB, determined by the location of the 17.1.5 Interrupt Routing The MSC8113 PIC serves a total of 24 and eight . Each can be configured as edge-triggered or level-triggered and can be assigned a priority in the range 0 through 7, where priority 0 masks the interrupt.
Page 563 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 VBA[31–12] VAB[5–0] Figure 17-5. Interrupt Service Routine Address Construction Table 17-8 summarizes the routing of MSC8113 interrupts. Unless stated otherwise, all signals are level-triggered. For details on signals, refer to the relevant chapters The PIC handles interrupts IRQ[0–23]...
Page 564 Interrupt Processing Table 17-8. MSC8113 Interrupt Routing (Continued) Service Routine VAB[0–5] Signal Description Address (Offset from VBA) Ethernet Ring 2 receive frame event 0x22 IRQ2 0x880 0x23 IRQ3 Ethernet Ring 3 receive frame event 0x8C0 0x24 IRQ4 Ethernet Transmit frame event...
Page 565: Interrupt Programming Examples
„ Setting the interrupt base address in the VBA Register „ Initializing the stack pointer „ Masking interrupts in the MSC8113 status register „ Masking, unmasking and programming PIC IR properties in the ELIRx registers „ Configuring the LIC Configuration register EMx and IMAPx in the LICICR „...
Page 566: Lic And Pic Programming
; configure the LIC-B IMAP20=’01’ route the interrupt line to IRQOUTB1 move.l #$00090000,LICBICR1 ; Enable LIC-B, interrupt number 20 (VRIQ0) move.l #$00100000,LICBIER org p:IRQ16 ; interrupt service routine for GIC org p:IRQ18 ; interrupt service routine for LIC MSC8113 Reference Manual, Rev. 0 17-22 Freescale Semiconductor...
Page 567: Clearing Pending Requests
Section 8.7, System Bus Address Space, on page 8-55. The addresses of the GIC registers for accesses through the DSI is presented in Section 8.8, DSI Address Map, on page 8-61. The GIC MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 568 For proper virtual interrupt operation, the LIC must be programmed to edge mode for the virtual interrupt pulse sources. Table 17-9. VIGR Bit Descriptions Name Reset Description Settings — — Reserved. Write to zero for future compatibility. 0–21 MSC8113 Reference Manual, Rev. 0 17-24 Freescale Semiconductor...
Page 569 Write access to VNMIGR with appropriate value to the CORENUM field generates an NMI pulse to the selected core. The generated NMI pulse sets the NMI0 status bit in the selected SC140 PIC IPRB register. See Table 17-8. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 17-25...
Page 570 Level Mode. Edge mode. Reserved. Write to zero for future compatibility. — 9–11 UART UART Interrupt Level Mode. Edge mode. TMCNT TMCNT Interrupt Level Mode. Edge mode. PIT Interrupt Level Mode. Edge mode. MSC8113 Reference Manual, Rev. 0 17-26 Freescale Semiconductor...
Page 571 Enable interrupt and route the interrupt line to output INT_OUT. IRQ[15–1] Interrupt Request 15–1 Disable interrupt. 16–30 Enable interrupt and route the interrupt line to output INT_OUT. — Reserved. Write to zero for future compatibility. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 17-27...
Page 572 Reserved. Write to zero for future compatibility. 9–15 IRQ[15–8] Interrupt Request 15–8 Disable interrupt. 16–23 Enable interrupt and route the interrupt line to the PIC IRQ16. — Reserved. Write to zero for future compatibility. 24–31 MSC8113 Reference Manual, Rev. 0 17-28 Freescale Semiconductor...
Page 573: Lic Programming Model
„ LIC Group B Interrupt Error Status Register (LICBIESR), page 17-39. Each LIC resides only in its associated core memory space, and all LIC blocks are seen by their associated SC140 on the same addresses. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 17-29...
Page 574: Lic Interrupt Configuration Registers
01 Route an enabled interrupt line through IRQOUTA1 into the PIC. 10–11, 31–24. 10 Route an enabled interrupt line through IRQOUTA2 into the PIC. 14–15, 18–19, 11 Route an enabled interrupt line through IRQOUTA3 into the PIC. 22–23, 26–27, 30–31 MSC8113 Reference Manual, Rev. 0 17-30 Freescale Semiconductor...
Page 575 01 Route an enabled interrupt line through IRQOUTA1 into the PIC. 10–11, 23–16. 10 Route an enabled interrupt line through IRQOUTA2 into the PIC. 14–15, 18–19, 11 Route an enabled interrupt line through IRQOUTA3 into the PIC. 22–23, 26–27, 30–31 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 17-31...
Page 576 11 Route an enabled interrupt line through IRQOUTA3 into the PIC. 22–23, 26–27, 30–31 LICAICR3 LIC Group A Interrupt Configuration Register 3 IMAP7 IMAP6 IMAP5 IMAP4 Type Reset Boot IMAP3 IMAP2 IMAP1 IMAP0 Type Reset Boot MSC8113 Reference Manual, Rev. 0 17-32 Freescale Semiconductor...
Page 577 LICBISR is set, the interrupt is captured by the corresponding bit in the LICBIESR and the LICSEIRQ global interrupt line is asserted towards the PIC. 11 Reserved. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 17-33...
Page 578 01 Route an enabled interrupt line through IRQOUTB1 into the PIC. 10–11, 14–15, 23–16. 10 Route an enabled interrupt line through IRQOUTB2 into the PIC. 18–19, 22–23, 26–27, 30–31 11 Route an enabled interrupt line through IRQOUTB3 into the PIC. MSC8113 Reference Manual, Rev. 0 17-34 Freescale Semiconductor...
Page 579 01 Route an enabled interrupt line through IRQOUTB1 into the PIC. 10–11, 15–8. 10 Route an enabled interrupt line through IRQOUTB2 into the PIC. 14–15, 18–19, 11 Route an enabled interrupt line through IRQOUTB3 into the PIC. 22–23, 26–27, 30–31 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 17-35...
Page 580 01 Route an enabled interrupt line through IRQOUTB1 into the PIC. 10–11, 10 Route an enabled interrupt line through IRQOUTB2 into the PIC. 14–15, 18–19, 11 Route an enabled interrupt line through IRQOUTB3 into the PIC. 22–23, 26–27, 30–31 MSC8113 Reference Manual, Rev. 0 17-36 Freescale Semiconductor...
Page 581: Lic Interrupt Enable Registers
(read only) or edge routed by the IMAP field to the appropriate mode. The second edge status bit is constantly PIC interrupt input. cleared, to eliminate a second edge error interrupt. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 17-37...
Page 582: Lic Interrupt Status Registers
PIC input. Note: If a status bit in LICAIESR or LICBIESR is set, it blocks the reassertion of the corresponding status bit in LICAISR or LICBISR in second-edge mode. MSC8113 Reference Manual, Rev. 0 17-38 Freescale Semiconductor...
Page 583 PIC input. IRQ23 Note: If a status bit in LICAIESR or LICBIESR is set, it blocks the reassertion of the corresponding status bit in LICAISR or LICBISR in second-edge mode. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 17-39...
Page 584: Pic Registers
IPL. A value of zero in these three bits indicates that interrupts are disabled on this input. Table 17-24. Interrupt Priority Level Bits PILxx0 PILxx1 PILxx2 Enabled Value — MSC8113 Reference Manual, Rev. 0 17-40 Freescale Semiconductor...
Page 585 The mode for the 24 programmable inputs can be defined as either edge-triggered or level-triggered. Note: Unless specified otherwise in Table 17-8, MSC8113 Interrupt Routing, on page 17-19, all maskable PIC interrupt sources should be programmed as level-triggered. Table 17-25 shows the settings for the interrupt trigger mode bit.
Page 586 The MSC8113 boot procedure configures ELIRF to the appropriate trigger mode and sets the corresponding signals. The value of ELIRF after boot is 0x0008, which sets (EOnCE IRQ20 interrupt) to edge-triggered mode. For a summary of the routing of MSC8113 interrupts, refer to Table 17-8. MSC8113 Reference Manual, Rev. 0 17-42 Freescale Semiconductor...
Page 587: Interrupt Pending Registers
PIC Interrupt Pending Register B 16–23 24–31 NMIs IPRA PIC Interrupt Pending Register A IP15 IP14 IP13 IP12 IP11 IP10 Type Reset IPRA reflects the status for IR inputs 0 through 15. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 17-43...
Page 588 IP22–16 Status of IR input 22–16 9–15 The description and settings are the same as IP23 for inputs 22–16. MSC8113 Reference Manual, Rev. 0 17-44 Freescale Semiconductor...
Page 589 VBA Register. At reset the value of the 20-bit wide VBA Register is set to zero. The offset for each exception vector is predefined. There are 64 possible exception vector locations. The spacing between two exception vectors is 32 words (four full execution sets). MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 17-45...
Page 590 Interrupt Processing MSC8113 Reference Manual, Rev. 0 17-46 Freescale Semiconductor...
Page 591 This chapter covers aspects of JTAG that are specific to the MSC8113. It includes the items that the standard requires to be defined, with additional information specific to the MSC8113 device. For details on the standard, refer to the IEEE Std.
Page 592: Overview
„ Give entry to Debug mode. „ Query identification information (manufacturer, part number and version) from an MSC8113-based device. „ Force test data onto the outputs of an MSC8113-based device while replacing its BSR in the serial data path with a single-bit register. Note: Precautions must be taken to ensure that the IEEE Std.
Page 593 SHIFT SHIFT changes on the falling edge of TCK. TRST An asynchronous reset (with an internal pull-up resistor) that provides initialization of the TAP controller and other logic required by the standard. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 18-3...
Page 594: Tap Controller
TAP controller states, refer to the IEEE Std. 1149.1 documentation. Test Logic Reset Run-Test/Idle Select-DR_SCAN Select-IR_SCAN Capture-DR Capture-IR Shift-DR Shift-IR Exit1-DR Exit1-IR Pause-DR Pause-IR Exit2-DR Exit2-IR Update-DR Update-IR Figure 18-2. TAP Controller State Machine MSC8113 Reference Manual, Rev. 0 18-4 Freescale Semiconductor...
Page 595: Instruction Decoding
EOnCE modules, you must shift 4 bits to the choose cells. For details, see Section 18.4. The MSC8113 includes a 5-bit instruction register without parity, consisting of a shift register with five parallel outputs. Data is transferred from the shift register to the parallel outputs during controller state.
Page 596 EXTEST Selects the Boundary Scan Register (BSR). EXTEST also asserts internal reset for the MSC8113 system logic to force a predictable internal state while external boundary scan operations are performed. By using the TAP, the register can: • Scan user-defined values into the output buffers •...
Page 597 MSC8113. When the DEBUG_REQUEST instruction is decoded, TDI and TDO connect to the EOnCE registers. In addition, ENABLE_EONCE is active and forced to request Debug mode from the MSC8113, in order to perform system debug functions. Before the DEBUG_REQUEST instruction is selected, the CHOOSE_EONCE instruction should be executed to define which EOnCE is to be selected for DEBUG_REQUEST.
Page 598: Multi-Core Jtag And Eonce Module Concept
Figure 18-4. JTAG TAP Controller and EOnCE Module Multi-Core Interconnection Each of the three MSC8113 EOnCE modules has an interface to a JTAG port. The interface is active even when a reset signal to the SC140 core is asserted. However, system reset must be deasserted to allow a proper interface with the cores.
Page 599: Enabling The Eonce Module
JTAG clock. Each EOnCE module includes an EOnCE controller, an event counter (used by the MSC8113 ICache to count hits/misses in cache; see Section 9.4.1), an event detector unit, a synchronizer, an event selector, and a trace unit.
Page 600: Debug_Request And Enable_Eonce Commands
The number of bits in this stream, that is, the number of clocks in this state, is equal to the number of selected SC140 cores in the cascade, which is three. This state is indicated by the signal. For example, for the three SC140 cores on the MSC8113, to activate CHOOSE_CLOCK_DR...
Page 601: Signalling A Debug Request
Write/read data into the chosen register via shift-dr or update-dr. The chosen register is written/read. Figure 18-6. Reading and Writing EOnCE Registers Via the JTAG TAP 18.5 Signalling a Debug Request signals connect to each of the MSC8113 EOnCE modules. is an input that signals EE[0–1] a debug request;...
Page 602: Ee_Ctrl Modifications For The Msc8113
Debugging 18.5.1 EE_CTRL Modifications for the MSC8113 The relevant paragraph from the EOnCE module chapter of SC140 DSP Core Reference Manual is reproduced here with the appropriate amendments. EE_CTRL EE Control Register — EE1DEF EE0DEF Type Reset Boot The modes for are restricted as follows: EE[0–1]...
Page 603: Event Selector Register Programming
18.5.2 Event Selector Register Programming There are four event selector registers. The Event Selector Mask Debug Mode (ESEL_DM) register in the EOnCE programs the event selectors for the debug events. The MSC8113 only supports the signals. Also, there is a requirement to block triggering from if only some SC140 cores must enter Debug mode.
Page 604: Real-Time Debug Request
SC140 cores enters Debug mode. Note: input initiates Debug mode, and the output is the debug acknowledge indication. MSC8113 SC140 core Figure 18-7. Selected SC140 Core Issues a Debug Request to All Other SC140 Cores MSC8113 Reference Manual, Rev. 0 18-14 Freescale Semiconductor...
Page 605: Exiting Debug Mode
To ensure interrupt acceptance, you should implement a double-acknowledge software protocol that communicates between the software agent that asserts the interrupt request and the debug exception handler that runs on the SC140 core. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 18-15...
Page 606: Generating A Debug Exception From An Edca Pc Detection Event
„ Immediately following a conditional change-of-flow instruction (such as JF or IFT JMP). 18.6 Tracing in the MSC8113 The trace buffer in each EOnCE module in the MSC8113 is 8 KB. Use of a trace buffer in the MSC8113 requires specific procedures, depending on how you access the trace buffer.
Page 607: General Jtag Mode Restrictions
To save power when JTAG is not in use, the MSC8113 should be in the following state: „ To enter or to remain in the Low-Power Stop mode, the TAP controller must be in the test-logic-reset state.
Page 608: Jtag And Eonce Module Programming Model
BSR. The boundary scan bit definitions vary according to the specific chip implementation of the MSC8113 and are described by the BSDL file on the product website. Figure 18-8 through Figure 18-11 show various BSR cell types.
Page 609 From Last Cell Update DR Figure 18-8. Output Signal Cell (O.PIN) To Next Cell Data to Input System Logic Clock DR Shift DR From Last Cell Figure 18-9. Observe-Only Input Signal Cell (I.OBS) MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 18-19...
Page 610 The BSDL file on the product website describes the boundary scan serial string. The three MSC8113 cell types described in this file are depicted in Figure 18-8 through Figure 18-10, which describe the cell structure for each type.
Page 611: Shift Registers
It can then be shifted out CAPTURE in the controller state. See Figure 18-13. SHIFT Shift-DR Parallel Input Serial Output Serial Input Clock-DR Figure 18-13. Identification Register Configuration (ID) MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 18-21...
Page 612: General-Purpose Register
10–31 18.8.3.4 Parallel Input Register PIREG JTAG Parallel Input Register JTAG port access onl — core2 core2 core1 core1 core0 core0 cores[1–0] upd_ack cores[1–0] upd_ack cores[1–0] upd_ack Type Reset — Type Reset MSC8113 Reference Manual, Rev. 0 18-22 Freescale Semiconductor...
Page 613 Indicates whether the SC140 core 0 EOnCE instruction dispatched to it. module has executed the last instruction EOnCE module has not executed the dispatched to it. last instruction dispatched to it. — Reserved. 15–0 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 18-23...
Page 614 Debugging MSC8113 Reference Manual, Rev. 0 18-24 Freescale Semiconductor...
Page 615: Internal Peripheral Bus (Ipbus)
„ In shared data link mode, the receive and transmit modules share sync, clock, and full duplex data links between the transmit and receive modules. The clock and the sync signals can also be shared between the TDM modules. Note: For details, see Chapter 20, TDM Interface. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 19-1...
Page 616: Uart
19.4 GPIOs The MSC8113 has 32 general-purpose I/O (GPIO) signals. Each signal line in the I/O port is configured either as a GPIO signal or as a dedicated peripheral interface signal. In addition, fifteen of the signal lines can generate interrupts to the global interrupt controller. Each signal is configured as an input or output (with a register for data output that is read or written at any time).
Page 617: Direct Slave Interface (Dsi)
19.7 Direct Slave Interface (DSI) The Direct Slave Interface (DSI) gives an external host direct access to the MSC8113 device. It provides the following slave interfaces to an external host: „ Asynchronous interface giving the host single accesses (with no external clock).
Page 618: Ipbus Functionality
Stop mode according to the Stop Control Register bits.These modules must not be accessed while they are in Stop mode. There is no Stop for the HS and GPIO modules. The Stop option applies to the different slave modules as follows: MSC8113 Reference Manual, Rev. 0 19-4 Freescale Semiconductor...
Page 619: Ipbus Programming Model
Timer B TDM3 Ethernet UART Figure 19-2. Stop Mode for Different IPBus Modules 19.11 IPBus Programming Model Refer to Section 8.5, IPBus Address Space, on page 8-12 for the IPBus base address. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 19-5...
Page 620 DSI is requested to enter Stop mode. UART_STC UART Stop UART is not requested to enter Determines whether the UART module is requested to Stop mode. enter Stop mode. UART is requested to enter Stop mode. MSC8113 Reference Manual, Rev. 0 19-6 Freescale Semiconductor...
Page 621 Determines whether the DSI module is in Stop mode. DSI is in Stop mode. UART_STA UART Stop Ack UART is not in Stop mode. Determines whether the UART module is in Stop mode. UART is in Stop mode. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 19-7...
Page 622 Internal Peripheral Bus (IPBus) MSC8113 Reference Manual, Rev. 0 19-8 Freescale Semiconductor...
Page 623: Tdm Interface
TDM Interface The MSC8113 Time-Division Multiplexing (TDM) interface enables communication among many devices over a single bus. Traffic is managed according to a time-division multiplexing method in which only one device drives the bus (transmit) for each channel. Each device drives its active transmit channels and samples its active receive channels when its channel is active.
Page 624 The four TDM modules have an I/O matrix that routes the clock and sync signals between the TDM modules and the MSC8113 signal lines. The TDM is configured by all three SC140 cores through the interface to the IPBus (see Figure 20-1). Data is received and transmitted from the TDM modules to the channel buffers through the local bus.
Page 625 Rx error int3, Rx threshold1 int3, Rx threshold2 int3 Tx error int1, Tx threshold1 int1, Tx threshold2 int1 Tx error int3, Tx threshold1 int3, Tx threshold2 int3 Figure 20-1. General TDM Module Interface MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 20-3...
Page 626 A/m Law Data Configuration Registers Conversion IP logic TDM DMA To Local Bus Interface To IPBus Multiplex Notes: X is the TDM number. Receive data flow: Transmit data flow: Figure 20-2. TDM Block Diagram MSC8113 Reference Manual, Rev. 0 20-4 Freescale Semiconductor...
Page 627: Typical Configurations
Typical Configurations 20.1 Typical Configurations The TDM connects in various configurations. Figure 20-3 shows two MSC8113 devices that connect point-to-point. Data transmits from the device on the left to the device on the right or vice versa. On-Board Clock Generator...
Page 628: Tdm Basics
Figure 20-5 depicts an application in which all the TDM modules share the sync and the clock (see Figure 20-11). Therefore, each TDM module supports one or two active links. In this example, 16 receive link and 16 transmit links connect to two MSC8113 devices. FSYN...
Page 629 RNCF[7–0] = 8 × 23 (24 channels), RCS = 4 × 7 (8 bits) and RT1 = 1 (T1 mode). Receive Frame parameters: TNCF[7–0] = 8 × 23 (24 channels), TCS = 4 × 7 (8 bits) and TT1 = 1 (T1 mode) Transmit Frame parameters: Figure 20-7. T1 Frame MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 20-7...
Page 630: Common Signals For The Tdm Modules
TDM1 TDM2 TDM3 RTSAL[3–0] = 0001 RTSAL[3–0] = 0001 RTSAL[3–0] = 0000 RTSAL[3–0] = 0000 CTS = 1 CTS = 1 CTS = 0 CTS = 0 Figure 20-8. TDM Modules Model MSC8113 Reference Manual, Rev. 0 20-8 Freescale Semiconductor...
Page 631 RTSAL[3–0] = 1111 RTSAL[3–0] = 1111 RTSAL[3–0] = 1111 RTSAL[3–0] = 1111 CTS = 1 CTS = 1 CTS = 1 CTS = 1 Figure 20-10. Shared Frame Sync, Clock, and Data Links MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 20-9...
Page 632: Receiver And Transmitter Independent Or Shared Operation
FSYNC (frame sync) specifies that the receiver and transmitter share the same sync. FCLK (frame clock) specifies that the receiver and transmitter share the same clock. Figure 20-11. TDM Module Sharing Modes MSC8113 Reference Manual, Rev. 0 20-10 Freescale Semiconductor...
Page 633 Channel 3 Channel 6 Channel 7 Channel 10 Channel 11 x The TDM number. N The number of channels in a TDM frame. Figure 20-13. Shared Sync and Clock (Two Active Data Links) MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 20-11...
Page 634 Table 20-2 describes the maximum bit rate as a function of these parameters. Factors other than the width of the channel can affect the bit rate, for example, capacity on the data links. MSC8113 Reference Manual, Rev. 0 20-12 Freescale Semiconductor...
Page 635: Tdm Data Structures
Up to 32 transmit bytes of channel 2 are located in four buffers (TNB = 3). Only 8 receive bytes of channel 2 are located in one buffer (RNB = 0). Each buffer contains 8 bytes per channel. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 20-13...
Page 636 0x1000 (offset from TDMx Receive Local Memory) is 0x44556677, and the data to be read from address 0x1004 (offset from TDMx Receive Local Memory) is 0x00112233. 8 Bytes 0x1000 Figure 20-17. TDMx Local Memory Read Example MSC8113 Reference Manual, Rev. 0 20-14 Freescale Semiconductor...
Page 637: Serial Interface
One-Bit Length:SOL = 0 TDMx(R/T)CLK TDMxTSYN (sync_out) TDMxTDAT N – 1 Channel 0 Channel 1 Word Length: SOL = 1 TDMx(R/T)CLK TDMxTSYN(sync_out) TDMxTDAT Channel 0 Channel 1 Four Bits Figure 20-18. Sync Length Selection MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 20-15...
Page 638: Sync In Configuration
Therefore, the transmit delay when the transmit sync and transmit data are sampled/driven out at the same clock edge is (TFSD – 1). And when the sync and the data sampled/driven out at different clock edge is (TFSD – 1 + 0.5). MSC8113 Reference Manual, Rev. 0 20-16 Freescale Semiconductor...
Page 639 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 Channel number Channel 0 Channel 1 Channel 2 Start of the frame data drive 0 bit delay sync sample Figure 20-19. Frame Sync Configurations MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 20-17...
Page 640: Serial Interface Synchronization
TDM frame is identified by a frame sync signal that is asserted at the beginning of every frame. The frame sync synchronization is necessary when more than one device drives the bus. Figure 20-22 shows the state diagram of the frame sync synchronization. MSC8113 Reference Manual, Rev. 0 20-18 Freescale Semiconductor...
Page 641 Sync event found not at the expected position Sync event found at Last bit of the frame the expected position PRESYNC Figure 20-22. Frame Sync Synchronization State Diagram MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 20-19...
Page 642: Reverse Data Order
The TDMxRIR[RRDO] bit defines how the receive channel data is stored in memory. If TDMxRIR[RRDO] is clear, the first bit of the received channel data is stored as the most significant bit. The TDMxTIR[TRDO] bit selects the transmit data bits order. If MSC8113 Reference Manual, Rev. 0 20-20 Freescale Semiconductor...
Page 643: Tdm Local Memory
A single data transfer from the local bus to TDM local memory transfers at least 64 bits of data. Each channel can store more than 64 bits MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 644: Buffers Mapped On The Local Bus
μ-law channel, the received 14 bits are converted into an 8-bit PCM sample. This channel also occupies 16 bits (14 bits padded with two zeros at the right) per 8 transmit bits, essentially MSC8113 Reference Manual, Rev. 0 20-22 Freescale Semiconductor...
Page 645: Data Buffer Address
„ Transmit Channel Data Base Address. TDMxTCPRn[TCDBA] field, page 20-59. TGBA << 16 + TCDBA points to the first byte of transmit data buffer n. The four lsbs of TCDBA must be 0000. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 20-23...
Page 646 The TDBD can be used to show which data is already read from the buffer so that the buffer can be filled with new data. Note: For A/μ-law channels the RDBD and the TDBD fields should be doubled before use. MSC8113 Reference Manual, Rev. 0 20-24 Freescale Semiconductor...
Page 647 (A/μ law active) RGBA TGBA RGBA TGBA RCDBA 0000 RCPRx TCDBA 0000 TCPRx Receive data buffer i base address Transmit data buffer i base address Figure 20-25. Data Buffer Location in Main Memory MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 20-25...
Page 648: Threshold Pointers And Interrupts
The SC140 core can now fill all the transmit buffers from their beginnings to the byte to which the second threshold (TDBST) points. Meanwhile, the TDM keeps reading new data from the buffer. MSC8113 Reference Manual, Rev. 0 20-26 Freescale Semiconductor...
Page 649 If (TDMxRDBFT[RDBFT] == (TDMxRDBS[RDBS] - 0xF)) then TDMxRDBFT[RDBFT] = 0x0 else if (TDMxRDBFT[RDBFT] == (TDMxRDBS[RDBS] - 0x7)) then TDMxRDBFT[RDBFT] = 0x8 else TDMxRDBFT[RDBFT] = TDMxRDBFT[RDBFT] + 0x10 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 20-27...
Page 650: Unified Buffer Mode
Transmit Data Buffer Channel 1 is a transparent channel TDBS RCPR1[RCONV] = 00. Channel k is an A/μ law channel RCPRk[RCONV] = 10. Figure 20-27. Transmit Data Buffer in Independent Data Buffer Mode (TUBM=0) MSC8113 Reference Manual, Rev. 0 20-28 Freescale Semiconductor...
Page 651: Adaptation Machine
Each TDM module has an adaptation machine that counts the number of bits between frame SYNCs. This module can be used to determine the frame size in bits. MSC8113 boot code uses this module during boot from TDM to determine whether the TDM boot master is a T1 (193 bits) or an E1 (256 bits) interface.
Page 652 Read the value of the ASD field in the TDMxASDR. (See the TDMxASDR TDMx Adaptation Sync Distance Register on page 20-62). Clear the AMS bit by writing a 1 to the AMS bit in the TDMxASR. MSC8113 Reference Manual, Rev. 0 20-30 Freescale Semiconductor...
Page 653: Tdm Power Saving
20.3 TDM Power Saving The MSC8113 TDMs use the stop mode of different clocks to save power. Each TDM has three clock domains: transmit serial, receive serial, and the system clock. The transmit serial clock is not supplied to the TDM module when the transmitter is disabled, that is, the TDMxTCR[TEN] bit and the TDMxTSR[TENS] are both clear.
Page 654: Loopback Support
— Set the Transmit Sync Out (TSO) bit to according to the Transmit Sync signal direction (input or output) used in your system. — Set the Receive Frame Sync Delay field to 0x00 and the Transmit Frame Sync Delay field to 0x01. MSC8113 Reference Manual, Rev. 0 20-32 Freescale Semiconductor...
Page 655: Tdm Initialization
Program all the configuration registers (their default value is zero). Program all the control registers, except the TDMx Receive Control Register (TDMxRCR) and the TDMx Transmit Control Register (TDMxTCR). Fill the sync data in all the TDM receive local memory. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 20-33...
Page 656: Tdm Programming Model
„ TDMx Receive Interface Register (TDMxRIR), page 20-43. „ TDMx Transmit Interface Register (TDMxTIR), page 20-45. „ TDMx Receive Frame Parameters (TDMxRFP), page 20-47. „ TDMx Transmit Frame Parameters (TDMxTFP), page 20-49. MSC8113 Reference Manual, Rev. 0 20-34 Freescale Semiconductor...
Page 657 „ Local Bus GTD Transfer Error Address (LGTDTEA), page 20-69. „ GTD Transfer Error Requestor Number Register (LGTDTER), page 20-70. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 20-35...
Page 658: Configuration Registers
TDM signals as a function of the RTSAL field. Note: If the TDM modules share sync and clock signals, then the RFP, TFP,RIR, and TIR registers should be configured the same way for all the TDM modules. MSC8113 Reference Manual, Rev. 0 20-36 Freescale Semiconductor...
Page 659 The x specifies the TDM number of TDMs that share signals. For example if TDM0, TDM1, and TDM2 share signals, then x is equal to 0,1, and 2 and the receive data links are TDM0RDAT, TDM1RDAT, and TDM2RDAT. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 20-37...
Page 660 TDMx specifies the TDM number and any one of the shared TDM modules. TDMy specifies the TDM number and any one of the shared TDM modules except TDM0. For example, if TDM0 and TDM1 share signals, the unused signals are TDM1TCLK and TDM1TSYN. MSC8113 Reference Manual, Rev. 0 20-38 Freescale Semiconductor...
Page 661 (TDATA_B) (TDATA_A) other TDM modules. Receive and transmit share sync and clock signals. Two active data links. direction Input Input Output Output Inout Input 0110 Reserved 0111 Reserved MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 20-39...
Page 662 DATA_A sync/ clock/ sync and clock with not used not used other TDM modules. Independent mode. One active data link. direction Input Output Inout Input MSC8113 Reference Manual, Rev. 0 20-40 Freescale Semiconductor...
Page 663 (TDATA_B) (TDATA_A) frame clock with other TDM modules. Receive and transmit share the sync and clock signals. Two active data links. direction Input Input Output Output Inout Input 0110 Reserved 0111 Reserved MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 20-41...
Page 664 Frame sync specifies that the receiver and transmitter use the same sync. Frame clock specifies that the receiver and transmitter use the same clock. If data link specifies that the direction is inout, the signal is used for receive and transmit. MSC8113 Reference Manual, Rev. 0 20-42 Freescale Semiconductor...
Page 665 The receive data signal is sampled on clock. For details see Section 20.2.4.2. the falling edge of the receive clock. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 20-43...
Page 666 Data Edge Receive Clocks Note: Receive clocks is the number of receive clocks between the sample of the receive frame sync and the sample of first data bit of the received frame. MSC8113 Reference Manual, Rev. 0 20-44 Freescale Semiconductor...
Page 667 The transmit frame sync signal is driven out clock. For details, see Section 20.2.4.1. on the falling edge of the transmit clock. 22–25 Reserved. Write to zero for future compatibility. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 20-45...
Page 668 Transmit clocks is the number of transmit clocks between the first transmit frame sync sample and the first data bit of the frame that is driven out. The field value is negative because the data is driven out before the transmit frame sync sample. MSC8113 Reference Manual, Rev. 0 20-46 Freescale Semiconductor...
Page 669 The even values are channels. reserved. Table 20-15 describes the RNCF valid value as a function of the RTSAL field (Receive and Transmit Sharing and Active Links). For details, see Section 20.2.4. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 20-47...
Page 670 0 and 1 are located in the TDMxRCPR0 (See page 20-58). For details, see Section 20.2.6.4. Note: When this bit is set, the TDMxRIR[RRDO] bit should be cleared. MSC8113 Reference Manual, Rev. 0 20-48 Freescale Semiconductor...
Page 671 Table 20-17 describes the TNCF valid value as a function of the TDMxGIR[RTSAL] field (Receive and Transmit Sharing and Active Links). For details, see Section 20.2.4. — Reserved. Write to zero for future compatibility. 16–20 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 20-49...
Page 672 1 are located in Transmit Channel Parameter 0 (refer to page 20-59). For details, see Section 20.2.6.4. Note: When this bit is set, the TDMxTIR[TRDO] bit should be cleared. MSC8113 Reference Manual, Rev. 0 20-50 Freescale Semiconductor...
Page 673 29–31 must be set to “111”. For details, see Section 20.2.6.1, Data Buffer Size and A/m-law Channels, on page 20-22. Note: The minimum buffer size is 16 bytes. TDMxTDBS TDMx Transmit Data Buffer Size — TDBS Type Reset TDBS Type Reset MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 20-51...
Page 674 Determines the global base address of the receiver data buffers. It is added to the channel data buffer address and to the current receive displacement to generate the actual data address. TDMxTGBA TDMx Transmit Global Base Address — Type Reset TGBA Type Reset MSC8113 Reference Manual, Rev. 0 20-52 Freescale Semiconductor...
Page 675: Control Registers
Adaptation machine learns the transmit sync. Adaptation Machine Enable Adaptation machine is disabled. Determines whether the adaptation machine is Adaptation machine is enabled enabled or disabled. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 20-53...
Page 676 TDMxTCR controls the activation/deactivation of the TDMx Transmitter. Transmitter activation is valid only when the TENS bit is clear. Table 20-24. TDMxTCR Bit Descriptions Name Reset Description Settings — Reserved. Write to zero for future compatibility. 0–30 MSC8113 Reference Manual, Rev. 0 20-54 Freescale Semiconductor...
Page 677 0x000000 to (RDBS – 7) 8–31 Determines the location of the first threshold in the receive data buffers. The register value has a granularity of 8 bytes; that is, the three LSBits are always clear. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 20-55...
Page 678 TDM Interface TDMxTDBFT TDMx Transmit Data Buffers First Threshold — TDBFT Type Reset TDBFT Type Reset MSC8113 Reference Manual, Rev. 0 20-56 Freescale Semiconductor...
Page 679 0x000000 to (RDBS – 7) 8–31 Determines the location of the second threshold in the receive data buffers. The register value has a granularity of eight bytes; that is, the three LSBits are always clear. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 20-57...
Page 680 TDMxRCPRn[RACT] is cleared. The read/write access to TDMxRCPRn registers can done only to 32 bits, write or read of byte or word is not valid. The register reset value is unknown. MSC8113 Reference Manual, Rev. 0 20-58 Freescale Semiconductor...
Page 681 Note: All TDMxTCPRn with an index number (n) less than or equal to the TDMxTFP[TNCF] bit (see page 20-49) should be valid when setting the corresponding TDMxTCR[TEN] bit (see page 20-54). MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 20-59...
Page 682 Receive first threshold interrupt is Enable assertion of the receive first threshold interrupt disabled. when the Receive First threshold Event (RFTE) bit is set Receive first threshold interrupt is (see page 20-65). enabled. MSC8113 Reference Manual, Rev. 0 20-60 Freescale Semiconductor...
Page 683 Transmit Second Threshold Event Enabled Transmit second threshold interrupt is Enable assertion of the transmit second disabled. threshold interrupt when the Transmit second Transmit second threshold interrupt is Threshold Event (TSTE) bit is set. enabled. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 20-61...
Page 684: Status Registers
0x7FF The number of bits between the last two sync events is 2048. TDMxRDBDR TDMx Receive Data Buffers Displacement Register — RDBD Type Reset RDBD Type Reset MSC8113 Reference Manual, Rev. 0 20-62 Freescale Semiconductor...
Page 685 Points to the current displacement of the transmit data in the 0x000000 to the Transmit Data transmit data buffers. The value is unified to all the Buffer (TDBS – 7). transparent channels and is doubled for A/μ law channels. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 20-63...
Page 686 Reset TDMxTNB holds the number of transmit buffers in the TDM transmit local buffer. Table 20-37. TDMxTNB Bit Descriptions Name Reset Description Settings — Reserved. Write to zero for future compatibility. 0–26 MSC8113 Reference Manual, Rev. 0 20-64 Freescale Semiconductor...
Page 687 The first threshold A receive first threshold event pointer is determined by the Receive Data Buffer First has occurred. Threshold field (RDBFT). For details, see Section 20.2.6.3. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 20-65...
Page 688 A transmit first threshold is empty. The first threshold pointer is determined by the event has occurred. Transmit First Threshold Register (TDMxTFTR). For details, see Section 20.2.6.3. MSC8113 Reference Manual, Rev. 0 20-66 Freescale Semiconductor...
Page 689 Adaptation Sync Distance Register register contains a new value that the (TDMxASDR) loads the new value. SC140 core should read. TDMxRSR TDMx Receive Status Register — Type Reset — RSSS RENS Type Reset MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 20-67...
Page 690 The propagation of the enable/disable may The transmit machine is be delayed because of the different clock domains. enabled. Note: If the serial clock is not toggling, this bit may not reflect updated values. MSC8113 Reference Manual, Rev. 0 20-68 Freescale Semiconductor...
Page 691: System Bus Registers
Local Bus Transfer Error Status and Control Register (L_TESCR1) indicates whether an error has occurred on the local bus and L_TESCR1[TC] indicates whether the TDM initiated the error access (see page 12-112). The register is undefined at reset. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 20-69...
Page 692 00010 Receive TDM1. 00011 Transmit TDM1. 00100 Receive TDM2. 00101 Transmit TDM2. 00110 Receive TDM3. 00111 Transmit TDM3. The other values are reserved. — — Reserved. 5–7 MSC8113 Reference Manual, Rev. 0 20-70 Freescale Semiconductor...
Page 693: Uart
During transmission, the UART generates an interrupt request when its data register can be written with new character. An SC140 core or external host then writes the character to the data register. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 21-1...
Page 694 Register Figure 21-2. UART Block Diagram Figure 21-3 shows the full duplex UART system in which the MSC8113 UART transmits and receives simultaneously. A higher-level protocol should handle the full duplex communication to guarantee that no more than one slave UART transmits to the...
Page 695 Chip ID =n2 URXD UART-Rx UTXD UART-Tx Chip ID =n3 URXD UART-Rx UTXD UART-Tx Note: The RC value on the MultiPoint TxD may limit system baud rate. Figure 21-3. Full Duplex Multiple UART System MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 21-3...
Page 696 Chip ID =n1 Master device UART-Rx UART-Tx Chip ID =n2 UART-Rx UART-Tx Chip ID =n3 UART-Rx UART-Tx Note: The RC value on the MultiPoint UTXD might limit system baud rate. Figure 21-4. Single-Wire Connection MSC8113 Reference Manual, Rev. 0 21-4 Freescale Semiconductor...
Page 697 Stop Bit Note: The address bit identifies the frame as an address character. The address bit is bit 7 (M = 0) or bit 8 (M = 1). See Section 21.2.7, Receiver Wake-Up. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 21-5...
Page 698: Transmitter
The UART transmitter accommodates either 8-bit or 9-bit data characters. The state of the M bit in the SCI Control Register (SCICR) determines the length of the data characters. When 9-bit data is transmitted, bit T8 in the SCIDR is the ninth bit (bit 8). MSC8113 Reference Manual, Rev. 0 21-6 Freescale Semiconductor...
Page 699: Character Transmission
(SCIDR), while the shift register is still shifting out the first character. If the TDRE flag is set and no new data or break character transferred to the shift register, the UART sets a flag, transmit complete (TC) and becomes idle. UTXD MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 21-7...
Page 700 1 stop bit goes into the most significant bit position. Hardware supports odd or even parity. When parity is enabled, the most significant bit (msb) of the data character is the parity bit. MSC8113 Reference Manual, Rev. 0 21-8 Freescale Semiconductor...
Page 701: Break Characters
SBK bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. The automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next frame. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 21-9...
Page 702: Idle Characters
The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the SCICR[M] bit determines the length of data characters. When receiving 9-bit data, bit R8 in the SCIDR is the ninth bit (bit 8). MSC8113 Reference Manual, Rev. 0 21-10 Freescale Semiconductor...
Page 703: Character Reception
R8 bit in SCIDR if the SCI is in 9-bit data format. Reading RDRF bit at SCISR and then reading new data from SCIDR clears RDRF flag. Repeat step 2 for each subsequent reception. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 21-11...
Page 704: Data Sampling
To locate the start bit, data sampling logic searches for a logic 0 preceded by three logic 1s. When the falling edge of a possible start bit occurs, the RT clock logic begins to count to 16. MSC8113 Reference Manual, Rev. 0 21-12...
Page 705 NF, is set if not all samples have the same logical value. Table 21-5 summarizes the results of the data bit samples. Table 21-5. Data Bit Recovery RT8, RT9, and RT10 Samples Data Bit Determination Noise Flag MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 21-13...
Page 706 The noise flag is not set because the noise occurred before the start bit was found. Start Bit URXD Samples RT Clock RT Clock Count Reset RT Counter Figure 21-10. Start Bit Search Example 1 MSC8113 Reference Manual, Rev. 0 21-14 Freescale Semiconductor...
Page 707 Actual Start Bit Perceived Start Bit URXD Samples 0 0 0 0 RT Clock RT Clock Count Reset RT Counter Figure 21-12. Start Bit Search Example 3 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 21-15...
Page 708 Depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may set the framing error flag. MSC8113 Reference Manual, Rev. 0 21-16...
Page 709: Framing Error
The FE flag is set at the same time that the RDRF flag is set. FE inhibits further data reception until it is cleared. Clear SCISR[FE] by reading SCISR and then reading the SCIDR. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 21-17...
Page 710: Parity Error
As the receiver samples an incoming frame, it resynchronizes the RT clock on any valid falling edge within the frame. Resynchronization within frames corrects a misalignment between transmitter bit times and receiver bit times. MSC8113 Reference Manual, Rev. 0 21-18 Freescale Semiconductor...
Page 711: Slow Data Tolerance
163 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is: ((170 – 163) / 170) × 100 = 4.12% MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 21-19...
Page 712: Fast Data Tolerance
The SCICR[WAKE] bit determines how the SCI is brought out of the standby state to process an incoming message. This wake bit enables either idle line wake-up or address mark wake-up. MSC8113 Reference Manual, Rev. 0 21-20 Freescale Semiconductor...
Page 713: Idle Input Line Wake-Up (Wake = 0)
After reset the UART transmitter and receiver are disabled and are not driven. UTXD URXD For information on initializing the transmitter, refer to Section 21.1.1. For information on initializing the receiver, refer to Section 21.2.1. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 21-21...
Page 714: Modes Of Operation
UTXD multiple-transmitter system. Then the signals of nonactive transmitters follow the logic UTXD level of an active one. External pull-up resistors are necessary on open-drain outputs. MSC8113 Reference Manual, Rev. 0 21-22 Freescale Semiconductor...
Page 715: Loop Operation
Therefore, disable the receiver and transmitter (SCICR[TE] = 0, SCICR[RE] = 0) before entering Stop mode. 21.4.5 Receiver Standby Mode Refer to Section 21.2.7, Receiver Wake-Up. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 21-23...
Page 716: Interrupt Operation
„ SCI Control Register (SCICR), on page 21-25. „ SCI Status Register (SCISR), on page 21-28. „ SCI Data Register (SCIDR), on page 21-30. „ SCI Data Direction Register (SCIDDR), on page 21-31. MSC8113 Reference Manual, Rev. 0 21-24 Freescale Semiconductor...
Page 717 The baud-rate register used by the counter to 19-31 determine the baud rate of the SCI. SCICR SCI Control Register 1 — Type Reset LOOP — RSRC WAKE TCIE ILIE Type Reset MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 21-25...
Page 718 1s sets the parity bit. With odd parity, an odd number of 1s clears the parity bit and an even number of 1s sets the parity bit. MSC8113 Reference Manual, Rev. 0 21-26 Freescale Semiconductor...
Page 719 The external connection that URXD shares can be configured as a GPIO. Note: The function is described for the case in which the PAR[DD28] and PSOR[SO28] are both set (see Chapter 23, GPIO). MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 21-27...
Page 720 Once the RDRF flag is cleared, after it is set by a break or idle character, a valid frame must set the RDRF flag before another break or idle character can set it again. MSC8113 Reference Manual, Rev. 0 21-28 Freescale Semiconductor...
Page 721 Set when the receiver detects a logic 0 during the RT1 time No reception in progress. period of the start bit search. RAF is cleared when the receiver detects an idle character. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 21-29...
Page 722 In 8-bit data format, only SCIDR[24–31] needs to be accessed. When transmitting in 9-bit data format, write to SCIDR[16–31] (one access). Otherwise, write first to T8 and then to the low byte (SCIDR[24–31]). MSC8113 Reference Manual, Rev. 0 21-30 Freescale Semiconductor...
Page 723 UTXD is not driven when the transmitter is disabled (TE=0) or when LOOPS=1. — Reserved. Write to zero for future compatibility. 23–31 Note: The setting descriptions assume that the UTXD signal is configured for UART operation. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 21-31...
Page 724 UART MSC8113 Reference Manual, Rev. 0 21-32 Freescale Semiconductor...
Page 725 Timers The MSC8113 device contains 32 timers of 16 bits each that serve as frequency dividers, watchdog timers, clock generators, and event counters. Each timer receives input from one of 15 sources: six external input signals, eight timer outputs, or the local bus clock (BUSES_CLOCK).
Page 726 Before you reenable a timer, set the compare value to a relatively high number and allow the counter to advance for at least three input clocks to flush the cache. Then reenable the timer. MSC8113 Reference Manual, Rev. 0 22-2 Freescale Semiconductor...
Page 727 Multiplexers Local Clock Timer B7 Timer B8 15 to 1 Timer B9 Timer B10 IPBus Timer B11 Timer B12 Timer B13 Timer B14 Timer B15 Timers Module B Figure 22-1. MSC8113 Timers MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 22-3...
Page 728 Local Bus Clock Multiplexers Counter TIMERA8_OUT TIMERA9_OUT TIMERA10_OUT TIMERA11_OUT TIMERA12_OUT SIU/ TERAx TIMERA13_OUT PAD/GPIO TIMERA14_OUT Event TIMERA15_OUT Register Interrupt to the PIC/LIC TIERAx Interrupt Enable Register Figure 22-2. Timer x Module Block Diagram MSC8113 Reference Manual, Rev. 0 22-4 Freescale Semiconductor...
Page 729 Section 18.4). The clocks automatically restart when they are required. Each of the three MSC8113 SC140 cores can configure the timer modules. The configuration route is from the QBus via the SQBus to the IPBus to the timer modules. The arbitration of the SQBus occurs on the QBus.
Page 730 TE field: If a timer is configured to receive its input clock from another Timer disable. signal, the signal must be driven before the timer is enabled. Timer enable. MSC8113 Reference Manual, Rev. 0 22-6 Freescale Semiconductor...
Page 731 It also illustrates how to restart the timer by writing 1 to the TCR. The configuration registers are: „ TGCRA[INTP] = 0, TGCRA[TOG] = 1 „ TCFRA0[CYC] = 1, TCFRA0[IPOL] = 0 „ TIER[IE0] = 1 „ TCMPA0[COMPVAL] = 0x0123 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 22-7...
Page 732: Timers Programming Model
„ Timer Event Register A (TERA), page 22-18 „ Timer Event Register B (TERB), page 22-18 „ Timer Count Register A (TCNRA[0–15]), page 22-19 „ Timer Count Register B (TCNRB[0–15]), page 22-20 MSC8113 Reference Manual, Rev. 0 22-8 Freescale Semiconductor...
Page 733: Configuration Registers
COMPVAL field. This bit is valid only when (DIR0 = 1). DIR0 Signal Direction TIMER0 is an input. Defines the direction of the TIMER0. TIMER0 is an output. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 22-9...
Page 734 Timer B0 reaches the value of the associated COMPVAL field. This bit is valid only when then TIMER2 is configured as output. — Reserved. Write to zero for future compatibility. MSC8113 Reference Manual, Rev. 0 22-10 Freescale Semiconductor...
Page 735 IE15 IE14 IE13 IE12 IE11 IE10 Type Reset The MSC8113 device generates an interrupt when both the TERA bit and its corresponding enable bit are set. Table 22-6. TIERA Bit Descriptions Name Reset Description Settings — Reserved. Write to zero for future compatibility.
Page 736 Counter changes at the Defines the polarity of the input clock for Timer Ax. IPOL has no clock rising edge. effect if the bus clock is selected. Counter changes at the clock falling edge. MSC8113 Reference Manual, Rev. 0 22-12 Freescale Semiconductor...
Page 737 TDM1RCLK, is selected as an input clock, the corresponding signal line should be configured by the TDM registers as an input clock via the GPIO, in addition to configuring the GPIO registers (see Chapter 20, TDM Interface and Chapter 23, GPIO). MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 22-13...
Page 738 TDM registers as an input clock via the GPIO, in addition to configuring the GPIO registers (see Chapter 20, TDM Interface and Chapter 23, GPIO) MSC8113 Reference Manual, Rev. 0 22-14 Freescale Semiconductor...
Page 739 In Cyclic mode (TCFRBx[CYC] = 1), the counter is cleared and the counting continues. In One-Shot mode (TCFRBx[CYC] = 0), the counter is frozen and its output remains asserted until it is cleared. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 22-15...
Page 740: Control Registers
Note: Writing a value of 1 to the enable bit causes a one-shot configured timer to count again, regardless of whether its value is 0 or 1. MSC8113 Reference Manual, Rev. 0 22-16 Freescale Semiconductor...
Page 741: Status Registers
The MSC8113 device has two groups of status registers: „ Global registers, which hold the compare flags and the Status enable bits. The MSC8113 sets the status flag when an event occurs, and it is cleared by writing a 1 to the associated location.
Page 742 CFn flag, which also clears the associated interrupt. If timer n reaches the TCMPAx value while a 1 is written to the associated CFn flag, the associated CFn flag stays set and is not cleared. MSC8113 Reference Manual, Rev. 0 22-18 Freescale Semiconductor...
Page 743 32 bits, unless the two counters reach their TCMPAx values and stop. When the counter value is read, the maximum value can be TCMPAx – 1. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 22-19...
Page 744 32 bits, unless the two counters reach their TCMPBx values and stop. When the counter value is read, the maximum value can be TCMPBx – 1. MSC8113 Reference Manual, Rev. 0 22-20 Freescale Semiconductor...
Page 745: Gpio
GPIO The MSC8113 device has 32 general-purpose I/O (GPIO) ports that are multiplexed as either GPIO ports or dedicated peripheral interface ports. In addition, fifteen of the GPIOs can be configured to serve as Ethernet interface ports, and fifteen of the GPIOs can be configured to generate interrupts to the Global Interrupt Controller (GIC).
Page 746: Gpio Block Diagram
Dedicated 2 Port Special Options Registers PDIRx Input Output Port Data Direction Registers PODRx Regular Open drain Port Open-Drain Registers PDATx 0 (data) 1 (data) Port Data Registers Figure 23-1. Port Functional Operation MSC8113 Reference Manual, Rev. 0 23-2 Freescale Semiconductor...
Page 747 Dedicated 2 Port Special Options Registers PDIRx Input Output Port Data Direction Registers PODRx Regular Open drain Port Open-Drain Registers PDATx 0 (data) 1 (data) Port Data Registers Figure 23-2. Port Functional Operation MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 23-3...
Page 748: Ethernet Functionality Of Gpio
PAR and PSOR GPIO or Dedicated functionality according to PAR and PSOR GPIO or Dedicated functionality according to PAR and PSOR GPIO or Dedicated functionality according to PAR and PSOR MSC8113 Reference Manual, Rev. 0 23-4 Freescale Semiconductor...
Page 749 Ethernet controller. „ Default values are supplied to internal peripheral inputs connected to this GPIO port. Note: PARx of a GPIO port that has Ethernet functionality should be cleared (0). MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 23-5...
Page 750: Gpio Connection Functions
SIU TMCNT and PIT logic (either when this connection is a GPIO or when it serves the timer blocks). When this connection is programmed as an input to serve the SIU , it maps default TMCLK to the TIMER2 clock input of the timers block. MSC8113 Reference Manual, Rev. 0 23-6 Freescale Semiconductor...
Page 751 GPIO6 default value To IRQ4 IRQ4 Secondary Input IRQ4 Primary Input PAR[DD0] PSOR[SO0] PAR[DD6] PDIR[DR0] PSOR[SO6] PDIR[DR6] Figure 23-4. Using the Default Value to Connect the IRQ4 Secondary to Primary Input Source MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 23-7...
Page 752 — TDM1TSYN (primary) GPIO27 (Inout) — TDM1TCLK DRACK1 DONE1 (Inout) DACK1 — — TDM1TDAT (Inout) — DREQ2 — TDM1RSYN (primary) GPIO28 (Inout) DACK2 — — TDM1RCLK (Inout) — — — TDM1RDAT (Inout) MSC8113 Reference Manual, Rev. 0 23-8 Freescale Semiconductor...
Page 753: Gpio Programming Model
„ Pin Open-Drain Register (PODR), page 23-10 „ Pin Data Register (PDAT), page 23-10 „ Pin Data Direction Registers (PDIR), page 23-11 „ Pin Assignment Register (PAR), page 23-11 „ Pin Special Options Registers (PSOR), page 23-12 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 23-9...
Page 754 PDAT register is still stored in the output register, but it is prevented from reaching the actual pin. When the PDAT register is read, the state of the actual pin is read. MSC8113 Reference Manual, Rev. 0 23-10...
Page 755 Dedicated peripheral can be determined by other bits, such as those in the PSOR. function. When a GPIO port has Ethernet functionality (see Table 23-1), its PAR bit should be set to 0. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 23-11...
Page 756 PSOR or PDIR bit is programmed, an external connection may function for a short period as an unwanted dedicated function and cause unpredictable behavior. Thus, it is recommended that you program the GPIO in the following sequence: PSOR, PODR, PDIR, PAR. MSC8113 Reference Manual, Rev. 0 23-12 Freescale Semiconductor...
Page 757: I²C Software Module
This chapter assumes that you are already familiar with the I C bus specification. Note that the MSC8113 GPIO specifications do not fully conform to the I C bus electrical specification. Refer to the MSC8113 Technical Data sheet for details.
Page 758 High Period time for 50 KHz SCL at 500 Mhz core frequency and Core/Bus frequency ratio of 3. Refer to Table 24-4. HALF_LOW_PERIOD 0x00000200 Half time of the Low Period for 50 KHz SCL at 500 Mhz core frequency. Refer to Table 24-4. MSC8113 Reference Manual, Rev. 0 24-2 Freescale Semiconductor...
Page 759: I2C_Txrx_Bit Routine
Global Register Use D4, D5,D6, D7, D8, D14. Local Register Use D0 Timing of Low Period, Bit value extraction. D1 Bit value to set the SDA line. Routine call i2c_sample_gpio Figure 24-2. i2c_txrx_bit Routine MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 24-3...
Page 760 Wait HIGH_PERIOD. Refer to Table 24-4. hperiod_loop Check for SDA to be the same, and for start/stop condition. bsr i2c_sample_gpio GPIO at D2. bmtsts #SCL_SDA_10,d2.l Figure 24-2. i2c_txrx_bit Routine (Continued) MSC8113 Reference Manual, Rev. 0 24-4 Freescale Semiconductor...
Page 761: I2C_Txrx_Byte Routine
D4, D6, D7. Local Register Use Routine call i2c_txrx_bit Signal Diagram Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 ACK Bit Figure 24-3. i2c_txrx_byte Routine MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 24-5...
Page 762 Return if arbitration lost or start/stop condition indication. asr d4,d4 asl d6,d6 Next bit read. tsteq d4 bf byte_loop bmchg #$1,d7.l bsr i2c_txrx_bit asr d6,d6 bmchg #$1,d7.l Figure 24-3. i2c_txrx_byte Routine MSC8113 Reference Manual, Rev. 0 24-6 Freescale Semiconductor...
Page 763: I2C_Read_Sequentialdata Routine
Transmit slave address and A ift rts Return for any arbitration lost, wrong ACK, or start/stop condition indication. clr d5 Transmit Memory address A to A move.l r3,d0 Figure 24-5. i2c_read_SequentialData Routine MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 24-7...
Page 764 #$0001,d11.h Checksum calculation. ift asll #$8,d6 eor d6,d10 bmchg #$0001,d11.h tsteq d12 bf read_byte_loop bsr i2c_assert_stop bmtsts #$f,d11.l Clear T bit. Figure 24-5. i2c_read_SequentialData Routine (Continued) MSC8113 Reference Manual, Rev. 0 24-8 Freescale Semiconductor...
Page 765: I2C_Sample_Gpio Routine
Description i2c_sample_gpio Read GPIO to D1 moveu.w PDAT_ADDR,d1 and d8,d1 Read GPIO to D2 loop_sample moveu.w PDAT_ADDR,d2 and d8,d2 D1==D2 cmpeq d1,d2 tfr d2,d1 bf loop_sample D1=D2 PIN_VAL=D2 Figure 24-6. i2c_sample_gpio Routine MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 24-9...
Page 766: I2C_Assert_Start Routine
Exit loop on SCL = 0. deceq d0 bf start_loop start_rts Figure 24-7. i2c_assert_start Routine Table 24-5. HD_STA_TIME Timing Core_Clock Core_Clock Core_Clock Core_Clock Parameter at Core/Bus=3 at Core/Bus=4 at Core/Bus=5 at Core/Bus=6 HD_STA_TIME 0x21 MSC8113 Reference Manual, Rev. 0 24-10 Freescale Semiconductor...
Page 767: I2C_Assert_Stop Routine
Figure 24-8. i2c_assert_stop Routine Table 24-6. BUF_TIME Timing Core_Clock Core_Clock Core_Clock Core_Clock Parameter at Core/Bus = 3 at Core/Bus = 4 at Core/Bus = 5 at Core/Bus = 6 BUF_TIME 0x42 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 24-11...
Page 768: I2C_Waitfor_Startcond_Busfreetime Routine
Wait BUS_FREE_TIME. Refer to Table 24-7. wait_loop bsr i2c_sample_gpio bmtstc #SCL_SDA_10,d2.l If SCL = 0, rerun BusFree wait loop. i2c_WaitFor_StartCond_BusFreeTi bmtstc #SCL_SDA_01,d2.l bt wait_rts deceq d0 bf wait_loop wait_rts Figure 24-9. i2c_WaitFor_StartCond_BusFreeTime Routine MSC8113 Reference Manual, Rev. 0 24-12 Freescale Semiconductor...
Page 769: I2C_Write_Sequentialdata Routine
Slave address move.l r3,d0 extractu #$3,#$10,d0,d5 asl d5,d5 bmset #$a0,d5.l bsr i2c_txrx_byte ift rts clr d5 Memory address move.l r3,d0 extractu #$8,#$8,d0,d5 bsr i2c_txrx_byte Figure 24-11. i2c_write_SequentialData Routine MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 24-13...
Page 770 (r4)+,d5 bsr i2c_txrx_byte ift rts bsr i2c_assert_stop inca r3 move.l #$100000,d0 Burn waiting time. write_loop deceq d0 bf write_loop deceq d12 bf i2c_write_SequentialData Figure 24-11. i2c_write_SequentialData Routine (Continued) MSC8113 Reference Manual, Rev. 0 24-14 Freescale Semiconductor...
Page 771: Ethernet Controller
(MII) that can support various physical implementations. Other protocols developed modifications to this basic interface, including the reduced media-independent interface (RMII) and the serial media-independent interface (SMII). The MSC8113 Ethernet controller supports MII, RMII, and SMII for the 10/100 Ethernet rate. 25.1...
Page 772 „ Destination address (DA). The first bit of a total of 48 bits identifies the address as an individual address (0) or a group address (1). The second bit indicates whether the address is locally-defined (1) or globally-defined (0). MSC8113 Reference Manual, Rev. 0 25-2 Freescale Semiconductor...
Page 773 FCS last. The bits of each octet are transmitted least-significant bit (lsb) first. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 774 OUI), which is assigned by the IEEE. The last two bytes contain the type value set from the original Ethernet specifications if SNAP OUI = 00-00-00, or they become a SNAP protocol identifier if SNAP OUI is non zero. MSC8113 Reference Manual, Rev. 0 25-4 Freescale Semiconductor...
Page 775: Media-Independent Interfaces
Media-Independent Interfaces The Ethernet protocol can support a variety of physical interfaces to transfer information. The MSC8113 Ethernet controller supports three interfaces: MII, RMII, and SMII. The major difference between them is the number of signals used for data transfer: „...
Page 776: Modes Of Operation
• MIIGSK_CFGR[IFMODE] = 10 • MIIGSK_CFGR[LBMODE] = 1 • SMII_SYNC_DIR[SYNC_IN] = 0 • SMII_SYNC_DIR[SYNC] = 1 • MACCFG1R[MIILB] = 0 Echo mode (MII mode only) MIIGSK_CFGR[IFMODE] = 00 MIIGSK_CFGR[EMODE] = 1 MIIGSK_CFGR[LBMODE} = 0 MSC8113 Reference Manual, Rev. 0 25-6 Freescale Semiconductor...
Page 777: Mii Mode
0 selects 100 Mbps operation. For 10 Mbps operation, set the frequency by writing a 1 to MIIGSKCFGR[FRCONT]. The SMII reference clock generates both transmit and receive clocks for the MII. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-7...
Page 778: Special Modes
This configuration causes the SMII MAC transmit outputs to be looped back to the MAC receive inputs. Clearing this bit results in a return to normal operation in SMII SYNC Out mode. MSC8113 Reference Manual, Rev. 0 25-8 Freescale Semiconductor...
Page 779: Echo Mode
The MIIGSK_IMASK and MIIGSK_IEVENT registers are valid only in SMII mode. 25.4.5 Management Interface The management interface (ETHMDIO/ETHMDC) is identical to that defined in IEEE Std. 802.3u™ for all normal operating modes (MII/RMII/SMII). MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-9...
Page 780: External Signals
HD56/D56/ETHRX_DV/ GPIO10/TDM2TCLK/IRQ8/ETHRX_DV/ RX_DV CRS_DV — ETHCRS_DV ETHCRS_DV HD57/D57/ETHRX_ER GPIO11/TDM2TDAT/IRQ9/ETHRX_ER/ETHTXD RX_ER RX_ER HD58/D58/ETHMDC GPIO13/TDM2RCLK/IRQ11/ETHMDC HD59/D59/ETHMDIO GPIO9/TDM2SYN/IRQ7/ETHMDIO MDIO MDIO MDIO HD60/D60/ETHCOL GPIO8/TDM3RDAT/IRQ6/ETHCOL/NC — — Non-Multiplexed/Dedicated Signals ETHRX_CLK/NC/ETHSYNC_IN RX_CLK — SYNC_IN ETHTX_CLK/ETHREF_CLK/ETHCLOCK TX_CLK REF_CLK CLOCK MSC8113 Reference Manual, Rev. 0 25-10 Freescale Semiconductor...
Page 781 400 ns or 2.5 MHz, but the device can be configured as fast as 12.5 MHz, if the PHY supports that speed. ETHMDIO Management Data — ETHMDIO is a bidirectional signal to input PHY-supplied status during management read cycles and output control during management write cycles. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-11...
Page 782: Ethernet Controller Interfaces
Management Data — Inputs PHY-supplied status during management read cycles and outputs control during management write cycles. 25.6 Ethernet Controller Interfaces The following sections give a detailed functional description of the supported interfaces. MSC8113 Reference Manual, Rev. 0 25-12 Freescale Semiconductor...
Page 783: Mii
Ethernet Controller Interfaces 25.6.1 MII The MSC8113 Ethernet controller MII receive and transmit modules comply with the IEEE Std. 802.3. 25.6.1.1 MII Transmit Flow The Ethernet controller drives the transmit enable ( ) output signal, the ethernet transmit ETHTX_EN ) output data bus, and the ethernet transmit error ( ) output signal on the ETHTXD[3–0]...
Page 784: Mii Receive Flow
Figure 25-6. MII Receive Flow in 100 Mbps Full Duplex Mode with No Error 25.6.2 RMII The MSC8113 Ethernet controller RMII receive and transmit interface complies with the RMII specification defined by the RMII consortium. MSC8113 Reference Manual, Rev. 0...
Page 785: Rmii Transmit Flow
DA TA DA TA DA TA DA TA DA TA DA TA DA TA DA TA 00 00 00 00 ETHTXD[1–0] Figure 25-8. End Of Frame In RMII Mode 100 MBPS Full Duplex MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-15...
Page 786: Rmii Receive Flow
CRS_DV ETHRX_ER ETHRXD[1–0] 4 Bytes Figure 25-10. End Of Receive Frame in RMII Mode 25.6.3 SMII The MSC8113 Ethernet controller SMII receive and transmit interface complies with the Cisco serial MII specification. MSC8113 Reference Manual, Rev. 0 25-16 Freescale Semiconductor...
Page 787: Smii Transmit Flow
10-Bit IFG segment 10-Bit IFG segment 10-Bit IFG segment IFG Data IFG Data IFG Data ETHTXD TX_ER TX_EN Figure 25-11. Transmission Flow with No Errors IFG state in SMII Mode (100 Mbps) MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-17...
Page 788 10-Bit valid segment 10-Bit IFG segment Data IFG Data ETHTXD 4 Bytes TX_ER TX_EN Figure 25-13. Transmission Flow with No Errors End Of Frame in SMII SYNC Mode (Full Duplex 100 Mbps MSC8113 Reference Manual, Rev. 0 25-18 Freescale Semiconductor...
Page 789: Smii Receive Flow Mode
ETHSYNC 10-Bit IFG segment 10-Bit IFG segment 10-Bit IFG segment IFG Data IFG Data IFG Data ETHRXD RX_DV Figure 25-14. Receive Flow with No Errors IFG State in SMII Mode (100 Mbps) MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-19...
Page 790 Figure 25-15. Receive Flow with No Errors Start Of Valid Frame SMII Mode (100 Mbps) ETHCLOCK ETHSYNC 10-Bit valid segment 10 Bit IFG segment Data IFG Data ETHRXD 4 Bytes RX_DV Figure 25-16. Receive Flow with No Errors End Of Valid Frame SMII Mode (100 Mbps) MSC8113 Reference Manual, Rev. 0 25-20 Freescale Semiconductor...
Page 791: Mac Control Of Csma/Cd
Ethernet controller is deferring to a carrier, the Ethernet controller simply waits until the end of the carrier event plus the IPG timing before it fulfills the request. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-21...
Page 792: Controlling Packet Flow
(called a scan cycle) even though scan cycles are not explicitly defined in the standard. When requested (by setting MIIMCOMR[SCYC]), the MSC8113 performs repetitive read cycles of the PHY status register, for example. This method allows link characteristics to be monitored more efficiently. The different fields in the MII management indicator register (scan, not valid and busy) indicate availability of each read of the scan cycle to the host from MIIMSTATR[PHYS].
Page 793: Rmon Support
CSE cleared, it accepts the frame without any further search. If a subsequent pattern match is found but CSE is set, the search continues. This process continues until the end of frame (EOF) or until the first 256 bytes are received. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-23...
Page 794 CSE = 0? 256 Bytes Received or Reject All? *Address Recognition Match? Receive Frame and Perform any * See address recognition flowchart Action Determined by Discard Frame Match(es) Figure 25-17. Frame Acceptance/Rejection Flowchart MSC8113 Reference Manual, Rev. 0 25-24 Freescale Semiconductor...
Page 795: Destination Address Recognition
The pattern matching capabilities are explained in detail in Section 25.10.2, Receive Frame Processing with Pattern Matching, on page 25-30. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-25...
Page 796 Use Group Use Individual Table Table Hash Match? Broadcast Reject Promiscuous? Receive Frame Back to Pattern Matching Flowchart and Perform Any Discard Frame Action Determined by Match Figure 25-18. Ethernet Address Recognition Flowchart MSC8113 Reference Manual, Rev. 0 25-26 Freescale Semiconductor...
Page 797: Hash Table Algorithm
The hash tables cannot be used to reject frames that match a set of selected addresses because unintended addresses can map to the same bit in the hash table. Pattern matching can be used to reject frames with unintended address hits in the hash table. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-27...
Page 798: Buffer Descriptors
BDs in memory. Because of prefetching, a minimum of two BDs per ring are required. This applies to both the transmit and the receive descriptor rings. Software also points the data MSC8113 Reference Manual, Rev. 0 25-28 Freescale Semiconductor...
Page 799 RBASE Register RxBD Table Status and Control Data Length Buffer Pointer Rx Buffer Figure 25-19. Example Memory Structure for an 8-Byte BD Beginning BD pointer W = 1 Figure 25-20. Buffer Descriptor Ring MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-29...
Page 800: Receive Frame Processing With Pattern Matching
Ethernet controller frame processing features for specific applications. Table 25-9. Frame Processing Table Example Pattern Offsets 8-byte Patterns Operation Queue 16, 35 P4–P5 File 32,55 P8–P9 File 16,15 P10–P11 File P12–P13 Reject P14–P15 Reject MSC8113 Reference Manual, Rev. 0 25-30 Freescale Semiconductor...
Page 801: Receive Pattern Matching Filing
„ Entries can be set up so that after an initial match occurs, the search for additional patterns continues, but only if the continue search enable (CSE) bit is set in the hit entry. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 802 „ Pattern matching stops if there is a pattern match with the CSE bit cleared, and the attributes of this entry are used to process the frame. „ The attributes of the last entry matched are used even when 256 bytes or EOF is reached. MSC8113 Reference Manual, Rev. 0 25-32 Freescale Semiconductor...
Page 803 4-byte patterns that make up a concatenated pattern to point to different locations in the frame. In other words, each concatenated pattern can point its MI field anywhere within the 256 bytes of the frame. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-33...
Page 804 (PATTRBn[PMF] is set), reject all (RCTRL[RA]), short frame received, reject short frame (RCTRL[RSF]), unicast (UC) hit, multicast (MC) hit, broadcast (BC) hit, promiscuous (RCTRL[PROM]), broadcast (BC) reject (RCTRL[BC_REJ]), and pause frame received. MSC8113 Reference Manual, Rev. 0 25-34 Freescale Semiconductor...
Page 805: Filing
Figure 25-23 depicts an example of how to prepare multiple patterns to examine different fields within a frame. Depending on which patterns hit or win (for multiple pattern hits), the frame can be filed to a preselected queue. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-35...
Page 806: Transmit Frame Processing With Insertion
„ Insert index, which is the number of bytes to jump within the transmit buffer before beginning to insert data „ Insert length, which is the number of bytes of data that are inserted into the buffer MSC8113 Reference Manual, Rev. 0 25-36 Freescale Semiconductor...
Page 807 Resulting expansion Software must ensure that the data length of the frame’s Type/Length field is correct. Figure 25-24. Insertion by Replacement and Insertion by Expansion MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-37...
Page 808: Flow Control
Before transmitting flow control frames, poll the Used Entry Count Register in the FIFO. If the value is equal to or greater than the value in the Alarm Register, use the following recommended steps to transmit flow control frames: MSC8113 Reference Manual, Rev. 0 25-38 Freescale Semiconductor...
Page 809: Interrupt Handling
From Ethernet controller to GIC bit 20 of GCIER RIFGSI Ethernet controller Receive Inter Frame Gap Status From Ethernet controller to all PIC IRQ5 Interrupt (RIFGSI) Note: RIFGSI is used only in SMII mode. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-39...
Page 810 Receive buffer: An RxBD that is not the last one of the frame was updated. Receive frame: A frame was received and the last RxBD of that frame was updated. MSC8113 Reference Manual, Rev. 0 25-40 Freescale Semiconductor...
Page 811: Error-Handling
(RxBD[NO]) error is reported, IEVENT[RXFn] is set, and the alignment error counter increments. The Ethernet controller relies on the statistics collector block to increment the receive alignment error counter (RALN). If there is no CRC error, no error is reported. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-41...
Page 812: Inter-Packet Gap Time
Note: The MAC-to-MAC connection is not defined in the IEEE . Care must be Std. 802.3 taken to ensure that the receive side has enough set-up and hold time. MSC8113 Reference Manual, Rev. 0 25-42 Freescale Semiconductor...
Page 813 MSC8113 Ethernet signals Ethernet MII MAC ETHTX_ER RX_ER ETHTX_EN RX_DV ETHTXD[3–0] RXD[3–0] ETHTX_CLK RX_CLK ETHCOL ETHRXD[3–0] TXD[3–0] ETHRX_ER TX_ER ETHRX_CLK TX_CLK ETHRX_DV TX_EN ETHCRS Figure 25-26. Full Duplex MAC-to-MAC Connection In MII Mode (Transparent) MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-43...
Page 814 Figure 25-27. Ethernet Controller-to-PHY Connection in RMII Mode Ethernet RMII MAC MSC8113 Ethernet signals 50 MHz Clock CRS_DV ETHTX_EN RXD[1–0] ETHTXD[1–0] ETHREF_CLK REF_CLK ETHRXD[1–0] TXD[1–0] RX_ER ETHRX_ER CRS_DV TX_EN Figure 25-28. Full Duplex MAC-to-MAC Connection In RMII Mode MSC8113 Reference Manual, Rev. 0 25-44 Freescale Semiconductor...
Page 815 ETHMDIO Figure 25-29. Ethernet Controller-to-PHY Connection in SMII Mode MSC8113 Ethernet signals Ethernet SMII MAC 125 MHz Clock ETHTXD ETHSYNC_IN SYNC ETHCLOCK CLOCK ETHRXD Figure 25-30. Ethernet Controller-to-MAC Connection in SMII Mode MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-45...
Page 816: Initialization And Reset
(MAC-to-PHY mode). Before you change the PHY speed via software, you must first clear MACCFG1R[TXEN, RXEN] bits (page 25-84). Select MII, RMII, or SMII mode. MIIGSK Configuration Register (MIIGSK_CFGR) page 25-96. MSC8113 Reference Manual, Rev. 0 25-46 Freescale Semiconductor...
Page 817 For both methods, ensure that the top (first) TxBD in the transmitter ring is the last to have its ready bit set. For example, if the frame is described by three TxBDs, set TxBD[R] in the last TxBD first, then the middle TxBD, perform either method one or MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-47...
Page 818 Set the MACCFG1R[SRESET] bit (page 25-84). Clear the MACCFG1R[SRESET] bit (page 25-84). Write 01 to the MACCFG2R[22–23] bits (page 25-85). Set DMAMR[9] (page 25-61). Set FRXCTRLR[30] (page 25-63). Configure the MIIGSK_CFGR (page 25-96). MSC8113 Reference Manual, Rev. 0 25-48 Freescale Semiconductor...
Page 819: Ethernet Controller Programming Model
This section describes the Ethernet controller registers in detail. The discussion is organized around the following register groupings. Refer to Chapter 8, Memory Map for information on the location of the registers. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-49...
Page 820 25-80 Maximum Receive Buffer Length R0R1 Register MRBLR0R1 page 25-81 Maximum Receive Buffer Length R2R3 Register MRBLR2R3 page 25-82 RxBD Pointer 0–3 RBPTRn page 25-82 Receive Descriptor Base Address RBASEn page 25-83 MSC8113 Reference Manual, Rev. 0 25-50 Freescale Semiconductor...
Page 821 RFLR page 25-113 Receive Code Error Counter RCDE page 25-114 Receive Carrier Sense Error Counter RCSE page 25-114 Receive Undersize Packet Counter RUND page 25-115 Receive Oversize Packet Counter ROVR page 25-115 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-51...
Page 822 Data Structures (Buffer Descriptors) 8-Byte Transmit Data Buffer Descriptor TxBD page 25-137 32-Byte Transmit Data Buffer Descriptor TxBD page 25-139 8-Byte Receive Buffer Descriptor RxBD page 25-144 32-Byte Receive Buffer Descriptor RxBD page 25-146 MSC8113 Reference Manual, Rev. 0 25-52 Freescale Semiconductor...
Page 823: General Control And Status Registers
Reserved. Write to zero for future compatibility. MSRO MSTAT Register Overflow No MSTAT Register overflow. Generates an interrupt if the count for one of the MSTAT MSTAT Register overflow. registers exceeds the size of the register. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-53...
Page 824 An RxBD from queue 3 with the Interrupt (I) bit in its status Receive buffer. word was updated but was not the last BD of the frame. — Reserved. Write to zero for future compatibility. 20–22 MSC8113 Reference Manual, Rev. 0 25-54 Freescale Semiconductor...
Page 825 IEVENT bit is cleared either by writing a 1 to it, or by writing a 0 to the corresponding IMASK bit. Table 25-20. IMASK Bit Descriptions Reset Description Settings Reserved. Write to zero for future compatibility. RXCEN Receive Control Interrupt Enable RCI disabled. RCI enabled. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-55...
Page 826 Receive Frame Queue 0 Interrupt Enable RFQ0I disabled. RFQ0I enabled. RXFEN1 Receive Frame Queue 1 Interrupt Enable RFQ10I disabled. RFQ1I enabled. RXFEN2 Receive Frame Queue 2 Interrupt Enable RFQ2I disabled. RFQ2I enabled. MSC8113 Reference Manual, Rev. 0 25-56 Freescale Semiconductor...
Page 827 32-byte BD format. This bit must be set must be set before the Ethernet controller is enabled. It must not be changed without proper care. — Reserved. Write to zero for future compatibility. 25–31 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-57...
Page 828 (PTE) represent the extended pause control parameter. The pause time is measured in units of pause_quanta, equal to 512 bit times.The pause time can range from 0 to 65535 pause_quanta or 0 to 33553920 bit times. For details, see Section 25.11, Flow Control, on page 25-38. MSC8113 Reference Manual, Rev. 0 25-58 Freescale Semiconductor...
Page 829 DMA Control Register — Type Reset — — — Type Reset DMACTRL configures the DMA controller. Table 25-24. DMACTRL Bit Descriptions Reset Description Settings — Reserved. Write to zero for future compatibility. 0–26 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-59...
Page 830 “Wait” mode, the Ethernet controller allows two additional to TSTAT[THLT]. reads of a descriptor that is not ready before it enters a halt state. No interrupt is driven. To resume transmission, software must clear TSTAT[THLT]. MSC8113 Reference Manual, Rev. 0 25-60 Freescale Semiconductor...
Page 831 00 Low priority 14–15 Sets the transmit/receive transaction priority. 01 Mid priority 10 Mid priority 11 High priority — Reserved. Always write a 0 to this bit after any reset or configuration. 16–31 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-61...
Page 832: Fifo Control And Status Registers
Type Reset — — FULL EMPTY — Type Reset FRXSTATR contains the status bits of the Rx FIFO controller. This register is read/write by software. This register is cleared at system reset. MSC8113 Reference Manual, Rev. 0 25-62 Freescale Semiconductor...
Page 833 Always write a 1 to this bit after any reset or reconfiguration. — Reserved. Write to zero for future compatibility. FRXALAR FIFO Receive Alarm Register — Type Reset — FRXALAR Type Reset MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-63...
Page 834 Indicates the value to turn off the alarm state. The alarm turns off if the FIFO Rx Used Entry Count falls to less than or equal to that of the FIFO Receive Alarm Shutoff Register. MSC8113 Reference Manual, Rev. 0 25-64...
Page 835 FIFO falls to a value less than or equal to the value in the FRXPSR, the panic condition ends. This register is read/write by software. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 836 Not Full Indicates whether the Tx FIFO is full. Full EMPTY Tx FIFO Empty Not empty. Indicates whether the Tx FIFO is empty. Empty. — Reserved. Write to zero for future compatibility. MSC8113 Reference Manual, Rev. 0 25-66 Freescale Semiconductor...
Page 837 DMA writes to the FIFO. Note: Before configuring the Ethernet controller to half duplex MII mode, write a value of 0x25 to this field to prevent data loss if multiple collisions occur during data transfer. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-67...
Page 838 FIFO becomes greater than or equal to that in the FIFO Tx Starve Shutoff Register (FTXSSR). FTXSSR FIFO Transmit Starve Shutoff Register — Type Reset — FTXSS Type Reset MSC8113 Reference Manual, Rev. 0 25-68 Freescale Semiconductor...
Page 839: Transmit Control And Status Registers
Flow control pause frame transmitter pauses for the duration defined in the received received. pause frame. This bit automatically clears after the pause duration is complete. RFCP is written by Ethernet controller. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-69...
Page 840 DMA function. To restart the transmission function halted. transmission function, you must clear this bit by writing a one to it. — Reserved. Write to zero for future compatibility. 1–31 MSC8113 Reference Manual, Rev. 0 25-70 Freescale Semiconductor...
Page 841 In 32-byte mode (ECNTRL[DBDS] is set), this field must be 32-byte aligned so that bits 27 and 28 are reserved in 32-byte mode. The DMA module writes to CTBPTR internally. — Reserved. Write to zero for future compatibility. 29–31 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-71...
Page 842 W (wrap) bit in the last BD, you can select how many BDs to allocate for the transmit packets. You must initialize TBASE before enabling the Ethernet controller transmit function. — Reserved. Write to zero for future compatibility. 29-31 MSC8113 Reference Manual, Rev. 0 25-72 Freescale Semiconductor...
Page 843 IEVENT[TXF] is set after this buffer is serviced. Last in Frame The OSTBD is always the last in the frame, so L is always set. This bit is hardwired to a value of 1 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-73...
Page 844 16–31 Data length is the number of octets the Ethernet controller should transmit from the BD data buffer. The Ethernet controller never modifies this value. This bit is written by the user. MSC8113 Reference Manual, Rev. 0 25-74 Freescale Semiconductor...
Page 845 Contains the address of the associated data buffer. There are no alignment requirements for this address. The buffer must reside in memory external to the Ethernet controller. The Ethernet controller never modifies this value. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-75...
Page 846 TxBD[DL]. Insertion error occurs for replacement if the index + length is greater than TxBD[DL]. The Ethernet controller never modifies this value. OS32TBDR Out-of-Sequence 32 Byte TxBD Reserved Register — Type Reset — Type Reset MSC8113 Reference Manual, Rev. 0 25-76 Freescale Semiconductor...
Page 847 Contains the number of bytes of data that is inserted into the buffer. If this field holds a value of zero, no insertion occurs, and the values in the Tx insert buffer pointer and the insert index field are considered invalid. The Ethernet controller never modifies this value. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-77...
Page 848: Receive Control And Status Registers
For short frames to be received when RSF=1, a DA MINFLR bytes. hit or a pattern match hit accept needs to occur. When RSF=0, all frames shorter than MINFLR are automatically rejected. MSC8113 Reference Manual, Rev. 0 25-78 Freescale Semiconductor...
Page 849 All Ethernet controller receive A write with a value of 1 re-enables the queue for receiving. activity to RxBD queue 2 is halted. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-79...
Page 850 CRBPTR contains the address of the RxBD that is either being processed or was most recently processed. The DMA module writes to this register internally, and you should never write to it. MSC8113 Reference Manual, Rev. 0 25-80 Freescale Semiconductor...
Page 851 Therefore, user-supplied buffers must be at least as large as the MRBLR0. — To ensure that MRBLR1 and MRBLR0 are multiples of 64, these bits are reserved and should be 26–31 cleared. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-81...
Page 852 MRBLR2. — To ensure that MRBLR2 and MRBLR3 are multiples of 64, these bits are reserved and should be 26–31 cleared. RBPTRn RxBD Pointer 0-3 RBPTRn Type Reset RBPTRn — Type Reset MSC8113 Reference Manual, Rev. 0 25-82 Freescale Semiconductor...
Page 853 Together with setting the wrap (W) bit in the last BD, you can select how many BDs to allocate for the receive packets. — Reserved. Write to zero for future compatibility. 29–31 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-83...
Page 854: Mac Registers
Reset Tx Function Normal operation. Puts the transmit function block into reset. This block performs Resets the transmit function the frame transmission protocol. block. — Reserved. Write to zero for future compatibility. 16–22 MSC8113 Reference Manual, Rev. 0 25-84 Freescale Semiconductor...
Page 855 This bit is cleared by default. MACCFG2R MAC Configuration 2 Register — Type Reset Boot PREAL — — LENC — PADCRC CRCEN FDUP Type Reset Boot MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-85...
Page 856 PAD/CRC ENABLE is set, CRC ENABLE is ignored. FDUP Full Duplex Half-duplex mode. Selects half-duplex or full-duplex mode. Full-duplex mode. IPGIFGR Inter-Packet Gap/Inter-Frame Gap Register — NBBIPG1 — NBBIPG2 Type Reset MIFGE — BBIPG Type Reset MSC8113 Reference Manual, Rev. 0 25-86 Freescale Semiconductor...
Page 857 ABEB BPNB Type Reset RTXM — Type Reset HAFDUPR controls the carrier-sense multiple access/collision detection (CSMA/CD) logic. Half-duplex is supported for both 10 Mbps and 100 Mbps operation. This register is user-programmable. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-87...
Page 858 Because the collision window starts at the beginning of transmission, the preamble and SFD are included. Its default of 0x37 (55d) corresponds to the count of frame bytes at the end of the window. MSC8113 Reference Manual, Rev. 0 25-88 Freescale Semiconductor...
Page 859 Description — Reserved. Write to zero for future compatibility. 0–21 Excess Deferral Set if the MAC excessively defers a transmission. It clears if read. This bit latches high. — 000000001 Reserved. 23–31 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-89...
Page 860 Holds the third octet of the station address, which defaults to a value of 0x00. Station Address, Octet 4 24–31 Holds the fourth octet of the station address, which defaults to a value of 0x00. MSC8113 Reference Manual, Rev. 0 25-90 Freescale Semiconductor...
Page 861 Holds the fifth octet of the station address, which defaults to a value of 0x00. Station Address, Octet 6 8–15 Holds the sixth octet of the station address, which defaults to a value of 0x00. — Reserved. Write to zero for future compatibility. 16–31 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-91...
Page 862: Mii Management Registers
4. 010 BUSES_CLOCK/8 divided by 6. 011 BUSES_CLOCK/8 divided by 8. 100 BUSES_CLOCK/8 divided by 10. 101 BUSES_CLOCK/8 divided by 14. 110 BUSES_CLOCK/8 divided by 20. 111 BUSES_CLOCK/8 divided by 28. MSC8113 Reference Manual, Rev. 0 25-92 Freescale Semiconductor...
Page 863 Causes the MII management to perform a single read cycle. If RCYC is set, an MII management read cycle is performed using the PHY address at MIIMADD[PHYADDR] and the register address (at MIIMADD[RADDR]. The read data is returned in the MIIMSTATR[PHYS] bit. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-93...
Page 864: Mii Management Address Register
Reserved. Write to zero for future compatibility. 0–15 PHYC PHY Control 16–31 Causes an MII management write cycle to be performed using this 16-bit data field, the pre-configured PHY address at MIIMADD[PHYADDR]), and the register address (at MIIMADD[RADDR]). MSC8113 Reference Manual, Rev. 0 25-94 Freescale Semiconductor...
Page 865 BUSY Busy No read or write cycle. Indicates that an MII management block is performing an MII Read or write cycle is in management read or write cycle. progress. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-95...
Page 866: Miigsk Registers
MII PHY to be looped back to the Ethernet Ethernet controller transmit outputs. controller transmit outputs to the MII PHY. Proper operation is guaranteed only when: • MIIGSK_CFGR[IFMODE] = 00 • MIIGSK_CFGR[LBMODE] = 0 MSC8113 Reference Manual, Rev. 0 25-96 Freescale Semiconductor...
Page 867 Puts all Ethernet controller modules into reset. Internal Reset Note: MIIGSK_GPR is not reset by the Ethernet controller Internal Reset. — Reserved 30-28 Drive Strength Select slow drive Select standard pad drive strength. Select high drive MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-97...
Page 868 „ For the SMII MAC-to-MAC connection, the Ethernet controller is synchronized on the receive signal, and the receive and transmit operation proceeds according to the SYNC input sync signal, . In this mode, the generation of the transmit output signal is ETHSYNC_IN disabled. MSC8113 Reference Manual, Rev. 0 25-98 Freescale Semiconductor...
Page 869 You can write any value to these bits, but the SMII specification provides recommended status bit definitions. Note: MIIGSK_TIFBR can be programmed only when MIIGSK_ENR[EN] = 0, that is, the Ethernet controller is disabled. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-99...
Page 870 Part of the 10-bit data segments transferred in the inter-packet Forced error. gap between frames. Note: If the TX_EN bit = 1, this is data. If TX_EN = 0, this is a status bit. MSC8113 Reference Manual, Rev. 0 25-100 Freescale Semiconductor...
Page 871 Allows you to read the value of the received inter-frame 100 Mbps. segment bits. RXD0 IFG Receive Segment Data Bit 0 No previous RX error. Allows you to read the value of the received inter-frame RX error previous frame. segment bits. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-101...
Page 872 MIIGSK_IEVENT generates an interrupt if the corresponding bit in the MIIGSK_IMASK register is also set. The bit in MIIGSK_IEVENT is cleared if a 1 is written to that bit position. Writing a 0 has no effect. MSC8113 Reference Manual, Rev. 0 25-102 Freescale Semiconductor...
Page 873 In the interrupt handler, use the following steps: Disable all interrupts by clearing the MIIGSK_IEVENT register. Clear the IEVENT register. Update the MIIGSK_ERIFBR according to the expected value. Enable the desired interrupt in the MIIGSK_IMASK register. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-103...
Page 874 Interrupt 2 enabled. IE1EN Interrupt Event 1 Enable Interrupt 1 disabled. Enabled/disables interrupt event 1. Interrupt 1 enabled. IE0EN Interrupt Event 0 Enable Interrupt 0 disabled. Enabled/disables interrupt event 0. Interrupt 0 enabled. MSC8113 Reference Manual, Rev. 0 25-104 Freescale Semiconductor...
Page 875: Rmon Management Information Base (Mib)
TR64 Transmit and Receive 64-byte Frame Counter 10–31 Increments for each good or bad frame transmitted and received that is 64 bytes long, inclusive (excluding preamble and SFD but including FCS bytes). MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-105...
Page 876 Transmit and Receive 128- to 255-Byte Frame Counter 10–31 Increments for each good or bad frame transmitted and received that is 128 to 255 bytes long, inclusive (excluding preamble and SFD but including FCS bytes). MSC8113 Reference Manual, Rev. 0 25-106 Freescale Semiconductor...
Page 877 Transmit and Receive 512- to 1023-Byte Frame Counter 10–31 Increments for each good or bad frame transmitted and received that is 512 to 1023 bytes long, inclusive (excluding preamble and SFD but including FCS bytes). MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-107...
Page 878 Transmit and Receive 1519- to 1522-Byte Frame Counter 10–31 Increments for each good or bad frame transmitted and received that is 1519 to 1522 bytes long, inclusive (excluding Preamble and SFD but including FCS bytes). MSC8113 Reference Manual, Rev. 0 25-108 Freescale Semiconductor...
Page 879 Bits Reset Description — Reserved. Write to zero for future compatibility. 0–9 RPKT Receive Packet Counter 10–31 Increments for each frame received packet (including bad packets, all unicast, broadcast, and multicast packets). MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-109...
Page 880 0–9 RMCA Receive Multicast Packet Counter 10–31 Increments for each multicast good frame of lengths 64 to 1518 (non-VLAN) or 1522 (VLAN), excluding broadcast frames. This count does not include range/length errors. MSC8113 Reference Manual, Rev. 0 25-110 Freescale Semiconductor...
Page 881 Table 25-93. RXCF Bit Descriptions Bits Reset Description — Reserved. Write to zero for future compatibility. 0–15 RXCF Receive Control Frame Packet Counter 16–31 Increments for each MAC control frame received (PAUSE and unsupported). MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-111...
Page 882 — Reserved. Write to zero for future compatibility. 0–15 RXUO Receive Unknown Opcode Counter 16–31 Increments each time a MAC control frame is received that contains an opcode other than a pause. MSC8113 Reference Manual, Rev. 0 25-112 Freescale Semiconductor...
Page 883 Increments for each frame received in which the 802.3 length field does not match the number of data bytes actually received (46 –1500 bytes). The counter does not increment if the length field is not a valid 802.3 length, such as an ethertype value. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-113...
Page 884 Controllern_RXER and an 0xE on Ethernet Controllern_RXD. The event is reported along with the statistics generated on the next received frame. Only one false carrier condition can be detected and logged between frames. MSC8113 Reference Manual, Rev. 0 25-114 Freescale Semiconductor...
Page 885 Increments each time a frame is received that exceeds 1518 (non-VLAN) or 1522 (VLAN) and contains a valid FCS and is otherwise well formed. This count does not include range length errors. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-115...
Page 886 Reserved. Write to zero for future compatibility. 0–15 RJBR Receive Jabber Counter 16-31 Increments for frames received that exceed 1518 (non-VLAN) or 1522 (VLAN) bytes and contain an invalid FCS. This includes alignment errors. MSC8113 Reference Manual, Rev. 0 25-116 Freescale Semiconductor...
Page 887 Increments by the number of bytes that are put on the wire, including fragments of frames involved with collisions. This count does not include preamble/SFD or jam bytes.This counter does not count if the frame is a truncated frame MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-117...
Page 888 Table 25-107. TMCA Bit Descriptions Bits Reset Description — Reserved. Write to zero for future compatibility. 0–9 TMCA Transmit Multicast Packet Counter 10–31 Increments for each valid multicast frame transmitted, excluding broadcast frames. MSC8113 Reference Manual, Rev. 0 25-118 Freescale Semiconductor...
Page 889 Table 25-109. TXPF Bit Descriptions Bits Reset Description — Reserved. Write to zero for future compatibility. 0–15 TXPF Transmit Pause Frame Packet Counter 16–31 Increments each time a valid pause MAC control frame is transmitted. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-119...
Page 890 — Reserved. Write to zero for future compatibility. 0–19 TEDF Transmit Excessive Deferral Packet Counter 20–31 Increments for aborted frames that were deferred for an excessive period of time (3036 byte times). MSC8113 Reference Manual, Rev. 0 25-120 Freescale Semiconductor...
Page 891 Reserved. Write to zero for future compatibility. 0–19 TMCL Transmit Multiple Collision Packet Counter 20–31 Increments for each frame that experienced 2–15 collisions, including any late collisions, during transmission as defined by the HAFDUPR[RTXM] field. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-121...
Page 892 Bits Reset Description — Reserved. Write to zero for future compatibility. 0–19 TXCL Transmit Excessive Collision Packet Counter 20–31 Increments for each frame that experiences 16 collisions during transmission and is aborted. MSC8113 Reference Manual, Rev. 0 25-122 Freescale Semiconductor...
Page 893 Table 25-117. TJBR Bit Descriptions Bits Reset Description — Reserved. Write to zero for future compatibility. 0–19 TJBR Transmit Jabber Frame Counter 20–31 Increments for each oversized transmitted frame with an incorrect FCS value. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-123...
Page 894 — Reserved. Write to zero for future compatibility. 0–19 TXCF2 Transmit Control Frame Counter 0–31 Increments for every transmit frame with a valid size and a type field signifying a control frame. MSC8113 Reference Manual, Rev. 0 25-124 Freescale Semiconductor...
Page 895 Bits Reset Description — Reserved. Write to zero for future compatibility. 0–19 TDFR Transmit Undersize Frame Counter 20–31 Increments for every frame less than 64 bytes long with a correct FCS value. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-125...
Page 896 Carry Register 1 TR127 Counter Carry C1255 Carry Register 1 TR255 Counter Carry C1511 Carry Register 1 TR511 Counter Carry C11K Carry Register 1 TR1K Counter Carry C1MAX Carry Register 1 TRMAX Counter Carry MSC8113 Reference Manual, Rev. 0 25-126 Freescale Semiconductor...
Page 897 Carry Register 1 RJBR Counter Carry C1RDR Carry Register 1 RDRP Counter Carry CAR2 Carry Register Two — C2TJB C2TFCC2TCF C2TOV Type Reset C2TUN C2TFGC2TBY C2TPK C2TMC C2TBCC2TPF C2TDFC2TEDC2TSC C2TMA C2TLCC2TXC C2TNC — C2TDP Type Reset MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-127...
Page 898 Carry Register 2 TLCL Counter Carry C2TXC Carry Register 2 TXCL Counter Carry C2TNC Carry Register 2 TNCL Counter Carry — Reserved. Write to zero for future compatibility. C2TDP Carry Register 2 TDRP Counter Carry MSC8113 Reference Manual, Rev. 0 25-128 Freescale Semiconductor...
Page 899 M1RBC Mask Register 1 RBCA Counter Carry Mask M1RXC Mask Register 1 RXCF Counter Carry Mask M1RXP Mask Register 1 RXPF Counter Carry Mask M1RXU Mask Register 1 RXUO Counter Carry Mask MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-129...
Page 900 M2TJB Mask Register 2 TJBR Counter Carry Mask M2TFC Mask Register 2 TFCS Counter Carry Mask M2TXC Mask Register 2 TXCF Counter Carry Mask M2TOV Mask Register 2 TOVR Counter Carry Mask MSC8113 Reference Manual, Rev. 0 25-130 Freescale Semiconductor...
Page 901: Hash Function Registers
A hash entry usually represents a set of addresses. A hash table hit occurs if the DA CRC result points to an enabled hash entry. You should further filter the address. For details, see Section 25.9.3, Hash Table Algorithm, on page 25-27. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-131...
Page 902 256 entries. You can enable a hash entry by setting the appropriate bit. A hash table hit occurs if the DA CRC result points to an enabled hash entry. MSC8113 Reference Manual, Rev. 0 25-132...
Page 903: Pattern Matching Registers
Reset PMASKn is a set of user-programmable registers (bytes 0, 1, 2, 3) to mask a pattern match associated with the PMDn registers. Data is masked on a bit-by-bit basis, thus allowing MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-133...
Page 904 If a pattern match reject occurs, 256-byte maximum. CSE is ignored (the frame is rejected and searching is discontinued). MSC8113 Reference Manual, Rev. 0 25-134 Freescale Semiconductor...
Page 905 Specifies which field is used to determine where determine where the frame is filed. the frame is filled. If a match occurs, the PATTRB[QC] field is used to determine where the frame is filed. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-135...
Page 906 DATTR. You must ensure that this override does not happen inadvertently. For a snoop enable bit, for example, the PATTRBn[RBDSEN] and PATTRBn[RDSEN] should match the corresponding DATTR fields unless you want to file to the default queue with a different snoop MSC8113 Reference Manual, Rev. 0 25-136 Freescale Semiconductor...
Page 907: Data Structures (Buffer Descriptors)
MIB block. TxBD 8-Byte Transmit Data Buffer Descriptor Offset + PADCRC HFELC 0x00 Offset + Data Length (DL) 0x02 Offset + Tx Data Buffer Pointer 0x04 Offset + 0x06 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-137...
Page 908 Hardware updates this bit after transmitting a frame frame did not have a collision before it (TxBD[L] is set. was sent but it was sent late because of deferring. If HAFDUP[EXCESS_DEFER]=0, this frame was aborted and not sent. MSC8113 Reference Manual, Rev. 0 25-138 Freescale Semiconductor...
Page 909 There are no alignment requirements for this address. TxBD 32-Byte Transmit Data Buffer Descriptor Offset + PADCRC HFE/LC 0x00 Offset + Data Length (DL) 0x02 Offset + Reserved 0x04 Offset + 0x06 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-139...
Page 910 The 32-byte TxBD is an extended version of the 8-byte TxBD. It supports insertion of data on a per-buffer descriptor basis, either insertion with replacement or insertion with expansion. Software programs the right TYPE/LENGTH field in the BD to take into account any inserted data. MSC8113 Reference Manual, Rev. 0 25-140 Freescale Semiconductor...
Page 911 Hardware updates this bit after transmitting a frame this frame did not have a collision (TxBD[L] is set. before it was sent but it was sent late because of deferring. If HAFDUP[EXCESS_DEFER]=0, this frame was aborted and not sent. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-141...
Page 912 TXDBPT Transmit Data Buffer Pointer 0–31 Contains the address of the associated data buffer. There are no alignment requirements for this address. +0x12 — Reserved. Write to zero for future compatibility. 0–31 MSC8113 Reference Manual, Rev. 0 25-142 Freescale Semiconductor...
Page 913 Tx insert buffer pointer and the Insert Index field are considered invalid. The Ethernet controller never modifies this value. +0x28 — Reserved. Write to zero for future compatibility. 0–15 + 0x30 — Reserved. Write to zero for future compatibility. 0–15 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-143...
Page 914 The buffer is not the last in a Specifies whether this buffer is the last one in the receive frame. frame. This bit is written by the Ethernet controller. The buffer is the last in a frame. MSC8113 Reference Manual, Rev. 0 25-144 Freescale Semiconductor...
Page 915 Receive frame truncated. discarded and the other error bits must be ignored because they may be incorrect. This bit is written by the Ethernet controller and is valid only if L is set. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-145...
Page 916 Offset + 0x14 Offset + Reserved 0x16 Offset + 0x18 Offset + 0x20 Offset + Reserved 0x22 Offset + 0x24 Offset + x026 Offset + Reserved x028 Offset + Byte Count 0x30 MSC8113 Reference Manual, Rev. 0 25-146 Freescale Semiconductor...
Page 917 + 0x00 Broadcast Normal operation. Broadcast mode. This bit is written by Ethernet Broadcast mode. controller and is valid only if L is set. L is set if the DA is broadcast (FF-FF-FF-FF-FF-FF). MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-147...
Page 918 Points to the first location of the associated data buffer and must be 64-byte aligned. The buffer must + 0x10 0–31 reside in memory external to the Ethernet controller. This field is written by the user. MSC8113 Reference Manual, Rev. 0 25-148 Freescale Semiconductor...
Page 919 Rx buffer pointer points, regardless of the L bit value. With the exception of the last BD (L is set), the data length and the byte count are always the same.This field is written by the Ethernet controller. MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor 25-149...
Page 920 Ethernet Controller MSC8113 Reference Manual, Rev. 0 25-150 Freescale Semiconductor...
Page 921: Programming Reference
MSC8113 registers. A.1 Register Addressing Register addressing is complex because of the flexible addressing model offered in the MSC8113 device. SC140 DSP core and extended core registers are shown on programming sheets with fixed addresses based on the default QBus bank configurations after reset and booting. While the QBus base addresses can be reconfigured, this is not recommended.
Page 922 Programming Reference A.2 Interrupts For information on the MSC8113 interrupt controllers, refer to Chapter 17, Interrupt Processing. The following tables are a summary of interrupt sources for each of the controllers. Table A-1. GIC INT_OUT Sources Source Description — Reserved —...
Page 923: Interrupts
TDM3 Transmit Second Threshold Event TDM3TFTE TDM3 Transmit First Threshold Event DMA global interrupt (sum of all channel interrupts) DMA_ERROR DMA error — Reserved — Reserved — Reserved — Reserved — Reserved — Reserved MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 924 Virtual Interrupt Number 4 VIRQ5 Virtual Interrupt Number 5 VIRQ6 Virtual Interrupt Number 6 VIRQ7 Virtual Interrupt Number 7 IRQ4 IRQ4 signal (global) IRQ5 IRQ5 signal (global) IRQ6 IRQ6 signal (global) IRQ7 IRQ7 signal (global) MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 925 Virtual Interrupt Number 12 VIRQ13 Virtual Interrupt Number 13 VIRQ14 Virtual Interrupt Number 14 VIRQ15 Virtual Interrupt Number 15 IRQ4 IRQ4 signal (global) IRQ5 IRQ5 signal (global) IRQ6 IRQ6 signal (global) IRQ7 IRQ7 signal (global) MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 926 Virtual Interrupt Number 20 VIRQ21 Virtual Interrupt Number 21 VIRQ22 Virtual Interrupt Number 22 VIRQ23 Virtual Interrupt Number 23 IRQ4 IRQ4 signal (global) IRQ5 IRQ5 signal (global) IRQ6 IRQ6 signal (global) IRQ7 IRQ7 signal (global) MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 927 Interrupts Table A-6. MSC8113 Interrupt Routing Service Routine VAB[0–5] Signal Description Address (Offset from VBA) TRAP Internal exception (generated by trap instruction) — Reserved 0x40 ILLEGAL Illegal instruction or set 0x80 DEBUG Debug exception (EOnCE) 0xC0 — Reserved 0x100 OVERFLOW...
Page 928: Programming Sheets
For details on the instruction set of the SC140 core, see the SC140 DSP Core Reference Manual, which is available at the web site listed on the back cover of this manual. Table A-7. Guide to MSC8113 Programming Sheets Module Programming Sheet...
Page 929 Programming Sheets Table A-7. Guide to MSC8113 Programming Sheets (Continued) Module Programming Sheet Type Page System Bus Configuration Register (BCR) page A-24 Interface Unit System Bus Arbiter Configuration Register (PPC_ACR) page A-25 (SIU) System Bus Arbitration-Level Registers (PPC_ALRH/PPC_ALRL) page A-26...
Page 930 Programming Reference Table A-7. Guide to MSC8113 Programming Sheets (Continued) Module Programming Sheet Type Page Interrupt Virtual Interrupt Generation Register (VIGR) page A-49 Controllers Virtual Interrupt Status Register (VISR) page A-49 Virtual NMI Generation Register (VNMIGR) page A-50 GIC Interrupt Configuration Register (GICR)
Page 931 Programming Sheets Table A-7. Guide to MSC8113 Programming Sheets (Continued) Module Programming Sheet Type Page Direct Slave DSI Control Register (DCR) page A-69 Interface (DSI) DSI Sliding Window Base Address Register (DSWBAR) page A-70 DSI Internal Base Address Registers (DIBAR[9, 11])
Page 932 Programming Reference Table A-7. Guide to MSC8113 Programming Sheets (Continued) Module Programming Sheet Type Page UART SCI Baud-Rate Register (SCIBR) page A-89 SCI Data Register (SCIDR) page A-89 SCI Data Direction Register (SCIDDR) page A-89 SCI Control Register (SCICR) page A-90...
Page 933 Programming Sheets Table A-7. Guide to MSC8113 Programming Sheets (Continued) Module Programming Sheet Type Page Ethernet FIFO Transmit Starve Register (FTXSR) page A-110 Controller FIFO Transmit Starve Shutoff Register (FTXSSR) page A-110 (cont.) Transmit Control Register (TCTRL) page A-111 Transmit Status Register (TSTAT)
Page 934 Programming Reference Table A-7. Guide to MSC8113 Programming Sheets (Continued) Module Programming Sheet Type Page Ethernet MIIGSK General-Purpose Register (MIIGSK_GPR) page A-131 Controller MIIGSK Enable Register (MIIGSK_ENR) page A-132 (cont.) MIIGSK SMII SYNC Direction Register (MIIGSK_SMII_SYNCDIR) page A-132 MIIGSK Transmit Inter-Frame Bits Register (MIIGSK_TIFBR)
Page 935 Programming Sheets Table A-7. Guide to MSC8113 Programming Sheets (Continued) Module Programming Sheet Type Page Ethernet Transmit Deferral Packet Counter (TDFR) page A-149 Controller Transmit Excessive Deferral Packet Counter (TEDF) page A-150 (cont.) Transmit Single Collision Packet Counter (TSCL) page A-150...
Page 936 Programming Reference SRSR MSC8113 Reference Manual, Rev. 0 A-16 Freescale Semiconductor...
Page 937 Programming Sheets MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor A-17...
Page 938 Programming Reference QBUSBR[0–2] QBUSMR[1–2] MSC8113 Reference Manual, Rev. 0 A-18 Freescale Semiconductor...
Page 939 Programming Sheets ICACR ICABR MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor A-19...
Page 940 Programming Reference IFUR WBCR MSC8113 Reference Manual, Rev. 0 A-20 Freescale Semiconductor...
Page 941 Programming Sheets DBR[0–3] FLBACR0 GPR1 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor A-21...
Page 942 Programming Reference HRCW MSC8113 Reference Manual, Rev. 0 A-22 Freescale Semiconductor...
Page 943 Programming Sheets MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor A-23...
Page 944 Programming Reference MSC8113 Reference Manual, Rev. 0 A-24 Freescale Semiconductor...
Page 945 Programming Sheets PPC_ACR MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor A-25...
Page 946 Programming Reference PPC_ALRH PPC_ALRL MSC8113 Reference Manual, Rev. 0 A-26 Freescale Semiconductor...
Page 947 Programming Sheets LCL_ACR MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor A-27...
Page 948 Programming Reference LCL_ALRH LCL_ALRL MSC8113 Reference Manual, Rev. 0 A-28 Freescale Semiconductor...
Page 949 Programming Sheets SIUMCR, p. 1 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor A-29...
Page 950 Programming Reference SIUMCR, p. 2 MSC8113 Reference Manual, Rev. 0 A-30 Freescale Semiconductor...
Page 951 Programming Sheets IMMR MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor A-31...
Page 952 Programming Reference SYPCR MSC8113 Reference Manual, Rev. 0 A-32 Freescale Semiconductor...
Page 953 Programming Sheets SWSR MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor A-33...
Page 954 Programming Reference TESCR1 MSC8113 Reference Manual, Rev. 0 A-34 Freescale Semiconductor...
Page 955 Programming Sheets TESCR2 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor A-35...
Page 956 Programming Reference L_TESCR1 MSC8113 Reference Manual, Rev. 0 A-36 Freescale Semiconductor...
Page 957 Programming Sheets TMCNTSC MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor A-37...
Page 958 Programming Reference TMCNT TMCNTAL MSC8113 Reference Manual, Rev. 0 A-38 Freescale Semiconductor...
Page 959 Programming Sheets PISCR PITC MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor A-39...
Page 960 Programming Reference BR[0–7, 9–11] MSC8113 Reference Manual, Rev. 0 A-40 Freescale Semiconductor...
Page 961 Programming Sheets OR[0–7, 9–11], GPCM MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor A-41...
Page 962 Programming Reference OR[0–7, 9–11], SDRAM MSC8113 Reference Manual, Rev. 0 A-42 Freescale Semiconductor...
Page 963 Programming Sheets OR[0–7, 9–11], MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor A-43...
Page 964 Programming Reference MAMR, MBMR, MCMR MSC8113 Reference Manual, Rev. 0 A-44 Freescale Semiconductor...
Page 965 Programming Sheets PSDMR, p. 1 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor A-45...
Page 966 Programming Reference PSDMR, p. 2 MSC8113 Reference Manual, Rev. 0 A-46 Freescale Semiconductor...
Page 967 Programming Sheets MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor A-47...
Page 968 Programming Reference PURT PSRT MPTPR MSC8113 Reference Manual, Rev. 0 A-48 Freescale Semiconductor...
Page 969 Programming Sheets VIGR VISR MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor A-49...
Page 970 Programming Reference VNMIGR GICR MSC8113 Reference Manual, Rev. 0 A-50 Freescale Semiconductor...
Page 971 Programming Sheets GEIER MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor A-51...
Page 972 Programming Reference GCIER GISR MSC8113 Reference Manual, Rev. 0 A-52 Freescale Semiconductor...
Page 973 Programming Sheets LICAICR[0–3] MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor A-53...
Page 974 Programming Reference LICBICR[0–3] MSC8113 Reference Manual, Rev. 0 A-54 Freescale Semiconductor...
Page 975 Programming Sheets LICAIER/LICBIER LICAISR/LICBISR LICAIESR/LICBIES MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor A-55...
Page 976 Programming Reference ELIRA ELIRB MSC8113 Reference Manual, Rev. 0 A-56 Freescale Semiconductor...
Page 977 Programming Sheets ELIRC ELIRD MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor A-57...
Page 978 Programming Reference ELIRE ELIRF MSC8113 Reference Manual, Rev. 0 A-58 Freescale Semiconductor...
Page 979 Programming Sheets IPRA IPRB MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor A-59...
Page 980 Programming Reference ICCR ICCMR MSC8113 Reference Manual, Rev. 0 A-60 Freescale Semiconductor...
Page 981 Programming Sheets DCHCR[0–15], p. 1 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor A-61...
Page 982 Programming Reference DCHCR[0–15] MSC8113 Reference Manual, Rev. 0 A-62 Freescale Semiconductor...
Page 983 Programming Sheets DCPR DSTR MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor A-63...
Page 984 Programming Reference DCPRAM MSC8113 Reference Manual, Rev. 0 A-64 Freescale Semiconductor...
Page 985 Programming Sheets BD_ATTR, p. 1 MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor A-65...
Page 986 Programming Reference BD_ATTR MSC8113 Reference Manual, Rev. 0 A-66 Freescale Semiconductor...
Page 987 Programming Sheets DIMR DEMR MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor A-67...
Page 988 Programming Reference DTEAR MSC8113 Reference Manual, Rev. 0 A-68 Freescale Semiconductor...
Page 989 Programming Sheets MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor A-69...
Page 990 Programming Reference DSWBAR DIBAR[9–11] DIAMR[9–11] MSC8113 Reference Manual, Rev. 0 A-70 Freescale Semiconductor...
Page 991 Programming Sheets DCIR MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor A-71...
Page 992 Programming Reference MSC8113 Reference Manual, Rev. 0 A-72 Freescale Semiconductor...
Page 993 Programming Sheets HSMPR[0–7] MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor A-73...
Page 994 Programming Reference TDM[0–3]GIR MSC8113 Reference Manual, Rev. 0 A-74 Freescale Semiconductor...
Page 995 Programming Sheets TDM[0–3]RIR MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor A-75...
Page 996 Programming Reference TDM[0–3]TIR MSC8113 Reference Manual, Rev. 0 A-76 Freescale Semiconductor...
Page 997 Programming Sheets TDM[0–3]RFP MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor A-77...
Page 998 Programming Reference TDM[0–3]TFP MSC8113 Reference Manual, Rev. 0 A-78 Freescale Semiconductor...
Page 999 Programming Sheets TDM[0–3]RDBS TDM[0–3]TDBS MSC8113 Reference Manual, Rev. 0 Freescale Semiconductor A-79...
Page 1000 Programming Reference TDM[0–3]RGBA TDM[0–3]TGBA MSC8113 Reference Manual, Rev. 0 A-80 Freescale Semiconductor...