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System Integration Module (SIM) 13.1 Introduction...................................197 13.1.1 Features................................ 197 13.2 Memory map and register definition..........................198 13.2.1 System Options Register 1 (SIM_SOPT1)....................199 13.2.2 System Options Register 2 (SIM_SOPT2)....................200 KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Chip-specific Information for this Module........................227 14.1.1 Kinetis Flashloader............................227 14.2 Introduction...................................228 14.3 Functional Description..............................229 14.3.1 Memory Maps.............................. 229 14.3.2 Start-up Process............................229 14.3.3 Clock Configuration.............................232 14.3.4 Flashloader Protocol............................ 232 KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Introduction...................................291 16.2 Modes of operation............................... 291 16.3 Memory map and register descriptions.........................293 16.3.1 Power Mode Protection register (SMC_PMPROT)..................294 16.3.2 Power Mode Control register (SMC_PMCTRL)..................295 16.3.3 Stop Control Register (SMC_STOPCTRL)....................297 KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Regulator Status And Control register (PMC_REGSC)................317 17.6.4 High Voltage Detect Status And Control 1 register (PMC_HVDSC1)............319 Chapter 18 Low-Leakage Wakeup Unit (LLWU) 18.1 Chip-specific Information for this Module........................321 18.1.1 Wake-up Sources............................321 KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Watchdog Reset Count register (WDOG_RSTCNT).................. 494 25.8.12 Watchdog Prescaler register (WDOG_PRESC)..................494 25.9 Watchdog operation with 8-bit access.......................... 494 25.9.1 General guideline............................494 25.9.2 Refresh and unlock operations with 8-bit access..................495 KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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MCG Control 12 Register (MCG_C12).......................517 26.4.13 MCG Status 2 Register (MCG_S2)......................517 26.4.13 MCG Test 3 Register (MCG_T3)........................ 518 26.5 Functional description..............................518 26.5.1 MCG mode state diagram..........................518 26.5.2 Low-power bit usage............................522 KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
• Chip-specific: The first section, Chip-specific [module name] information, includes the number of module instances on the chip and possible implementation differences between the module instances, such as differences in FIFO depths or the number of KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
• LIN Specification Package Revision 1.3; December 12, 2002 • LIN Specification Package Revision 2.0; September 23, 2003 Sample Reference Manual Figure 1-1. Example: chapter chip-specific information and general module information KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
1.3.2 Example: chip-specific information that refers to a different chapter The chip-specific information below refers to another chapter's chip-specific information. In this case, read both sets of chip-specific information before reading further in the chapter. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
• The page number on which each register is described • Register figures • Field-description tables • Associated text The register figures show the field structure using the conventions in the following figure. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Fixed-width type indicates text that must be typed exactly as shown. It is used for instruction mnemonics, directives, symbols, subcommands, parameters, and operators. Fixed-width type Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
• Consider undefined locations in memory to be reserved. Write 1 to clear: Refers to a register bitfield that must be written as 1 to be "cleared." KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Memory protection unit (MPU) Cache Interrupt controller Direct memory access (DMA) 16 channels DMA request multiplex Non-maskable interrupt (NMI) Software watchdog Hardware watchdog Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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External square wave input clock DC to 50 MHz Internal clock references 32 kHz oscillator 4 MHz oscillator 1 kHz oscillator 48 MHz Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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2 channels with DMA support Functional in Stop/VLPS mode 16-bit low-power timer PWM modules(TPM2) 2 channels with DMA support Functional in Stop/VLPS mode Ethernet 1588 Timer Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Higher Baud Rates (CPU clock) UART 1-2 Hardware flow control IrDA Higher Baud Rates on UART1 (CPU clock) Secure Digital (SD) interface Synchronous Audio interface (SAI) Inter-IC Sound (I2S) AC'97 support KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Includes power- on-reset (POR) and integrated low voltage detect (LVD)/high voltage detect (HVD) with reset (brownout) capability and selectable LVD/HVD trip points. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
VBAT register file 32-byte register file that is accessible during all power modes and is powered by VBAT. 2.4.4 Clocks The following clock modules are available on this device. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
12-bit digital-to-analog converters (DAC) Low-power general-purpose DAC, whose output can be placed on an external pin or set as one of the inputs to the analog comparator or ADC. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
• 32-bit seconds counter with 32-bit Alarm • 16-bit Prescaler with compensation that can correct errors between 0.12 ppm and 3906 ppm 2.4.8 Communication interfaces The following communication interfaces are available on this device: KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
All general purpose input or output (GPIO) pins are capable of interrupt and DMA request generation. All GPIO pins have 3.3 V tolerance. 2.5 Orderable part numbers The following table summarizes the part numbers of the devices covered by this document. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
SysTick Calibration Value Register is always zero. • The NOREF bit in SysTick Calibration Value Register is always set, implying that FCLK is the only available source of reference timing. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
ARM Cortex-M4 Technical Reference Manual Interrupt Controller (NVIC) System memory map System memory map Clocking Clock distribution Power management Power management Private Peripheral Bus ARM Cortex-M4 core ARM Cortex-M4 core (PPB) KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
– – – ARM core MemManage Fault 0x0000_0014 – – – ARM core Bus Fault 0x0000_0018 – – – ARM core Usage Fault Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Low Leakage Wakeup NOTE: The LLWU interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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2. Indicates the NVIC's ISER, ICER, ISPR, ICPR, and IABR register number used for this IRQ. The equation to calculate this value is: IRQ div 32 3. Indicates the NVIC's IPR register number used for this IRQ. The equation to calculate this value is: IRQ div 4 KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
3.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at arm.com. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
UART Active edge on RXD LPUART Functional when using clock source which is active in Stop and VLPS modes USB FS/LS Controller Wakeup Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Power Management Transfers ARM Cortex M4 core ARM Cortex-M4 core Private Peripheral Bus (PPB) 3.5 JTAG Controller Configuration This section summarizes how the module has been configured in the chip. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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JTAG controller cJTAG multiplexing Figure 3-5. JTAGC Controller configuration Table 3-9. Reference links to related information Topic Related module Reference Full description JTAGC JTAGC Signal multiplexing Port control Signal multiplexing KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Peripheral bridge Peripheral bridge 4.1.1 Flash memory types This device contains the following types of flash memory: • Program flash memory — non-volatile flash memory that can execute program code KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
SWJ-DP debug port by setting DAP_CONTROL[0]. DAP_STATUS[0] is set to indicate the mass erase command has been accepted. DAP_STATUS[0] is cleared when the mass erase completes. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
The Flash Memory Controller supports up to eight crossbar switch masters. However, this device has a different number of crossbar switch masters. See Crossbar Switch Configuration for details on the master port assignments. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Misaligned accesses across the 0x2000_0000 boundary are not supported in the ARM Cortex-M4 architecture. The amount of SRAM for the devices covered in this document is shown in the following table. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Table 4-4. Reference links to related information Topic Related module Reference Full description Register file Register file System memory map System memory map Clocking Clock distribution Power management Power management KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
VBAT. The VBAT Register file is made up of eight 4-byte registers RFVBAT_REGn, where n ranges from 0 to 7. It is only reset during VBAT power-on reset. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Table 5-1. System memory map System 32-bit Address Range Destination Slave Access 0x0000_0000–0x07FF_FFFF Program flash and read-only data All masters Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
1. Access rights to AIPS-Lite peripheral bridge and general purpose input/output (GPIO) module address space is limited to the core, DMA . 2. ARM Cortex-M4 core access privileges also includes accesses via the debug interface. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Figure 5-1. Alias bit-band mapping NOTE Each bit in bit-band region has an equivalent bit that can be manipulated through bit 0 in a corresponding long word in the alias bit-band region. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
The base address for each is specified in System memory map. Flash memory base address Registers Program flash base address Flash configuration field Program flash Figure 5-2. Flash memory map KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Accesses to the SRAM_L and SRAM_U memory ranges outside the amount of RAM on the device causes the bus cycle to be terminated with an error followed by the appropriate response in the requesting bus master. 5.5 Peripheral bridge (AIPS-Lite) memory map KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
5.5.2 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map Table 5-2. Peripheral bridge 0 slot assignments System 32-bit base address Slot Module number 0x4000_0000 — 0x4000_1000 — 0x4000_2000 — Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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— 0x4002_3000 — 0x4002_4000 FlexCAN 0 0x4002_5000 FlexCAN 1 (only for KS22) 0x4002_6000 — 0x4002_7000 — 0x4002_8000 — 0x4002_9000 Random Number Generator (RNGA) Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Port B multiplexing control 0x4004_B000 Port C multiplexing control 0x4004_C000 Port D multiplexing control 0x4004_D000 Port E multiplexing control 0x4004_E000 — 0x4004_F000 — 0x4005_0000 — Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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0x4007_1000 — 0x4007_2000 USB OTG FS/LS 0x4007_3000 Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) 0x4007_4000 — 0x4007_5000 — 0x4007_6000 — 0x4007_7000 — Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
SIM module. Reference those sections for detailed register and bit descriptions. 6.3 High-Level device clocking diagram The following system oscillator, MCG, and module registers control the multiplexers, dividers, and clock gates shown in the below figure: KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Note: See subsequent sections for details on where these clocks are used. Figure 6-1. Clocking diagram 6.4 Clock definitions The following table describes the clocks in the previous block diagram. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Up to 120 MHz Up to 120 MHz Up to 4 MHz In all stop modes except for partial stop modes and during PLL locking when Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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30-40 kHz 30-40 kHz 30-40 kHz System OSC or System OSC's 32kHz LPO or RTC OSC OSC_CR[ERCLKE depending on N] cleared (ERCLK32K) SIM_SOPT1[OSC3 2KSEL] Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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MCGOUTCLK LPUART0 clock Up to 120MHz Up to 100MHz Up to 16MHz MCGPLLCLK or LPUART0 is disabled MCGFLLCLK or IRC48MCLK or MCGIRCLK or Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
3. The flash clock frequency must be programmed to 26.67 MHz or less, less than or equal to the bus clock, and an integer divide of the core clock. The core clock to flash clock ratio is limited to a max value of 8. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
This gives the user flexibility for a lower frequency, low-power boot option. The flash erased state defaults to fast clocking mode, since where the low power boot (FTF_FOPT[LPBOOT]) bit resides in flash is logic 1 in the flash erased state. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
The following table summarizes the clocks associated with each module. Table 6-2. Module clocks Module Bus interface clock Internal clocks I/O interface clocks Core modules Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Timers Bus clock TPM clock TPM_CLKIN0, TPM_CLKIN1 Bus clock — — Bus clock — — LPTMR Flash clock LPO, OSCERCLK, — MCGIRCLK, ERCLK32K Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
IRC48MCLK is not forced disabled in VLPR and should be disabled by software prior to VLPR entry. IRC48MCLK is enabled via any of the following control settings while operating in these modes: KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
• clock source for FlexIO communications • clock source for LPI2C communications 6.7.3 WDOG clocking The WDOG may be clocked from two clock sources as shown in the following figure. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
The digital filters in can be clocked as shown in the following figure. NOTE In stop mode, the digital input filters are bypassed unless they are configured to run from the 1 kHz LPO clock source. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
When the RTC is enabled, the RTC_CLKOUT signal can be configured to drive to an external pin via the associated pin muxing control, as shown below. NOTE RTC_CLKOUT is disabled in LLSx and VLLSx modes. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
For the USB FS OTG controller to operate, the minimum system clock frequency is 20 MHz. The USB OTG controller also requires a 48 MHz clock. The clock source options are shown below. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
The LPUART0 module has a selectable clock as shown in the following figure. NOTE The chosen clock must remain enabled if the LPUART0 is to continue operating in all required low-power modes. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
The transmitter and receiver can independently select between the bus clock and the audio master clocks to generate the bit clock. The MCLK and BCLK source options appear in the following figure. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
The chosen clock must remain enabled if FlexIO is to continue operation in required low-power modes. 6.7.13 LPI2C clocking Each LPI2C module has a selectable clock as shown in the following figure. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
6.7.15 FlexCAN clocking The clock for the FlexCAN's protocol engine can be selected as shown in the following figure. OSCERCLK FlexCAN clock Bus clock CANx_CTRL1[CLKSRC] Figure 6-13. FlexCAN clock generation KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
7.2 Reset This section discusses basic reset mechanisms and sources. Some modules that cause resets can be configured to cause interrupts instead. Consult the individual peripheral chapters for more information. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
• TDO with no pull-down or pull-up Note that the nTRST signal is initially configured as disabled, however once configured to its JTAG functionality its associated input pin is configured as: • nTRST in PU KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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The RCM's SRS0[LVD] bit is set following either an LVD reset or POR. The HVD function is quite similar to the LVD, and shares the same RCM status bitfield (RCM_SRS[LVD]). For more details, see HVD reset operation. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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MCG module, the MCU resets. The RCM's SRS0[LOC] bit is set to indicate this reset source. NOTE To prevent unexpected loss of clock reset events, all clock monitors should be disabled before entering any low power modes, including VLPR and VLPW. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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The LOCKUP condition causes a system reset and also causes the RCM's SRS1[LOCKUP] bit to set. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
The Chip POR asserts on POR, LVD, and VLLS Wakeup reset sources. It resets the Reset Pin Filter registers and parts of the SIM and MCG. The Chip POR also causes the Chip Reset (including Early Chip Reset) to occur. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Reset negates after the RESET pin is pulled high. Keeping the RESET pin asserted externally delays the negation of the internal Chip Reset. 7.2.5 Debug resets The following sections detail the debug resets available on the device. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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• Crossbar bus switch • AHB-AP • Private peripheral bus 1. CDBGRSTREQ does not affect AHB resources so that debug resources on the private peripheral bus are available during System Reset. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Table 7-2. Flash Option Register Bit Definitions Field Value Definition Reserved Reserved for future expansion. FAST_INIT Select initialization speed on POR, VLLSx, and any system reset. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
3. The system reset on internal logic continues to be held, but the Flash Controller is released from reset and begins initialization operation while the Reset Control logic continues to drive the RESET pin out low. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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NMI interrupt. The processor executes an Exception Entry and reads the NMI interrupt handler address from vector-table offset 8. The CPU begins execution at the NMI interrupt handler. Subsequent system resets follow this same reset flow. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
If configured, a DMA request (using the asynchronous DMA wakeup) can also be used to exit Partial Stop for the duration of a DMA transfer before the device is transitioned back into PSTOP2. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Stop mode and then requesting bus slaves to enter Stop mode. In STOP and VLPS modes, MCG and PMC would then also enter their appropriate modes. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
VLPS mode. The MCG, PMC, SRAM and Flash read port are not affected by Compute Operation, although the Flash register interface is disabled. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
• The CPU is in Stop mode, including the entry sequence and for the duration of a DMA wakeup. • The CPU is in Compute Operation, including the entry sequence and for the duration of a DMA wakeup. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Stop mode entry is not supported directly from HSRUN and requires transition to Run prior to an attempt to enter a stop mode. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Sleep Deep Wakeup Reset Low Leakage LPTimer, RTC, CMP, DAC can be used. NVIC is disabled; LLWU is Stop3) used to wake up. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Recovery from VLLSx is through the wake-up Reset event. The chip wake-ups from VLLSx by means of reset, an enabled pin or enabled module. See the table "LLWU inputs" in the LLWU configuration section for a list of the sources. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
VLPR and VLPW are limited in frequency. The LLS and VLLSx mode(s) are the lowest power stop modes based on amount of logic or memory that is required to be retained by the application. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
• System level wait and VLPW modes equate to: SLEEPING & SLEEPDEEP • All other low power modes equate to: SLEEPING & SLEEPDEEP When entering the non-wait modes, the chip performs the following sequence: KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
• static = Module register states and associated memories are retained. • powered = Memory is powered to retain contents. • low power = Memory is powered to retain contents in a lower power state KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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4 MHz max 4 MHz max OFF in CPO Bus clock 4 MHz max 4 MHz max OFF in CPO MHz max in PSTOP2 from Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Async operation FF with external static with external clock Async operation clock in CPO FF in PSTOP2 FlexIO Async operation Async operation static Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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5. Use an externally generated bit clock or an externally generated audio master clock (including EXTAL). 6. System OSC and LPO clock sources are not available in VLLS0. Pulse counting is available in all modes. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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VLLSx only supports low speed external pin to pin or external pin to DAC compares. Windowed, sampled & filtered modes of operation are not available while in stop, VLPS, LLSx, or VLLSx modes. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
(FSEC[SEC] = 00, 01, or 11), programmer interfaces are only allowed to launch mass erase operations and have no access to memory locations. Further information regarding the flash security options and enabling/disabling flash security is available in the Flash Memory Module. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Blocks) command. A mass erase via the debugger is allowed even when some memory locations are protected. When mass erase is disabled, mass erase via the debugger is blocked. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Singlestep, Register Access, Run, Core Status S/W Instrumentation Messaging + Simple Data Trace Messaging + Watchpoint Messaging DWT (Data and Address Watchpoints) 4 data and address watchpoints Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
• ARM Debug Interface v5.1 • ARM CoreSight Architecture Specification 10.2 The Debug Port The configuration of the cJTAG module, JTAG controller, and debug port is illustrated in the following figure: KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
3. Send more than 50 TCK cycles with TMS (SWDIO) =1 NOTE See the ARM documentation for the CoreSight DAP Lite for restrictions. 10.2.2 JTAG-to-cJTAG change sequence 1. Reset the debug port KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
TAPs (TDO) are muxed based on the IR code which is selected. This design is fully JTAG compliant and appears to the JTAG chain as a single TAP. At power on reset, ARM's IDCODE (IR=4'b1110) is selected. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
JTAG, cJTAG, or SWD. The MDM-AP is accessible as Debug Access Port 1 with the available registers shown in the table below. Table 10-4. MDM-AP Register Summary Address Register Description 0x0100_0000 Status MDM-AP Status Register Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Table 10-5. MDM-AP Control register assignments Name Secure Description Flash Mass Erase in Progress Set to cause mass erase. Cleared by hardware after mass erase operation completes. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
This bit is used by the debugger to clear the sticky LLS and VLLSx mode entry status bits. This bit is asserted and cleared by the debugger. 1. Command available in secure mode KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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LLS was exited and is cleared by a write of 1 to the LLS, VLLSx Status Acknowledge bit in MDM AP Control register. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
• SYSRESETREQ bit in the NVIC application interrupt and reset control register • A system reset in the DAP control register which allows the debugger to hold the Core in reset. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
21-bit counter to generate the timestamp. The Cortex-M4 clock or the bitclock rate of the Serial Wire Viewer (SWV) output clocks the counter. 4. Global system timestamping. Timestamps can optionally be generated using a system-wide 48-bit count value. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
NOTE An event is emitted each time a counter overflows. • The DWT can be configured to emit PC samples at defined intervals, and to emit interrupt event information. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
• FF = Full functionality. In VLPR and VLPW the system frequency is limited, but if a module does not have a limitation in its functionality, it is still listed as FF. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
When mass erase is disabled (FSEC[MEEN]= 10), the debugger does not have the capability of performing a mass erase operation via writes to MDM-AP Control Register. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous "signal multiplexing and pin assignments" section. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
11.3 Module Signal Description Tables The following sections correlate the chip-level signal name with the signal name used in the module's chapter. They also briefly describe the signal function and direction. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
EWM input for safety status of external safety circuits. The polarity of EWM_in is programmable using the EWM_CTRL[ASSIN] bit. The default polarity is active-low. EWM_OUT EWM_out EWM reset out signal KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Module signal Description name CMP0_IN[5:0] IN[5:0] Analog voltage inputs CMP0_OUT CMPO Comparator output Table 11-9. DAC 0 Signal Descriptions Chip signal name Module signal Description name DAC0_OUT — DAC output KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
TPM channel (n = 5 to 0). A TPM channel pin is configured as output when configured in an output compare or PWM mode and the TPM counter is enabled, otherwise the TPM channel pin is an input. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
CAN Transmit Pin Output Table 11-19. SPI 0 Signal Descriptions Chip signal name Module signal Description name SPI0_PCS0 PCS0/SS Peripheral Chip Select 0 (O) Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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I2C bus is idle. LPI2C1_SCLS SCLS Secondary I2C clock line. If LPI2C master/slave are configured to use separate pins, this the LPI2C slave SCL pin. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Receive data Table 11-26. UART 2 Signal Descriptions Chip signal name Module signal Description name UART2_CTS Clear to send UART2_RTS Request to send UART2_TX Transmit data UART2_RX Receive data KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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I2S1_TXD SAI_TX_DATA Transmit Data. The transmit data is generated synchronously by the bit clock and is tristated whenever not transmitting a word. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
PORTD31–PORTD0 General-purpose input/output PTE[31:0] PORTE31–PORTE0 General-purpose input/output 1. The available GPIO pins depends on the specific package. See the signal multiplexing section for which exact GPIO signals are available. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Table 12-1. Reference links to related information Topic Related module Reference Full description Port control Port control System memory map System memory map Clocking Clock Distribution Register access Peripheral bus Peripheral bridge controller KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Disabled Disabled Disabled enable at reset Pin mux control Pin mux at reset PTA0/PTA1/PTA2/ ALT0 ALT0 ALT0 ALT0 PTA3/PTA4=ALT7; Others=ALT0 Lock bit Interrupt and DMA request Digital glitch filter KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
There is one instance of the PORT module for each port. Not all pins within each port are implemented on a specific device. 12.3.1 Features The PORT module has the following features: • Pin interrupt KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
In Wait mode, PORT continues to operate normally and may be configured to exit the Low-Power mode if an enabled interrupt is detected. DMA requests are still generated during the Wait mode, but do not cause an exit from the Low-Power mode. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Negated—pin is logic 0. Timing Assertion—may occur at any time and can assert asynchronously to the system clock. Negation—may occur at any time and can assert asynchronously to the system clock. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Pin Control Register n (PORTA_PCR28) See section 12.6.1/186 4004_9074 Pin Control Register n (PORTA_PCR29) See section 12.6.1/186 4004_9078 Pin Control Register n (PORTA_PCR30) See section 12.6.1/186 Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Pin Control Register n (PORTB_PCR25) See section 12.6.1/186 4004_A068 Pin Control Register n (PORTB_PCR26) See section 12.6.1/186 4004_A06C Pin Control Register n (PORTB_PCR27) See section 12.6.1/186 Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Pin Control Register n (PORTC_PCR22) See section 12.6.1/186 4004_B05C Pin Control Register n (PORTC_PCR23) See section 12.6.1/186 4004_B060 Pin Control Register n (PORTC_PCR24) See section 12.6.1/186 Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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4004_C04C Pin Control Register n (PORTD_PCR19) See section 12.6.1/186 4004_C050 Pin Control Register n (PORTD_PCR20) See section 12.6.1/186 4004_C054 Pin Control Register n (PORTD_PCR21) See section 12.6.1/186 Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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4004_D040 Pin Control Register n (PORTE_PCR16) See section 12.6.1/186 4004_D044 Pin Control Register n (PORTE_PCR17) See section 12.6.1/186 4004_D048 Pin Control Register n (PORTE_PCR18) See section 12.6.1/186 Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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4004_D0A0 Interrupt Status Flag Register (PORTE_ISFR) 0000_0000h 12.6.4/190 4004_D0C0 Digital Filter Enable Register (PORTE_DFER) 0000_0000h 12.6.5/190 4004_D0C4 Digital Filter Clock Register (PORTE_DFCR) 0000_0000h 12.6.6/191 4004_D0C8 Digital Filter Width Register (PORTE_DFWR) 0000_0000h 12.6.7/191 KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
This read-only field is reserved and always has the value 0. Interrupt Status Flag The pin interrupt configuration is valid in all digital pin muxing modes. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Alternative 2 (chip-specific). 0011 Alternative 3 (chip-specific). 0100 Alternative 4 (chip-specific). 0101 Alternative 5 (chip-specific). 0110 Alternative 6 (chip-specific). 0111 Alternative 7 (chip-specific). Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Corresponding Pin Control Register is updated with the value in GPWD. GPWD Global Pin Write Data Write value that is written to all Pin Control Registers bits [15:0] that are selected by GPWE. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Chapter of Signal Multiplexing and Signal Descriptions for the pins that support digital filter. The digital filter configuration is valid in all digital pin muxing modes. Address: Base address + C0h offset Reset PORTx_DFER field descriptions Field Description Digital Filter Enable KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
12.6.7 Digital Filter Width Register (PORTx_DFWR) This register is read only for ports that do not support a digital filter. The digital filter configuration is valid in all digital pin muxing modes. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Pin Control register. For example, if an I C function is enabled on a pin, that does not override the pullup or open drain configuration for that pin. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
The global pin control registers are write-only registers, that always read as 0. 12.7.3 External interrupts The external interrupt capability of the PORT module is available in all digital pin muxing modes provided the PORT module is enabled. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
If the digital filters for a port are configured to use the bus clock, then the digital filters are bypassed for the duration of Stop mode. While the digital filters KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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The maximum latency through a digital filter equals three filter clock cycles plus the filter width configuration register. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
ERCLK32K is output on PTE0. ERCLK32K is output on PTE26. Reserved. 15–12 RAM size RAMSIZE This field specifies the amount of system RAM available on the device. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Reset SIM_SOPT2 field descriptions Field Description 31–30 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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This read-only field is reserved and always has the value 0. Debug trace clock select TRACECLKSEL Selects the core/system clock, or MCG output clock (MCGOUTCLK) as the trace clock source. MCGOUTCLK Core/system clock Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
This field is reserved. This read-only field is reserved and always has the value 0. 13.2.3 System Options Register 5 (SIM_SOPT5) Address: 4004_7000h base + 1010h offset = 4004_8010h Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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UART 0 transmit data source select Selects the source for the UART 0 transmit data. UART0_TX pin UART0_TX pin modulated with TPM1 channel 0 output Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Selects the ADC0 pre-trigger source when alternative triggers are enabled through ADC0ALTTRGEN. This field is not used when the TPM trigger source is selected. Pre-trigger A Pre-trigger B Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Reset SIM_SOPT9 field descriptions Field Description 31–27 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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NOTE: When the TPM is not in input capture mode, clear this field. TPM1_CH0 signal CMP0 output Reserved USB start of frame pulse Reserved This field is reserved. This read-only field is reserved and always has the value 0. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Kinetis V series 0111 Kinetis KS series 19–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
This read-only field is reserved and always has the value 0. This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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This bit controls the clock gate to the EWM module. Clock disabled Clock enabled This field is reserved. Reserved This read-only field is reserved and always has the value 0. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
This bit controls the clock gate to the Port D module. Clock disabled Clock enabled Port C Clock Gate Control PORTC This bit controls the clock gate to the Port C module. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
This bit controls software access to the Low Power Timer module. Access disabled Access enabled 13.2.9 System Clock Gating Control Register 6 (SIM_SCGC6) Address: 4004_7000h base + 103Ch offset = 4004_803Ch I2S1 Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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This bit controls the clock gate to the TPM0 module. Clock disabled Clock enabled PIT Clock Gate Control This bit controls the clock gate to the PIT module. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Clock enabled This field is reserved. Reserved This read-only field is reserved and always has the value 0. LPUART0 Clock Gate Control LPUART0 Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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This bit controls the clock gate to the flash memory. Flash reads are still supported while the flash memory is clock gated, but entry into low power modes is blocked. Clock disabled Clock enabled KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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1101 Divide-by-14. 1110 Divide-by-15. 1111 Divide-by-16. 23–20 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
This read-only field is reserved and always has the value 0. 13.2.12 System Clock Divider Register 2 (SIM_CLKDIV2) Address: 4004_7000h base + 1048h offset = 4004_8048h Reset USBDIV Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
13.2.13 Flash Configuration Register 1 (SIM_FCFG1) Address: 4004_7000h base + 104Ch offset = 4004_804Ch PFSIZE Reset Reset * Notes: • Reset value loaded during System Reset from Flash IFR. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Flash accesses are disabled (and generate a bus error) and the Flash memory is placed in a low power state. This bit should not be changed during VLP modes. Relocate the interrupt vectors out of Flash memory before disabling the Flash. Flash is enabled Flash is disabled KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
13.2.19 System Clock Divider Register 3 (SIM_CLKDIV3) This register should only be written when the LPUART, LPI2C and TPM modules are disabled. Address: 4004_7000h base + 1064h offset = 4004_8064h Reset PLLFLLDIV Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
I2S0_MCLK UARTSELONUSB UART Selection over USB DP/DM pins. For more details, see the "UART Over USB Capability" section in the USB chapter. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Chapter 13 System Integration Module (SIM) SIM_MISCCTL field descriptions (continued) Field Description UART0 UART1 UART2 LPUART (default) 13.3 Functional description For more information about the functions of SIM, see the Introduction section. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
• Packet error detection and retransmission • Protection of RAM used by the flashloader while it is running • Provides command to read properties of the device, such as flash and RAM size KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
The Kinetis Flashloader requires a minimum memory space of 32 KB of RAM. For Kinetis devices with less than this amount of on-chip RAM, the Kinetis Flashloader is not available. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
• There is no timeout for the active peripheral detection process. • If communication is detected, then all inactive peripherals are shut down, and the command phase is entered. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Start byte (0x5A) received on CANn? Enter flashloader activity detected on Init hardware USB FS? Configure clocks Was a Ping packet received on UARTn? KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 Init Flash, NXP Semiconductors Property and Memory interfaces...
14.3.4.1 Command with no data phase The protocol for a command with no data phase contains: • Command packet (from host) • Generic response command packet (to host) KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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The protocol for a command with an incoming data phase contains: • Command packet (from host) • Generic response command packet (to host) • Incoming data packets (from host) • Generic response command packet (to host) KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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• Data phases may be aborted by the receiving side by sending the final Generic Response early with a status of KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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The protocol for a command with an outgoing data phase contains: • Command packet (from host) • ReadMemory Response command packet (to host) (kCommandFlag_HasDataPhase set) • Outgoing data packets (to host) • Generic response command packet (to host) KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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• If the ReadMemory Response command packet prior to the start of the data phase does not contain the kCommandFlag_HasDataPhase flag, then the data phase is aborted. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
A Ping packet must be sent before any other communications. In response to a Ping packet, the target sends a Ping Response packet. Table 14-3. Ping Packet Format Byte # Value Name 0x5A start byte 0xA6 ping KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Byte # Value Parameter 0x5A start byte 0xA7 Ping response code Protocol bugfix Protocol minor Protocol major Protocol name = 'P' (0x50) Options low Options high CRC16 low CRC16 high KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Data phase is being aborted. 0xA4 kFramingPacketType_Command The framing packet contains a command packet payload. 0xA5 kFramingPacketType_Data The framing packet contains a data packet payload. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Table 14-10. Commands that are supported Command Name 0x01 FlashEraseAll 0x02 FlashEraseRegion 0x03 ReadMemory 0x04 WriteMemory Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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ParameterCount: The number of parameters included in the command packet. Parameters: The parameters are word-length (32 bits). With the default maximum packet size of 32 bytes, a command packet can contain up to 7 parameters. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Flashloader Status Error Codes, lists the status codes returned to the host by the Kinetis Flashloader. 4 - 7 Command tag The Command tag parameter identifies the response to the command sent by the host. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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0. The parameter count is set to 2 plus the number of words requested to be read in the FlashReadOnceCommand. Table 14-15. FlashReadOnceResponse Parameters Byte # Value Parameter 0 – 3 Status Code Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
The address needs to be a valid memory location residing in accessible flash (internal or external) or in RAM. The command supports the passing of one 32-bit KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Properties are the defined units of data that can be accessed with the GetProperty or SetProperty commands. Properties may be read-only or read-write. All read-write properties are 32-bit integers, so they can easily be carried in a command parameter. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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0x08 0x00 crc16 0x73 0xD4 Command packet commandTag 0x07 – GetProperty flags 0x00 reserved 0x00 parameterCount 0x01 propertyTag 0x00000001 - CurrentVersion The GetProperty command has no data phase. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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The property tag and the new value to set are the 2 parameters required for the SetProperty command. Table 14-21. Parameters for SetProperty Command Byte # Command 0 - 3 Property tag 4 - 7 Property value KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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The SetProperty command has no data phase. Response: The target (Kinetis Flashloader) will return a GenericResponse packet with one of following status codes: Table 14-23. SetProperty Response Status Codes Status Code kStatus_Success kStatus_ReadOnly kStatus_UnknownProperty kStatus_InvalidArgument KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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0x5A packetType 0xA4, kFramingPacketType_Command length 0x04 0x00 crc16 0xC4 0x2E Command packet commandTag 0x01 - FlashEraseAll flags 0x00 reserved 0x00 parameterCount 0x00 The FlashEraseAll command has no data phase. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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WriteMemory is that a data pattern is included in FillMemory command parameter, and there is no data phase for the FillMemory command, while WriteMemory does have a data phase. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Byte # Command 0 - 3 Index of program once field 4 - 7 Byte count (must be evenly divisible by 4) 8 - 11 Data 12 - 16 Data KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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14.3.6.8 FlashReadOnce command The FlashReadOnce command returns the contents of the program once field by given index and byte count. The FlashReadOnce command uses 2 parameters: index and byteCount. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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0x02 index 0x0000_0000 byteCount 0x0000_0004 Table 14-34. FlashReadOnce Response Format (Example) FlashReadOnce Parameter Value Response Framing packet start byte 0x5A packetType 0xA4 Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Start address of specific non-volatile memory to be read 4 - 7 byteCount Byte count to be read 8 - 11 option 0: IFR 1: Flash firmware ID KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Table 14-40. Parameters for read memory command Byte Parameter Description Start address Start address of memory to read from Byte count Number of bytes to read and return to caller KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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GenericResponse packet with a status code either set to kStatus_Success or an appropriate error status code. 14.3.6.13 Reset command The Reset command will result in flashloader resetting the chip. The Reset command requires no parameters. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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The command only specifies the size in bytes of the SB file that will be sent in the data phase. The SB file will be processed as it is received by the Flashloader . KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
• 0x00 will be sent as the response to host if the target is busy with processing or preparing data. The following flow charts demonstrate the communication flow of how the host reads ping packet, ACK and response from the target. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Reached 0x5A Read 1 byte 0xA1 maximum received? from target received? retries? Report a timeout error Figure 14-19. Host reads ACK packet from target via I2C KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
• The byte 0x00 will be sent as response to host if target is under the following conditions: • Processing incoming packet • Preparing outgoing data • Received invalid data KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Send 0x00 to 0x5A 0xA1 shift out 1 byte received? received? from target Report a Next action timeout error Figure 14-22. Host reads ACK from target via SPI KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
(8-bit data, no parity bit and 1 stop bit). If the bytes of the ping packet are sent one-by-one with more than 80 ms delay between them, then the autobaud KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Reached Wait for 1 byte 0x5A 0xA1 maximum received? received? from target retries? Report a timeout error Figure 14-24. Host reads an ACK from target via UART KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
The ability for the device to NAK Out transfers (until they can be received) provides the required flow control; the built-in CRC of each USB packet provides the required error detection. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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• VID = 0x15A2 • PID = 0x0073 Default Strings: • Manufacturer [1] = "Freescale Semiconductor Inc." (Note that Freescale Semiconductor is now NXP Semiconductors.) • Product [2] = "Kinetis Bootloader" 14.4.4.3 Endpoints The HID peripheral uses 3 endpoints: • Control (0) •...
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(in bytes) of the packet sent in the report. This size does not include the Report ID or the Packet Length header itself. During a data phase, a packet size of 0 indicates a data phase abort request from the receiver. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
(and it should report the error to the application). The following flowcharts show how the host reads a ping packet, ACK and response from the target. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Read 1 byte of ping response from target packet 0x5A 0xA7 Read 1 byte Report Error received? received? from target Figure 14-28. Host reads a ping response from target via FlexCAN KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
VerifyWrites feature is enabled by default. 0 - No verification is done. 1 - Enable verification. MaxPacketSize Maximum supported packet size for the currently active peripheral interface. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
0 = Normal 1 = User (default) 2 = Factory TargetVersion SoC target build version number 14.5.1 Property Definitions Get/Set property definitions are provided in this section. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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0x01. To get the bit mask for a given command, use this expression: mask = 1 << (tag - 1) Table 14-47. Command bits: [31: [17] [16] [15] [14] [13] [12] [11] [10] Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
I2C Slave RX Overrun error. kStatus_I2C_AribtrationLost I2C Arbitration Lost error. kStatus_SPI_SlaveTxUnderrun SPI Slave TX Underrun error. kStatus_SPI_SlaveRxOverrun SPI Slave RX Overrun error. kStatus_SPI_Timeout SPI tranfser timed out. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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CRC check is invalid, because the BCA is invalid or the CRC parameters are unset (all 0xFF bytes). kStatus_AppCrcCheckOutOfRange 10404 CRC check is valid but addresses are out of range. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Kinetis Flashloader Status Error Codes KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Indicates a reset has been caused by an active-low level on the external RESET pin. Reset not caused by external reset pin Reset caused by external reset pin Watchdog WDOG Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
The reset state of these bits depends on what caused the MCU to reset. NOTE The reset value of this register depends on the reset source: • POR (including LVD) — 0x00 • LVD (without POR) — 0x00 KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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JTAG Generated Reset JTAG Indicates a reset has been caused by JTAG selection of certain IR codes: EXTEST, HIGHZ, and CLAMP. Reset not caused by JTAG Reset caused by JTAG KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Selects how the reset pin filter is enabled in run and wait modes. All filtering disabled Bus clock filter enabled for normal operation LPO clock filter enabled for normal operation Reserved KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Bus clock filter count is 22 10110 Bus clock filter count is 23 10111 Bus clock filter count is 24 11000 Bus clock filter count is 25 Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Sticky Watchdog SWDOG Indicates a reset has been caused by the watchdog timer timing out.This reset source can be blocked by disabling the watchdog. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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In LLS mode, the RESET pin is the only wakeup source that can cause this reset. Any enabled wakeup source in a VLLSx mode causes a reset. Reset not caused by LLWU module wakeup source Reset caused by LLWU module wakeup source KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Reset caused by software setting of SYSRESETREQ bit Sticky Core Lockup SLOCKUP Indicates a reset has been caused by the ARM core indication of a LOCKUP event. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Sticky JTAG Generated Reset SJTAG Indicates a reset has been caused by JTAG selection of certain IR codes: EXTEST, HIGHZ, and CLAMP. Reset not caused by JTAG Reset caused by JTAG KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Stop are the common terms used for the primary operating modes of Kinetis microcontrollers. The following table shows the translation between the ARM CPU modes and the Kinetis MCU power modes. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
This ensures that all register writes associated with setting up the low power mode being entered have completed before the MCU enters the low power mode. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Provided the appropriate control bits are set up in PMCTRL, this write-once field allows the MCU to enter High Speed Run mode (HSRUN). Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
This register is reset on Chip POR not VLLS and by reset types that trigger Chip POR not VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See the Reset section details for more information. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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NOTE: When set to STOP, the PSTOPO bits in the STOPCTRL register can be used to select a Partial Stop mode if desired. Normal Stop (STOP) Reserved Very-Low-Power Stop (VLPS) Low-Leakage Stop (LLSx) Very-Low-Leakage Stop (VLLSx) Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
POR detect circuit is disabled in VLLS0 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Address: 4007_E000h base + 3h offset = 4007_E003h Read PMSTAT Write Reset SMC_PMSTAT field descriptions Field Description PMSTAT Power Mode Status NOTE: When debug is enabled, the PMSTAT will not update to STOP or VLPS KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
16.4.1 Power mode transitions The following figure shows the power mode state transitions available on the chip. Any reset always brings the MCU back to the normal RUN state. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Sleep-now or sleep-on-exit modes entered with SLEEPDEEP clear, controlled in System Control Register in ARM core. See note. WAIT Interrupt or Reset STOP PMCTRL[RUNM]=00, PMCTRL[STOPM]=000 Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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VLLSx PMPROT[AVLLS]=1, PMCTRL[STOPM]=100, STOPCTRL[LLSM]=x (VLLSx), Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Entry into a low-power stop mode (Stop, VLPS, LLS, VLLSx) is initiated by a CPU executing the WFI instruction. After the instruction is executed, the following sequence occurs: 1. The CPU clock is gated off immediately. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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For wait modes (WAIT and VLPW), the CPU clock is gated off while all other clocking continues, as in RUN and VLPR mode operation. Some modules that support stop-in- wait functionality have their clocks disabled in these configurations. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
• All clock monitors in the MCG must be disabled. • The maximum frequencies of the system, bus, flash, and core are restricted. See the Power Management details about which frequencies are supported. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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To reenter normal RUN mode, clear PMCTRL[RUNM]. Any reset also clears PMCTRL[RUNM] and causes the system to exit to normal RUN mode after the MCU exits its reset flow. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
A system reset causes an exit from VLPW mode, returning the device to normal RUN mode. 16.4.5 Stop modes This device contains a variety of stop modes to meet your application needs. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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A system reset will cause an exit from STOP mode, returning the device to normal RUN mode via an MCU reset. 16.4.5.2 Very-Low-Power Stop (VLPS) mode The two ways in which VLPS mode can be entered are listed here. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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NOTE The LLWU interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit Stop mode on an LLS recovery. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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An asserted RESET pin will cause an exit from any VLLS mode, returning the device to normal RUN mode. When exiting VLLS via the RESET pin, RCM_SRS[PIN] and RCM_SRS[WAKEUP] are set. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
The VLLDBGACK bit is cleared by the debugger (or can be left set as is) or clears automatically due to the reset generated as part of the next VLLS recovery. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
). The trip voltage is selected by LVDH LVDL LVDSC1[LVDV]. The LVD is disabled upon entering VLPx, LLS, and VLLSx modes. Two flags are available to indicate the status of the low-voltage detect system: KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
LVDSC2[LVWIE]. If enabled, an LVW interrupt request occurs when LVDSC2[LVWF] is set. LVDSC2[LVWF] is cleared by writing 1 to LVDSC2[LVWACK]. LVDSC2[LVWV] selects one of the four trip voltages: KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
By configuring the HVD circuit for interrupt operation (HVDSC1[HVDIE] set and HVDSC1[HVDRE] clear), HVDSC1[HVDF] is set and an HVD interrupt request occurs upon detection of a high voltage condition. HVDSC1[HVDF] is cleared by writing 1 to HVDSC1[HVDACK]. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Low Voltage Detect Status And Control 2 register 4007_D001 17.6.2/316 (PMC_LVDSC2) 4007_D002 Regulator Status And Control register (PMC_REGSC) 17.6.3/317 High Voltage Detect Status And Control 1 register 4007_D00B 17.6.4/319 (PMC_HVDSC1) KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Chip Reset Not VLLS. For more information about these reset types, refer to the Reset section details. Address: 4007_D000h base + 1h offset = 4007_D001h Read LVWF LVWIE LVWV Write LVWACK Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
(REGONS) indicating the regulator is in run regulation. NOTE This register is reset on Chip Reset Not VLLS and by reset types that trigger Chip Reset not VLLS. See the Reset section details for more information. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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This field is reserved. Reserved NOTE: This reserved bit must remain cleared (set to 0). Bandgap Buffer Enable BGBE Enables the bandgap buffer. Bandgap buffer not enabled Bandgap buffer enabled KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
High-Voltage Detect Interrupt Enable HVDIE Enables hardware interrupt requests for HVDF. Hardware interrupt disabled (use polling) Request a hardware interrupt when HVDF = 1 Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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This read-only field is reserved and always has the value 0. High-Voltage Detect Voltage Select HVDV Selects the HVD trip point voltage (V Low trip point selected (V HVDL High trip point selected (V HVDH KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
The input sources are described in the device's chip configuration details. Each of the available wake-up sources can be individually enabled. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
NOTE The LLWU interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit Stop mode on an LLS recovery. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Upon an exit from the LLS or VLLSx mode, the LLWU becomes inactive. 18.2.3 Block diagram The following figure is the block diagram for the LLWU module. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
LLWU_P0 wakeup occurred Edge detect WUPE0 Figure 18-1. LLWU block diagram 18.3 LLWU signal descriptions The signal properties of LLWU are shown in the table found here. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
LLWU_P19-LLWU_P16. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
External input pin enabled with any change detection 18.4.6 LLWU Pin Enable 6 register (LLWU_PE6) LLWU_PE6 contains the field to enable and select the edge detect type for the external wakeup input pins LLWU_P23-LLWU_P20. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Enables and configures the edge detection for the wakeup pin. External input pin disabled as wakeup input External input pin enabled with rising edge detection Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Enables and configures the edge detection for the wakeup pin. External input pin disabled as wakeup input External input pin enabled with rising edge detection Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Internal module flag used as wakeup source Wakeup Module Enable For Module 5 WUME5 Enables an internal module as a wakeup source input. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
WUPEx bit is cleared. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF2. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Address: 4007_C000h base + Ah offset = 4007_C00Ah Read WUF15 WUF14 WUF13 WUF12 WUF11 WUF10 WUF9 WUF8 Write Reset LLWU_PF2 field descriptions Field Description Wakeup Flag For LLWU_P15 WUF15 Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF8. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF22. LLWU_P22 input was not a wakeup source LLWU_P22 input was a wakeup source Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
LLWU_PF4 contains the wakeup flags indicating which wakeup source caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF27. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Module 2 input was not a wakeup source Module 2 input was a wakeup source Wakeup flag For module 1 MWUF1 Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Pin Filter 1 was a wakeup source 6–5 Digital Filter On External Pin FILTE Controls the digital filter options for the external pin detect. Filter disabled Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
6–5 Digital Filter On External Pin FILTE Controls the digital filter options for the external pin detect. Filter disabled Filter posedge detect enabled Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Four wakeup detect filters are available for selected external pins. Glitch filtering is not provided on the internal modules. For internal module interrupts, the WUMEx bit enables the associated module interrupt as a wakeup source. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
LLWU flag from being falsely set when PMC_REGSC[ACKISO] is cleared. The signal selected as a wake-up source pin must be a digital pin, as selected in the pin mux control. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
This read-only field is reserved and always has the value 0. Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Bits 15-8 are read-only indicator flags based on the processor’s FPSCR register. Attempted writes to these bits are ignored. Once set, the flags remain asserted until software clears the corresponding FPSCR bit. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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This read-only bit is a copy of the core’s FPSCR[IOC] bit and signals an illegal operation has been detected in the processor’s FPU. Once set, this bit remains set until software clears the FPSCR[IOC] bit. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
31–3 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Compute Operation wakeup on interrupt CPOWOI Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
To determine the exact source of the interrupt qualify the interrupt status flags with the corresponding interrupt enable bits. 1. From MCM_ISCR[31:16] && MCM_ISCR[15:0] 2. Search the result for asserted flags, which indicate the exact interrupt sources KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Slave port number Flash memory controller SRAM controllers Peripheral bridge 0/GPIO 20.2 Introduction The information found here provides information on the layout, configuration, and programming of the crossbar switch. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
The latency in servicing the request depends on each master's priority level and the responding slave's access time. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
5 masters, master 1 has lower priority than master 3). If two masters request access to the same slave port, the master with the highest priority gains control over the slave port. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
20.5 Initialization/application information No initialization is required for the crossbar switch. See the chip-specific crossbar switch information for the reset state of the arbitration scheme. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Initialization/application information KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
21.2.1 Features Key features of the peripheral bridge are: • Supports peripheral slots with 8-, 16-, and 32-bit datapath width KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
All accesses to the peripheral slots must be sized less than or equal to the designated peripheral slot size. If an access is attempted that is larger than the targeted port, an error response is generated. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Port control module Port A Port control module Port B Port control module Port C Port control module Port D Port control module Port E Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
22.2 Introduction 22.2.1 Overview The Direct Memory Access Multiplexer (DMAMUX) routes DMA sources, called slots, to any of the 16 DMA channels. This process is illustrated in the following figure. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
• Each channel router can be assigned to one of the possible peripheral DMA slots or to one of the always-on slots. 22.2.3 Modes of operation The following operating modes are available: • Disabled mode KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
• For 8-bit registers, the lower address byte is read as the most significant byte. • For 16-bit registers, the lower address word is read as the most significant word. The following figure provides examples of this. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
DMA slots (peripheral slots or always-on slots) in the system. NOTE Setting multiple CHCFG registers with the same source value will result in unpredictable behavior. This is true, even if a channel is disabled (ENBL==0). KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Functionally, the DMAMUX channels may be divided into two classes: • Channels that implement the normal routing functionality plus periodic triggering capability • Channels that implement only the normal routing functionality KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
This can either be a new software activation, or a transfer request from the DMA channel MUX. The options for doing this are: • Transfer all data in a single minor loop. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
1. Determine with which DMA channel the source will be associated. Note that only the first 4 DMA channels have periodic triggering capability. 2. Clear the CHCFG[ENBL] and CHCFG[TRIG] fields of the DMA channel. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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DMA channels that have triggering capability. To configure source #5 transmit for use with DMA channel 1, with no periodic triggering capability: 1. Write 0x00 to CHCFG1. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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2. Write 0x00 to CHCFG8. 3. Write 0x87 to CHCFG8. (In this example, setting CHCFG[TRIG] would have no effect due to the assumption that channel 8 does not support the periodic triggering functionality.) KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
• Local memory containing transfer control descriptors for each of the 16 channels 23.1.1 eDMA system block diagram Figure 23-1 illustrates the components of the eDMA system, including the eDMA module ("engine"). KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
After the minor loop completes execution, the address path hardware writes Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
The eDMA module features: • All data movement via dual-address transfers: read from source, write to destination • Programmable source and destination addresses and transfer size • Support for enhanced addressing modes KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
• Support for complex data structures In the discussion of this module, n is used to reference the channel number. 23.2 Modes of operation The eDMA operates in the following modes: KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
0, channel 1, ... channel 15. Each TCDn definition is presented as 11 registers of 16 or 32 bits. 23.3.2 TCD initialization Prior to activating a channel, you must initialize its TCD with the appropriate transfer profile. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
23.3.4/404 4000_8018 Clear Enable Error Interrupt Register (DMA_CEEI) (always 23.3.5/406 reads 0) 4000_8019 Set Enable Error Interrupt Register (DMA_SEEI) (always 23.3.6/407 reads 0) Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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4000_9000 TCD Source Address (DMA_TCD0_SADDR) Undefined 23.3.18/425 4000_9004 TCD Signed Source Address Offset (DMA_TCD0_SOFF) Undefined 23.3.19/425 4000_9006 TCD Transfer Attributes (DMA_TCD0_ATTR) Undefined 23.3.20/426 Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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TCD Current Minor Loop Link, Major Loop Count (Channel 4000_9036 Undefined 23.3.27/432 Linking Enabled) (DMA_TCD1_CITER_ELINKYES) 4000_9036 DMA_TCD1_CITER_ELINKNO Undefined 23.3.28/433 TCD Last Destination Address Adjustment/Scatter Gather 4000_9038 Undefined 23.3.29/434 Address (DMA_TCD1_DLASTSGA) Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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4000_9068 Enabled and Offset Disabled) Undefined 23.3.22/428 (DMA_TCD3_NBYTES_MLOFFNO) TCD Signed Minor Loop Offset (Minor Loop Mapping and 4000_9068 Undefined 23.3.23/429 Offset Enabled) (DMA_TCD3_NBYTES_MLOFFYES) Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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(DMA_TCD4_BITER_ELINKYES) TCD Beginning Minor Loop Link, Major Loop Count 4000_909E Undefined 23.3.32/438 (Channel Linking Disabled) (DMA_TCD4_BITER_ELINKNO) 4000_90A0 TCD Source Address (DMA_TCD5_SADDR) Undefined 23.3.18/425 Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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4000_90D4 Undefined 23.3.26/431 (DMA_TCD6_DOFF) TCD Current Minor Loop Link, Major Loop Count (Channel 4000_90D6 Undefined 23.3.27/432 Linking Enabled) (DMA_TCD6_CITER_ELINKYES) 4000_90D6 DMA_TCD6_CITER_ELINKNO Undefined 23.3.28/433 Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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TCD Minor Byte Count (Minor Loop Mapping Disabled) 4000_9108 Undefined 23.3.21/427 (DMA_TCD8_NBYTES_MLNO) TCD Signed Minor Loop Offset (Minor Loop Mapping 4000_9108 Enabled and Offset Disabled) Undefined 23.3.22/428 (DMA_TCD8_NBYTES_MLOFFNO) Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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4000_913C TCD Control and Status (DMA_TCD9_CSR) Undefined 23.3.30/435 TCD Beginning Minor Loop Link, Major Loop Count 4000_913E (Channel Linking Enabled) Undefined 23.3.31/437 (DMA_TCD9_BITER_ELINKYES) Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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TCD Signed Minor Loop Offset (Minor Loop Mapping and 4000_9168 Undefined 23.3.23/429 Offset Enabled) (DMA_TCD11_NBYTES_MLOFFYES) TCD Last Source Address Adjustment 4000_916C Undefined 23.3.24/430 (DMA_TCD11_SLAST) 4000_9170 TCD Destination Address (DMA_TCD11_DADDR) Undefined 23.3.25/431 Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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4000_919E (Channel Linking Disabled) Undefined 23.3.32/438 (DMA_TCD12_BITER_ELINKNO) 4000_91A0 TCD Source Address (DMA_TCD13_SADDR) Undefined 23.3.18/425 4000_91A4 TCD Signed Source Address Offset (DMA_TCD13_SOFF) Undefined 23.3.19/425 Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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4000_91D4 Undefined 23.3.26/431 (DMA_TCD14_DOFF) TCD Current Minor Loop Link, Major Loop Count (Channel 4000_91D6 Undefined 23.3.27/432 Linking Enabled) (DMA_TCD14_CITER_ELINKYES) 4000_91D6 DMA_TCD14_CITER_ELINKNO Undefined 23.3.28/433 Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
TCD Beginning Minor Loop Link, Major Loop Count 4000_91FE (Channel Linking Disabled) Undefined 23.3.32/438 (DMA_TCD15_BITER_ELINKNO) 23.3.1 Control Register (DMA_CR) The CR defines the basic operating configuration of the DMA. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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When minor loop mapping is disabled (EMLM is 0), all 32 bits of TCDn word2 are assigned to the NBYTES field. Address: 4000_8000h base + 0h offset = 4000_8000h Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Normal operation Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
• A cancel transfer with error bit that will be set when a transfer is canceled via the corresponding cancel transfer control bit See the Error Reporting and Handling section for more details. Address: 4000_8000h base + 4h offset = 4000_8004h Reset ERRCHN Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. • TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled Enable DMA Request 4 ERQ4 Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
The DMA error indicator and the error interrupt enable flag must be asserted before an error interrupt request for a given channel is asserted to the interrupt controller. Address: 4000_8000h base + 14h offset = 4000_8014h Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request Enable Error Interrupt 6 EEI6 Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: 4000_8000h base + 18h offset = 4000_8018h Read Write CAEE CEEI Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Sets All Enable Error Interrupts SAEE Set only the EEI bit specified in the SEEI field. Sets all bits in EEI 5–4 This field is reserved. Reserved Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Clear only the ERQ bit specified in the CERQ field Clear all bits in ERQ 5–4 This field is reserved. Reserved CERQ Clear Enable Request Clears the corresponding bit in ERQ. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Set only the ERQ bit specified in the SERQ field Set all bits in ERQ 5–4 This field is reserved. Reserved SERQ Set Enable Request Sets the corresponding bit in ERQ. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Clears only the TCDn_CSR[DONE] bit specified in the CDNE field Clears all bits in TCDn_CSR[DONE] 5–4 This field is reserved. Reserved CDNE Clear DONE Bit Clears the corresponding bit in TCDn_CSR[DONE] KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Set only the TCDn_CSR[START] bit specified in the SSRT field Set all bits in TCDn_CSR[START] 5–4 This field is reserved. Reserved SSRT Set START Bit Sets the corresponding bit in TCDn_CSR[START] KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Clear only the ERR bit specified in the CERR field Clear all bits in ERR 5–4 This field is reserved. Reserved CERR Clear Error Indicator Clears the corresponding bit in ERR KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Clear only the INT bit specified in the CINT field Clear all bits in INT 5–4 This field is reserved. Reserved CINT Clear Interrupt Request Clears the corresponding bit in INT KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Reset DMA_INT field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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The interrupt request for corresponding channel is active Interrupt Request 4 INT4 The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
A zero in any bit position has no affect on the corresponding channel’s current error status. The CERR is provided so the error indicator for a single channel can easily be cleared. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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An error in this channel has occurred Error In Channel 10 ERR10 An error in this channel has not occurred An error in this channel has occurred Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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An error in this channel has not occurred An error in this channel has occurred Error In Channel 0 ERR0 An error in this channel has not occurred An error in this channel has occurred KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Hardware Request Status Channel 15 HRS15 Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 420
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically cleared by hardware. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 421
A hardware service request for channel 3 is not present A hardware service request for channel 3 is present Hardware Request Status Channel 2 HRS2 Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Reset DMA_EARS field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 423
Enable asynchronous DMA request in stop mode for channel 4 EDREQ_4 Disable asynchronous DMA request for channel 4. Enable asynchronous DMA request for channel 4. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Channel n cannot be suspended by a higher priority channel’s service request. Channel n can be temporarily suspended by the service request of a higher priority channel. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
16-bit 32-bit Reserved 16-byte burst 32-byte burst Reserved Reserved 7–3 Destination Address Modulo DMOD See the SMOD definition DSIZE Destination data transfer size Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
TCD memory. If the major iteration count is completed, additional processing is performed. NOTE: An NBYTES value of 0x0000_0000 is interpreted as a 4 GB transfer. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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The minor loop offset is applied to the SADDR Destination Minor Loop Offset enable DMLOE Selects whether the minor loop offset is applied to the destination address upon minor loop completion. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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TCD_NBYTES_MLOFFNO register description. If minor loop mapping is disabled, then refer to the TCD_NBYTES_MLNO register description. Address: 4000_8000h base + 1008h offset + (32d × i), where i=0d to 15d MLOFF Reset MLOFF NBYTES Reset * Notes: KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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This register uses two's complement notation; the overflow bit is discarded. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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DMA_TCDn_DOFF field descriptions Field Description DOFF Destination Address Signed Offset Sign-extended offset applied to the current destination address to form the next-state value as each destination write is completed. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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CITER field from the Beginning Iteration Count (BITER) field. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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It is decremented each time the minor loop is completed and updated in the transfer control descriptor memory. After the major iteration count is exhausted, the channel performs a number of operations, for Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 434
This channel reload is performed as the major iteration count completes. The scatter/gather address must be 0-modulo-32-byte, otherwise a configuration error is reported. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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The software clears it, or the hardware when the channel is activated. NOTE: This bit must be cleared to write the MAJORELINK or ESG bits. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the INT when the current major iteration count reaches zero. The end-of-major loop interrupt is disabled. The end-of-major loop interrupt is enabled. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 437
CITER field. The channel-to-channel linking is disabled The channel-to-channel linking is enabled 14–13 This field is reserved. Reserved 12–9 Link Channel Number LINKCH Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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15 bits in place of a link channel number. If the major loop is exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel linking. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 439
23.4.1 eDMA basic data flow The basic flow of a data transfer can be partitioned into three segments. As shown in the following diagram, the first segment involves the channel activation: KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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The following diagram illustrates the second part of the basic data flow: KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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(if scatter/ gather is enabled). The updates to the TCD memory and the assertion of an interrupt request are shown in the following diagram. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Each of these possible causes are detailed below: • The addresses and offsets must be aligned on 0-modulo-transfer-size boundaries. • The minor loop byte count must be a multiple of the source and destination transfer sizes. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Due to pipeline effect, the next transfer is already in progress when the bus error is received by the eDMA. If a bus error KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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If a channel is terminated by an error and then issues another service request before the error is fixed, that channel executes and terminates with the same error condition. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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23.4.4.1 Peak transfer rates The peak transfer rates for several different source and destination transfers are shown in the following tables. These tables assume: KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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In the case of an internal peripheral bus read and internal SRAM write, the combined data phase time is 4 cycles. For an SRAM read and internal peripheral bus write, it is 5 cycles. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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11.5 cycles (4 + (4+5)/2 + 3). This is the time from Cycle 4 to Cycle x +5. The resulting peak request rate, as a function of the system frequency, is shown in the following table. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 448
PEAKreq = 150 MHz / [ 4 + (1 + 1) + (1 + 3) + 3 ] cycles = 11.5 Mreq/sec For an internal peripheral bus to SRAM transfer, KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 449
2. Write the channel priority levels to the DCHPRIn registers if a configuration other than the default is desired. 3. Enable error interrupts in the EEI register if so desired. 4. Write the 32-byte TCD for each channel that may request service. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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CPU intervention. DMA arbitration can occur after each minor loop, and one level of minor loop DMA preemption is allowed. The number of minor loops in a major loop is specified by the beginning iteration count (BITER). KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 451
The eDMA performs various tests on the transfer control descriptor to verify consistency in the descriptor data. Most programming errors are reported on a per channel basis with the exception of channel priority error (ES[CPE]). KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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(TCDn_CITER = TCDn_BITER = 1). The data transfer begins after the channel service request is acknowledged and the channel is selected to execute. After the transfer is complete, the TCDn_CSR[DONE] bit is set and an interrupt generates if properly enabled. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 453
Write 32-bits to location 0x2008 → third iteration of the minor loop. g. Read byte from location 0x100C, read byte from location 0x100D, read byte from 0x100E, read byte from 0x100F. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Write 32-bits to location 0x2004 → second iteration of the minor loop. e. Read byte from location 0x1008, read byte from location 0x1009, read byte from 0x100A, read byte from 0x100B. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 455
Write 32-bits to location 0x201C → last iteration of the minor loop → major loop complete. 14. eDMA engine writes: TCDn_SADDR = 0x1000, TCDn_DADDR = 0x2000, TCDn_CITER = 2 (TCDn_BITER). KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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The first is to read the TCDn_CITER field and test for a change. Another method may be extracted from the sequence shown below. The second method is KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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NBYTES are the values the eDMA engine currently uses in its internal register file and not the values in the TCD local memory for that channel. The addresses, SADDR and KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 458
TCDn_CITER[E_LINK] = 1 TCDn_CITER[LINKCH] = 0xC TCDn_CITER[CITER] value = 0x4 TCDn_CSR[MAJOR_E_LINK] = 1 TCDn_CSR[MAJOR_LINKCH] = 0x7 executes as: 1. Minor loop done → set TCD12_CSR[START] bit KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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This section provides recommended methods to change the programming model during channel execution. 23.5.7.1 Dynamically changing the channel priority The following two options are recommended for dynamically changing channel priority levels: KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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NOTE The user must clear the TCD.done bit before writing the TCD.major.e_link bit. The TCD.done bit is cleared automatically by the eDMA engine after a channel begins execution. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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1. When the descriptors are built, write a unique TCD ID in the TCD.major.linkch field for each TCD associated with a channel using dynamic scatter/gather. 2. Write 1b to the TCD.d_req bit. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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If e_sg = 0b, read the 32 bit TCD dlast_sga field. If e_sg = 0b and the dlast_sga did not change, the attempted dynamic link did not succeed (the channel was already retiring). KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Chapter 23 Enhanced Direct Memory Access (eDMA) If e_sg = 0b and the dlast_sga changed, the dynamic link attempt was successful (the new TCD’s e_sg value cleared the e_sg bit). KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Initialization/application information KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 465
When the CPU enters a Run mode from Wait or Stop recovery, the pin resumes its previous state before entering Wait or Stop mode. When the CPU enters Run mode from Power Down, the pin returns to its reset state. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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• Refresh outside window leads to assertion of EWM_out. • Robust refresh mechanism • Write values of 0xB4 and 0x2C to EWM Refresh Register within 15 (EWM_refresh_time) peripheral bus clock cycles. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 467
The EWM module treats the stop and wait modes as the same. EWM functionality remains the same in both of these modes. 24.2.2.3 Debug Mode Entry to debug mode has no effect on the EWM. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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/EWM_out Output EWM_CMPL[COMPAREL] Control EWM_in Mechanism EWM Service Register Figure 24-1. EWM Block Diagram 24.3 EWM Signal Descriptions The EWM has two external signals, as shown in the following table. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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INEN, ASSIN and EWMEN bits can be written once after a CPU reset. Modifying these bits more than once, generates a bus transfer error. Address: 4006_1000h base + 0h offset = 4006_1000h Read INTEN INEN ASSIN EWMEN Write Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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24.4.3 Compare Low Register (EWM_CMPL) The CMPL register is reset to zero after a CPU reset. This provides no minimum time for the CPU to refresh the EWM counter. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Description COMPAREH To prevent runaway code from changing this field, software should write to this field after a CPU reset even if the (default) maximum refresh time is required. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 472
The EWM_out is a digital output signal used to gate an external circuit (application specific) that controls critical safety functions. For example, the EWM_out could be connected to the high voltage transistors circuits that control an AC motor in a large appliance. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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(setting the CTRL[INEN] bit), the EWM_in signal must be in the deasserted state prior to the CPU start refreshing the EWM. This ensures that the EWM_out stays in the deasserted state; otherwise, the EWM_out output signal is asserted. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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EWM Service Register. The CPU must access the EWM service register with correct write of unique data within the windowed time frame as determined by the CMPL and CMPH registers for correct EWM refresh operation. Therefore, three possible conditions can occur: KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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CLKPRESCALER[CLK_DIV]. This divided clock is used to run the EWM counter. NOTE The divided clock used to run the EWM counter must be no more than half the frequency of the bus clock. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 477
This table shows the WDOG low-power modes and the corresponding chip low-power modes. Table 25-2. WDOG low-power modes Module mode Chip mode Wait Wait, VLPW Stop Stop, VLPS Power Down LLS, VLLSx KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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• Quick test—Small time-out value programmed for quick test. • Byte test—Individual bytes of timer tested one at a time. • Read-only access to the WDOG timer—Allows dynamic check that WDOG timer is operational. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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• Count of WDOG resets as they occur. • Configurable interrupt on time-out to provide debug breadcrumbs. This is followed by a reset after 256 bus clock cycles. 25.4 Functional overview KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Software can adjust the period of servicing or the time-out value for the watchdog timer to meet the needs of the application. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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The watchdog issues a reset, that is, interrupt-then-reset if enabled, to the system for any of these invalid unlock sequences: KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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• Stop, Wait, and Debug mode enable • IRQ_RST_EN The operations of refreshing the watchdog goes undetected during the WCT. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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However, the watchdog still generates a reset, or interrupt-then-reset if enabled, on a non- time-out exception. See Generated Resets and Interrupts. You need to unlock the watchdog before enabling it. A system reset brings the watchdog out of the disabled mode. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Do not enable the watchdog interrupt during these tests. If required, you must ensure that the effective time-out value is greater than WCT time. See Generated Resets and Interrupts more details. To run a particular test: KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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The following figure explains the splitting concept: KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 486
Two successive timer time-outs without an intervening system reset result in the backup reset generator routing out the time-out signal as a reset to the system. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Also, jobs such as counting the number of watchdog resets would not be done. 25.8 Memory map and register definition This section consists of the memory map and register descriptions. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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This 2-bit field selects the byte to be tested when the watchdog is in the byte test mode. BYTESEL[1:0] Byte 0 selected Byte 1 selected Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 489
A change in the value of this bit must be held for more than one WDOG_CLK cycle for the WDOG to be enabled or disabled. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 490
WDOG_TOVALH field descriptions Field Description TOVALHIGH Defines the upper 16 bits of the 32-bit time-out value for the watchdog timer. It is defined in terms of cycles of the watchdog clock. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 491
A refresh outside this window resets the system or if IRQRSTEN is set, it interrupts and then resets the system. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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20 bus cycles, resets the system, or if IRQRSTEN is set, it interrupts and then resets the system. 25.8.8 Watchdog Unlock register (WDOG_UNLOCK) Address: 4005_2000h base + Eh offset = 4005_200Eh Read WDOGUNLOCK Write Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Address: 4005_2000h base + 12h offset = 4005_2012h Read TIMEROUTLOW Write Reset WDOG_TMROUTL field descriptions Field Description TIMEROUTLOW Shows the value of the lower 16 bits of the watchdog timer. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 494
When performing 8-bit accesses to the watchdog's 16-bit registers where the intention is to access both the bytes of a register, place the two 8-bit accesses one after the other in your code. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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16-bit value is correctly written, write4. Hence, the requirement of writing value2 of the sequence within 20 bus clock cycles of value1 is checked by measuring the gap between write2 and write4. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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• The time-out value of the watchdog should be set to a minimum of four watchdog clock cycles. This is to take into account the delay in new settings taking effect in the watchdog clock domain. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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If the second refresh value is not written within 20 bus cycles of the first value, the system is reset, or interrupt-then- reset if enabled. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Restrictions on watchdog operation KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Clock Distribution for more details on these clocks. 26.1.2 MCG Instantiation Information NOTE MCG_C12/S2/T3 registers are all reserved and not applicable for this SoC, in the MCG memory map. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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• Can be used as a clock source for other on-chip peripherals. • Phase-locked loop (PLL): • Voltage-controlled oscillator (VCO) • External reference clock is used as the PLL source. • Modulo VCO frequency divider • Phase/Frequency detector KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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• MCG PLL Clock (MCGPLLCLK) is provided as a clock source for other on-chip peripherals • MCG FLL Clock (MCGFLLCLK) is provided as a clock source for other on-chip peripherals KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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• MCG Fixed Frequency Clock (MCGFFCLK) is provided as a clock source for other on-chip peripherals • MCG Internal Reference Clock (MCGIRCLK) is provided as a clock source for other on-chip peripherals This figure presents the block diagram of the MCG module. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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4006_400C MCG Control 7 Register (MCG_C7) 26.4.12/ 4006_400D MCG Control 8 Register (MCG_C8) 26.4.13/ 4006_4011 MCG Control 12 Register (MCG_C12) 26.4.13/ 4006_4012 MCG Status 2 Register (MCG_S2) 26.4.13/ 4006_4013 MCG Test 3 Register (MCG_T3) KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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MCGIRCLK active. Internal Reference Stop Enable IREFSTEN Controls whether or not the internal reference clock remains enabled when the MCG enters Stop mode. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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EREFS Selects the source for the external reference clock. See the Oscillator (OSC) chapter for more details. External reference clock requested. Oscillator requested. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 507
If an SCTRIM value stored in nonvolatile memory is to be used, it is your responsibility to copy that value from the nonvolatile memory location to this register. 1. A value for SCTRIM is loaded during reset from a factory programmed location. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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Encoding 1 — Mid range. Encoding 2 — Mid-high range. Encoding 3 — High range. 4–1 Fast Internal Reference Clock Trim Setting FCTRIM Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 509
MCGPLLCLK is disabled in any of the Stop modes. MCGPLLCLK is enabled if system is in Normal Stop mode. PRDIV0 PLL External Reference Divider Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 510
LOLS 0 is set. No interrupt request is generated on loss of lock. Generate an interrupt request on loss of lock. PLL Select PLLS Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 512
IREFS bit due to internal synchronization between clock domains. Source of FLL reference clock is the external reference clock. Source of FLL reference clock is the internal reference clock. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 513
Writing to C1, C3, C4, and SC registers or entering Stop mode aborts the auto trim operation and clears this bit. Auto Trim Machine disabled. Auto Trim Machine enabled. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
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CME0 is set. This bit is cleared by writing a logic 1 to it when set. Loss of OSC0 has not occurred. Loss of OSC0 has occurred. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 515
Values are used by Auto Trim Machine to compare and adjust Internal Reference trim values during ATM SAR conversion. 26.4.11 MCG Control 7 Register (MCG_C7) Address: 4006_4000h base + Ch offset = 4006_400Ch Read OSCSEL Write Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 516
Enables the loss of clock monitoring circuit for the output of the RTC external reference clock. The LOCRE1 bit will determine whether an interrupt or a reset request is generated following a loss of RTC Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 517
Address: 4006_4000h base + 12h offset = 4006_4012h Read Write Reset MCG_S2 field descriptions Field Description Reserved This field is reserved. This read-only field is reserved and always has the value 0. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 518
Returns to the state that was active before the MCU enters Stop mode Stop the MCU entered Stop mode, unless a reset occurs while in Stop mode. Figure 26-2. MCG mode state diagram KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 519
• C1[FRDIV] must be written to divide external reference clock to be within the range of 31.25 kHz to 39.0625 kHz • 0 is written to C6[PLLS]. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 520
PLL Bypassed External PLL Bypassed External (PBE) mode is entered when all the following conditions occur: (PBE) • 10 is written to C1[CLKS]. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 521
2’b10 and S[LOCK] bit will clear without setting S[LOLS]. If C5[PLLSTEN]=1, the S[LOCK] bit will not get cleared and on exit the MCG will continue to run in PEE mode. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 522
(slow IRC) and 4 MHz (fast IRC). The fast IRC frequency can be divided down by programming of the FCRDIV to produce a frequency range of 32 kHz to 4 MHz. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 523
LOCRE bit is set. Otherwise the MCG sets the respective LOCS bit and the MCG generates a LOCS interrupt request. In the case where a OSC loss of clock is detected, the PLL LOCK status bit is cleared. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 524
Therefore, it is required that the MCG is configured in a clock mode where the reference clock used to generate the system clock is the external reference clock such as KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 525
The following sections include examples on how to initialize the MCG and properly switch between the various available modes. 26.6.1 MCG module initialization sequence The MCG comes out of reset configured for FEI mode. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 526
• If the MCG is in FEE, FBE, PEE, PBE, or BLPE mode, and C2[EREFS] was also set in step 1, wait here for S[OSCINIT0] bit to become set indicating that the external clock source has finished its initialization cycles and stabilized. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 527
5. Wait for the FLL lock time to guarantee FLL is running at new C4[DRST_DRS] and C4[DMX32] programmed frequency. To change from FEI clock mode to FBI clock mode, follow this procedure: KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 528
Each time any of these bits are changed (C6[PLLS], C1[IREFS], C1[CLKS], C2[IRCS], or C2[EREFS], the corresponding bits in the MCG status register (PLLST, IREFST, CLKST, IRCST, or OSCINIT) must be checked before moving on in the application software. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 529
This section will include several mode switching examples, using an 4 MHz external crystal. If using an external clock source less than 2 MHz, the MCG must not be configured for any of the PLL modes (PEE and PBE). KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 530
• C5[PRDIV] set to 5'b00001, or divide-by-2 resulting in a pll reference frequency of 4MHz/2 = 2 MHz. 3. Then, FBE must transition either directly to PBE mode or first through BLPE mode and then to PBE mode: KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 531
Loop until S[CLKST] are 2'b11, indicating that the PLL output is selected to feed MCGOUTCLK in the current clock mode. • Now, with PRDIV of divide-by-2, and C6[VDIV] of multiply-by-24, MCGOUTCLK = [(4 MHz / 2) * 24] = 48 MHz. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 532
S[CLKST] = %11? ENTER BLPE MODE ? CONTINUE IN PEE MODE C2 = 0x1E (C2[LP] = 1) Figure 26-3. Flowchart of FEI to PEE mode transition using an 4 MHz crystal KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 533
PLLS clock is the FLL. 3. Next, FBE mode transitions into FBI mode: a. C1 = 0x54 • C1[CLKS] set to 2'b01 to switch the system clock to the internal reference clock. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 534
• C2[LP] is 1 • C2[RANGE], C2[HGO], C2[EREFS], C1[IRCLKEN], and C1[IREFSTEN] bits are ignored when the C1[IREFS] bit is set. They can remain set, or be cleared at this point. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 535
BLPE MODE ? BLPE MODE ? (C2[LP]=1) CONTINUE IN BLPI MODE C2 = 0x1C (C2[LP] = 0) Figure 26-4. Flowchart of PEE to BLPI mode transition using an 4 MHz crystal KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 536
At this point, by default, the C4[DRST_DRS] bits are set to 2'b00 and C4[DMX32] is cleared to 0. If the MCGOUTCLK frequency of 40 MHz is desired instead, set the C4[DRST_DRS] bits to 0x01 to switch the FLL KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 537
S[CLKST] = %00? C1 = 0x10 CONTINUE IN FEE MODE CHECK S[OSCINIT] = 1 ? Figure 26-5. Flowchart of BLPI to FEE mode transition using an 4 MHz crystal KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 538
Initialization / Application information KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 539
• High gain option in frequency ranges: 32 kHz, 3–8 MHz, and 8–32 MHz • Voltage and frequency filtering to guarantee clock frequency and stability • Optionally external input bypass clock from EXTAL signal directly KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 540
Range selections Oscillator Circuits OSCERCLK Low Power config OSC32KCLK 4096 CNT_DONE_4096 OSC_EN EREFSTEN ERCLKEN Counter Control and Decoding OSCCLK OSC clock selection logic STOP Figure 27-1. OSC Module Block Diagram KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 541
2. With the low-power mode, the oscillator has the internal feedback resistor R . Therefore, the feedback resistor must not be externally with the Connection 3. XTAL EXTAL Crystal or Resonator Figure 27-2. Crystal/Ceramic Resonator Connections - Connection 1 KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 542
In external clock mode, the pins can be connected as shown in the figure found here. NOTE XTAL can be used as a GPIO when the GPIO alternate function is configured for it. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 544
Add 8 pF capacitor to the oscillator load. Oscillator 16 pF Capacitor Load Configure SC16P Configures the oscillator load. Disable the selection. Add 16 pF capacitor to the oscillator load. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 545
27.9.1 OSC module states The states of the OSC module are shown in the following figure. The states and their transitions between each other are described in this section. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 546
MCU, refer to the chip configuration details. The EXTAL and XTAL pins are also decoupled from all other oscillator circuitry in this state. The OSC module circuitry is configured to draw minimal current. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 547
(MCG, Timer, and so on) is configured to use the oscillator output clock (OSC_CLK_OUT). Table 27-3. Oscillator modes Mode Frequency Range Low-frequency, high-gain (32.768 kHz) up to f (39.0625 kHz) osc_lo osc_lo Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 548
(not sensitive to the DC level of EXTAL). Also in this mode, all external components except for the resonator itself are integrated, which includes the load capacitors and feeback resistor that biases EXTAL. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 549
There is no reset state associated with the OSC module. The counter logic is reset when the OSC is not configured to generate clocks. There are no sources of reset requests for the OSC module. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 550
OSC is still functional in these modes. After waking up from Very Low Leakage Stop (VLLSx) modes, all OSC register bits are reset and initialization is required through software. 27.12 Interrupts The OSC module does not generate any interrupts. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 551
• Automatic Gain Control (AGC) to optimize power consumption The RTC oscillator operations are described in detail in Functional Description 28.1.2 Block Diagram The following is the block diagram of the RTC oscillator. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 552
28.2.1 EXTAL32 — Oscillator Input This signal is the analog input of the RTC oscillator. 28.2.2 XTAL32 — Oscillator Output This signal is the analog output of the RTC oscillator module. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 553
EXTAL32 and XTAL32. In addition, there are two programmable capacitors with this oscillator, which can be used as the Cload of the oscillator. The programmable range is from 0pF to 30pF. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 554
Reset Overview 28.6 Reset Overview There is no reset state associated with the RTC oscillator. 28.7 Interrupts The RTC oscillator does not generate any interrupts. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 555
64-bit buffer can store previously accessed flash memory data for quick access times. 29.1.2 Features The FMC's features include: • Interface between the device and the flash memory: • 8-bit, 16-bit, and 32-bit read operations to program flash memory. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 556
Program the registers only while the flash controller is idle (for example, execute from RAM). Changing configuration settings while a flash access is in progress can lead to non-deterministic behavior. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 557
FMC memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4001_F000 Flash Access Protection Register (FMC_PFAPR) 00F8_003Fh 29.4.1/561 Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 558
Cache Data Storage (lower word) (FMC_DATAW0S0L) 0000_0000h 29.4.9/572 4001_F208 Cache Data Storage (upper word) (FMC_DATAW0S1U) 0000_0000h 29.4.8/571 4001_F20C Cache Data Storage (lower word) (FMC_DATAW0S1L) 0000_0000h 29.4.9/572 Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 559
Cache Data Storage (upper word) (FMC_DATAW1S6U) 0000_0000h 29.4.11/ 4001_F274 Cache Data Storage (lower word) (FMC_DATAW1S6L) 0000_0000h 29.4.10/ 4001_F278 Cache Data Storage (upper word) (FMC_DATAW1S7U) 0000_0000h Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 560
4001_F2C8 Cache Data Storage (upper word) (FMC_DATAW3S1U) 0000_0000h 29.4.15/ 4001_F2CC Cache Data Storage (lower word) (FMC_DATAW3S1L) 0000_0000h 29.4.14/ 4001_F2D0 Cache Data Storage (upper word) (FMC_DATAW3S2U) 0000_0000h Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 562
This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. Prefetching for this master is enabled. Prefetching for this master is disabled. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 563
No access may be performed by this master Only read accesses may be performed by this master Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 564
Only read accesses may be performed by this master Only write accesses may be performed by this master Both read and write accesses may be performed by this master KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 565
Cache way is unlocked and may be displaced Cache way is locked and its contents are not displaced 23–20 Cache Invalidate Way x CINV_WAY[3:0] Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 566
Do not cache data references. Cache data references. Bank 0 Instruction Cache Enable B0ICE This bit controls whether instruction fetches are loaded into the cache. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 567
31–28 This field is reserved. Reserved 27–19 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 568
14-bit tag for cache entry tag[18:5] 4–1 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 1-bit valid for cache entry valid KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 569
14-bit tag for cache entry tag[18:5] 4–1 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 1-bit valid for cache entry valid KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 570
14-bit tag for cache entry tag[18:5] 4–1 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 1-bit valid for cache entry valid KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 571
This section represents data for the upper word (bits [63:32]) of all sets in the indicated way. Address: 4001_F000h base + 200h offset + (8d × i), where i=0d to 7d data[63:32] Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 572
Address: 4001_F000h base + 240h offset + (8d × i), where i=0d to 7d data[63:32] Reset FMC_DATAW1SnU field descriptions Field Description data[63:32] Bits [63:32] of data entry KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 573
Address: 4001_F000h base + 280h offset + (8d × i), where i=0d to 7d data[63:32] Reset FMC_DATAW2SnU field descriptions Field Description data[63:32] Bits [63:32] of data entry KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 574
Address: 4001_F000h base + 2C0h offset + (8d × i), where i=0d to 7d data[63:32] Reset FMC_DATAW3SnU field descriptions Field Description data[63:32] Bits [63:32] of data entry KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 575
• The cache is configured for least recently used (LRU) replacement for all four ways. • The cache is configured for data or instruction replacement. • The single-entry buffer is enabled. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 576
For example, consider the following scenario: • Assume a system with a 4:1 core-to-flash clock ratio and with speculative reads enabled. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 577
[bytes]/(32 or 64)) • Separate control bits for supervisor-only access and execute-only access per segment • Access control evaluated on each bus cycle routed to the flash KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 578
Execute-only Access RegisterPROCESS PH Low 29.5.4.1.2/ See section (x_XACCL) 29.5.4.1.3/ Supervisor-only Access Register High (x_SACCH) See section Supervisor-only Access Register PROCESS PHLow 29.5.4.1.4/ See section (x_SACCL) 29.5.4.1.5/ Configuration Register (x_CR) See section KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 579
Any change made to an NVM location takes effect on the next system reset. The flash basis for the values is signified by x in the reset value. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 580
Reset * Notes: • Pre-programmed flash valuex = Undefined at reset. x_SACCH field descriptions Field Description SA[63:32] Supervisor Access Control for segments 63-32 KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 581
The NUMSG and SGSIZE values are fixed for a device. The chip-specific basis for the values is signified by * in the reset value. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 583
The next table shows segment assignments relative to the flash location. Table 29-4. Flash Protection Ranges SAn and XAn Protected Segment Address Range Segment Size (Fraction of total Flash) 64 Segment Encodings Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 584
Figure 29-1. Program flash protection (64 segments) 29.5.4.2.1 Interface Signals Table 29-5. Interface Signals Signal Width From Description xacc 64 or 32 Platform Direct xacc (execute-only access control) register Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 585
SWAP system being uninitialized. The SWAP command must be run with the initialization code to set the SWAP indicator address and initialize the SWAP system. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 586
Therefore, if we at the factory are sending pre-loaded code to another vendor, then that vendor will have access to our factory code. NDAs and legal agreements might help deal with this issue. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 588
FMC's cache might need to be disabled and/or flushed to prevent the possibility of returning stale data. Use the PFB0CR[CINV_WAY] field to invalidate the cache in this manner. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 589
('1') states and/or programmed ('0') states. Therefore, it is recommended that each flash block or sector be re-erased immediately prior to factory programming to ensure that the full data retention capability is achieved. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 590
• Supports MCU security mechanisms which prevent unauthorized access to the flash memory contents 30.1.2 Block Diagram The block diagram of the flash memory module is shown in the following figure. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 591
Longword — 32 bits of data with an aligned longword having byte-address[1:0] = 00. NVM — Nonvolatile memory. A memory technology that maintains stored data during power-off. The flash array is an NVM using NOR-type flash memory technology. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 592
This section describes the memory map and registers for the flash memory module. Data read from unimplemented memory space in the flash memory module is undefined. Writes to unimplemented or reserved memory space (registers) in the flash memory module are ignored. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 593
0x00 – 0x9F Reserved 0xA0 – 0xA3 Program Once XACCH-1 Field (index = 0x10) 0xA4 – 0xA7 Program Once XACCL-1 Field (index = 0x10) Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 594
CCIF. During this initialization period the user may write any register. All register writes are also disabled (except for registers FCNFG and FSTAT) whenever an erase suspend request is active (FCNFG[ERSSUSP]=1). KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 595
Undefined 30.3.3.6/ 4002_0013 Program Flash Protection Registers (FTFA_FPROT0) Undefined 30.3.3.7/ 4002_0018 Execute-only Access Registers (FTFA_XACCH3) Undefined 30.3.3.7/ 4002_0019 Execute-only Access Registers (FTFA_XACCH2) Undefined Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 596
MGSTAT0 bit is read only. The unassigned bits read 0 and are not writable. NOTE When set, the Access Error (ACCERR) and Flash Protection Violation (FPVIOL) bits in this register prevent the launch of KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 597
This field is reserved. Reserved This read-only field is reserved and always has the value 0. Memory Controller Command Completion Status Flag MGSTAT0 Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 598
ERSAREQ sets when an erase all request is triggered external to the flash memory module and CCIF is set (no command is currently being executed). ERSAREQ is cleared by the flash memory module when the operation completes. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 599
= Undefined at reset. FTFA_FSEC field descriptions Field Description 7–6 Backdoor Key Security Enable KEYEN Enables or disables backdoor key access to the flash memory module. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 600
NVM at reset. The function of the bits is defined in the device's Chip Configuration details. All bits in the register are read-only . KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 601
Some commands return information to the FCCOB registers. Any values returned to FCCOB are available for reading after the FSTAT[CCIF] flag returns to 1 by the memory controller. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 602
KB of program flash where each assigned bit protects 2 KB . For configurations with 48 KB of program flash memory or less, FPROT0 is not used. For configurations with 32 KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 603
1 and protected regions use a 0, only writes changing 1s to 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with 0-to-1 transitions are ignored. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 604
Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 0xA5 0xAD Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 605
SACCL3 SA[7:0] During the reset sequence, the SACC registers are loaded with the logical AND of Program Flash IFR addresses A and B as indicated in the following table. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 606
All bits in the register are read-only. The contents of this register are loaded during the reset sequence. Address: 4002_0000h base + 28h offset = 4002_0028h Read SGSIZE Write Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 607
Program flash memory is divided into 32 segments (64 Kbytes, 128 Kbytes) 0x28 Program flash memory is divided into 40 segments (160 Kbytes) 0x4x Program flash memory is divided into 64 segments (256 Kbytes, 512 Kbytes) KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 608
Flash protection features are discussed further in AN4507: Using the Kinetis Security and Flash Protection Features . Not all features described in the application note are available on this device. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 609
• FTFA_SACC — • For 2 program flash sizes greater than 128KB, eight registers control 64 segments of the program flash memory as shown in the following figure KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 610
Some devices also generate a bus error response as a result of a Read Collision Error event. See the chip configuration information to determine if a bus error response is also supported. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 611
Chip Configuration details of this device for how to activate each mode. 30.4.6 Flash Reads and Ignored Writes The flash memory module requires only the flash address to execute a flash memory read. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 612
Flash commands are specified using a command write sequence illustrated in Figure 30-5. The flash memory module performs various checks on the command (FCCOB) content and continues with command execution if all requirements are fulfilled. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 613
Program and erase commands also check the address to determine if the operation is requested to execute on protected areas. If the protection check fails, FSTAT[FPVIOL] (protection error) flag is set. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 614
FCCOB and FSTAT registers. 4. The flash memory module sets FSTAT[CCIF] signifying that the command has completed. The flow for a generic command write sequence is illustrated in the following figure. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 615
Program flash Function 0x01 Read 1s Section × Verify that a given number of program flash locations from a starting address are erased. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 616
(XA) segments then release flash access control. 30.4.9.3 Flash Commands by Mode The following table shows the flash commands that can be executed in each flash operating mode. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 617
(number of times a bit is erased and re-programmed). The lifetime of the erased states is relative to the last erase operation. The lifetime of the programmed states is measured from the last program time. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 618
Do not attempt to read a flash block while the flash memory module is running a command (FSTAT[CCIF] = 0) on that same block. The flash memory module may return invalid data to the MCU with the collision error flag (FSTAT[RDCOLERR]) set. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 619
Error bit Command not available in current mode/security FSTAT[ACCERR] An invalid margin code is supplied. FSTAT[ACCERR] An invalid flash address is supplied. FSTAT[ACCERR] Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 620
• Byte 2 data is programmed to byte address start+0b01, • Byte 1 data is programmed to byte address start+0b10, • Byte 0 data is programmed to byte address start+0b11. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 621
Flash address [23:16] Flash address [15:8] Flash address [7:0] Returned Values Read Data [31:24] Read Data [23:16] Read Data [15:8] Read Data [7:0] User-provided values Resource Select Code (see Table 30-10) KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 622
0s to 0 is not allowed as this overstresses the device. Table 30-12. Program Longword Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0x06 (PGM4) Flash address [23:16] Flash address [15:8] Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 623
Any errors have been encountered during the verify operation FSTAT[MGSTAT0] 30.4.11.5 Erase Flash Sector Command The Erase Flash Sector operation erases all addresses in a flash sector. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 624
If an Erase Flash Sector operation effectively completes before the flash memory module detects that a suspend request has been made, the flash memory module clears the ERSSUSP bit prior to setting CCIF. When an Erase Flash Sector operation has been KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 625
Data in this sector is not reliable until a new erase command fully completes. The following figure shows how to suspend and resume the Erase Flash Sector operation. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 626
ERSSCR Suspended Resume Erase? ERSSUSP: Bit in FCNFG register No, Abort SUSPACK: Internal Suspend Acknowledge Clear ERSSUSP User Cmd Interrupt/Suspend Figure 30-6. Suspend and Resume of Erase Flash Sector Operation KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 627
Table 30-18. Read 1s All Blocks Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid margin choice is specified FSTAT[ACCERR] Read-1s fails FSTAT[MGSTAT0] KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 628
The Read Once command can be executed any number of times. Table 30-20. Read Once Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid record index is supplied FSTAT[ACCERR] KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 629
Command not available in current mode/security FSTAT[ACCERR] An invalid record index is supplied FSTAT[ACCERR] The requested record has already been programmed to a non-FFFF value FSTAT[ACCERR] Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 630
Error Bit Command not available in current mode/security FSTAT[ACCERR] Any region of the program flash memory is protected FSTAT[FPVIOL] Any errors have been encountered during the verify operation FSTAT[MGSTAT0] KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 632
FCCOB Contents [7:0] 0x49 (ERSALLU) After clearing CCIF to launch the Erase All Blocks Unsecure command, the flash memory module erases all program flash memory, then verifies that all are erased. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 633
: • sets the read margin for 1s according to Table 30-30, • checks the contents of the program flash execute-only segments are in the erased state. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 634
If the flash memory module verifies that all segments were properly erased, flash access control is disabled until the next reset or, after programming any of the execute-only segments, the Read 1s All Execute-only Segments command is executed and fails with KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 635
. Note that not all features described in the application note are available on this device. Table 30-34. FSEC register fields FSEC field Description KEYEN Backdoor Key Access MEEN Mass Erase Capability FSLACC Factory Security Level Access MCU security KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 636
The user code stored in the program flash memory must have a method of receiving the backdoor keys from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 637
If a reset occurs while any flash command is in progress, that command is immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. Commands and operations do not automatically resume after exiting reset. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 639
• Option for inversion of final CRC result • 32-bit CPU register programming interface 31.1.2 Block diagram The following is a block diagram of the CRC. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 640
Register name Access Reset value (in bits) page (hex) 4003_2000 CRC Data register (CRC_DATA) FFFF_FFFFh 31.2.1/641 4003_2004 CRC Polynomial register (CRC_GPOLY) 0000_1021h 31.2.2/642 4003_2008 CRC Control register (CRC_CTRL) 0000_0000h 31.2.3/642 KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 641
When CTRL[WAS] is 1, values written to this field are part of the seed value. When CTRL[WAS] is 0, data written to this field is used for CRC checksum generation. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 642
CRC calculation. A new CRC calculation is initialized by asserting CTRL[WAS] and then writing the seed into the CRC data register. Address: 4003_2000h base + 8h offset = 4003_2008h TOTR FXOR WAS Reset Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 643
Width of CRC protocol. TCRC 16-bit CRC protocol. 32-bit CRC protocol. Reserved This field is reserved. This read-only field is reserved and always has the value 0. 31.3 Functional description KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 644
8. When all values have been written, read the final CRC result from CRC_DATA[LU:LL]. Transpose and complement operations are performed on the fly while reading or writing values. See Transpose feature CRC result complement for details. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 645
CTRL[TOT] or CTRL[TOTR] fields, according to the CRC calculation being used. The following types of transpose functions are available for writing to and reading from the CRC data register: 1. CTRL[TOT] or CTRL[TOTR] is 00. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 646
= {reg[0:7], reg[8:15],reg[16:23], reg[24:31]} Figure 31-3. Transpose type 10 4. CTRL[TOT] or CTRL[TOTR] is 11. Bytes are transposed, but bits are not transposed. reg[31:0] becomes {reg[7:0], reg[15:8], reg[23:16], reg[31:24]} KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 647
CRC data register every time the CRC data register is read. When CTRL[FXOR] is cleared, reading the CRC data register accesses the raw checksum value. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 649
RNGA as quickly as the hardware allows, there are about one or two bits of added entropy per 32-bit word. Any single bit of that word contains that KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 650
The ring-oscillator clocks are inactive; RNGA does not generate entropy. 32.2.1 Entering Normal mode To enter Normal mode, write 0 to CR[SLP]. 32.2.2 Entering Sleep mode To enter Sleep mode, write 1 to CR[SLP]. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 651
This read-only field is reserved and always has the value 0. Sleep Specifies whether RNGA is in Sleep or Normal mode. NOTE: You can also enter Sleep mode by asserting the DOZE signal. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 652
Specifies whether random-data generation and loading (into OR[RANDOUT]) is enabled. NOTE: This field is sticky. You must reset RNGA to stop RNGA from loading OR[RANDOUT] with data. Disabled Enabled KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 653
NOTE: If you read OR[RANDOUT] when SR[OREG_LVL] is not 0, then the contents of a random number contained in OR[RANDOUT] are returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL]. No words (empty) One word (valid) Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 654
Used only when high assurance is enabled (CR[HA]). Indicates that a security violation has occurred. NOTE: This field is sticky. To clear SR[SECV], you must reset RNGA. No security violation Security violation KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 655
RNG_OR field descriptions Field Description RANDOUT Random Output Stores a random-data word generated by RNGA. This is a read-only field. NOTE: Before reading RANDOUT, be sure it is valid (SR[OREG_LVL]=1). KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 656
OR when it is empty, RNGA returns all zeros and, if the interrupt is enabled, RNGA drives a request to the interrupt controller. Polling SR[OREG_LVL] is very important to make sure random values are present before reading from OR. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 657
3. Poll SR[OREG_LVL] until it is not 0. 4. When SR[OREG_LVL] is not 0, read the available random data from OR[RANDOUT]. 5. Repeat steps 3 and 4 as needed. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 658
Initialization/application information For application information, see Overview. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 659
DMA (via DMA req) on conversion completion. 33.1.3 ADCx Connections/Channel Assignment NOTE As indicated by the following sections, each ADCx_DPx input and certain ADCx_DMx inputs may operate as single-ended ADC channels in single-ended mode. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 660
Reserved 11001 AD25 Reserved Reserved 11010 AD26 Temperature Sensor (Diff) Temperature Sensor (S.E) 11011 AD27 Bandgap (Diff) Bandgap (S.E) 11100 AD28 Reserved Reserved Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 662
ADCx_SE6b ADCx_SE7b Figure 33-1. ADCx_SEn channels a and b selection 33.1.5 ADC Reference Options The ADC supports the following references: • VREFH/VREFL - connected as the primary reference option KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 664
Note however that ALTCLK2 is force disabled and therefore not available in VLPS. 33.1.9 ADC low-power modes This table shows the ADC low-power modes and the corresponding chip low-power modes. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 665
• Input clock selectable from up to four sources • Operation in low-power modes for lower noise • Asynchronous clock source for lower noise operation with option to output the clock KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 666
• Temperature sensor • Hardware average function • Selectable voltage reference: external or alternate • Self-Calibration mode 33.2.2 Block diagram The following figure is the ADC module block diagram. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 668
The ADC module supports up to 4 pairs of differential inputs and up to 24 single-ended inputs. Each differential pair requires two inputs, DADPx and DADMx. The ADC also requires four supply/reference/ground connections. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 669
. The two pairs are external (V and V ) and alternate (V and V REFH REFL ALTH ALTL These voltage references are selected using SC2[REFSEL]. The alternate V ALTH KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 670
ADC Configuration Register 1 (ADC0_CFG1) 0000_0000h 33.4.2/675 4003_B00C ADC Configuration Register 2 (ADC0_CFG2) 0000_0000h 33.4.3/676 4003_B010 ADC Data Result Register (ADC0_RA) 0000_0000h 33.4.4/677 Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 671
ADC Minus-Side General Calibration Value Register 33.4.24/ 4003_B06C 0000_0020h (ADC0_CLM0) 33.4.1 ADC Status and Control Registers 1 (ADCx_SC1n) SC1A is used for both software and hardware trigger modes of operation. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 672
SC1B–SC1n registers do not initiate a new conversion. Address: 4003_B000h base + 0h offset + (4d × i), where i=0d to 1d Reset AIEN DIFF ADCH Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 673
When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. 00111 When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 674
Voltage reference selected is determined by SC2[REFSEL]. 11110 When DIFF=0,V is selected as input; when DIFF=1, it is reserved. Voltage reference REFSL selected is determined by SC2[REFSEL]. 11111 Module is disabled. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 675
When ADLSMP=1, the long sample time select bits, (ADLSTS[1:0]), can select the extent of the long sample time. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 676
Configuration Register 2 (CFG2) selects the special high-speed configuration for very high speed conversions and selects the long sample time duration during long sample mode. Address: 4003_B000h base + Ch offset = 4003_B00Ch Reset ADLSTS Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 677
The data result registers (Rn) contain the result of an ADC conversion of the channel selected by the corresponding status and channel control register (SC1A:SC1n). For every status and channel control register, there is a corresponding data result register. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 678
Address: 4003_B000h base + 10h offset + (4d × i), where i=0d to 1d Reset ADCx_Rn field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Data result KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 679
Address: 4003_B000h base + 18h offset + (4d × i), where i=0d to 1d Reset ADCx_CVn field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Compare Value. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 680
Conversion in progress. Conversion Trigger Select ADTRG Selects the type of trigger used for initiating a conversion. Two types of trigger are selectable: Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 681
. This pair may be additional external pins or ALTH ALTL internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU Reserved Reserved KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 682
ADC register is written, or any stop mode is entered before the calibration sequence completes. Writing 1 to CALF clears it. Calibration completed normally. Calibration failed. ADC accuracy specifications are not guaranteed. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 683
For more information regarding the calibration procedure, please refer to the Calibration function section. Address: 4003_B000h base + 28h offset = 4003_B028h Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 684
MG[15] and MG[14]. This register must be written by the user with the value described in the calibration procedure. Otherwise, the gain error specifications may not be met. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 685
CLPD Reset ADCx_CLPD field descriptions Field Description 31–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CLPD Calibration Value Calibration Value KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 686
CLP4 Reset ADCx_CLP4 field descriptions Field Description 31–10 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CLP4 Calibration Value Calibration Value KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 687
CLP2 Reset ADCx_CLP2 field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CLP2 Calibration Value Calibration Value KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 688
CLP0 Reset ADCx_CLP0 field descriptions Field Description 31–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CLP0 Calibration Value Calibration Value KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 689
Calibration Value Calibration Value 33.4.19 ADC Minus-Side General Calibration Value Register (ADCx_CLMS) For more information, see CLMD register description. Address: 4003_B000h base + 58h offset = 4003_B058h CLMS Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 690
Reset ADCx_CLM3 field descriptions Field Description 31–9 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 691
CLM1 Reset ADCx_CLM1 field descriptions Field Description 31–7 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CLM1 Calibration Value Calibration Value KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 692
The ADC module has the capability of automatically comparing the result of a conversion with the contents of the CV1 and CV2 registers. The compare function is enabled by setting SC2[ACFE] and operates in any of the conversion modes and configurations. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 693
If the available clocks are too fast, the clock must be divided to the appropriate frequency. This divider is specified by CFG1[ADIV] and can be divide-by 1, 2, 4, or 8. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 694
ADHWT signal to trigger a new conversion. The channel and status fields selected for the conversion depend on the active trigger select signal: • ADHWTSA active selects SC1A. • ADHWTSn active selects SC1n. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 695
SC2[ADTRG]=1, and a hardware trigger select event, ADHWTSn, has occurred. The channel and status fields selected depend on the active trigger select signal: • ADHWTSA active selects SC1A. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 696
SC1n[COCO] sets only if the last of the selected number of conversions is completed and the compare condition is true. An interrupt is generated if the respective SC1n[AIEN] is high at the time that the respective SC1n[COCO] is set. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 697
CFG2[ADACKEN]=1, it remains active regardless of the state of the ADC or the MCU power mode. Power consumption when the ADC is active can be reduced by setting CFG1[ADLPC]. This results in a lower maximum value for f ADCK KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 698
3. The result of the conversion is transferred to Rn upon completion of the conversion algorithm. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 700
• 10-bit mode, with the bus clock selected as the input clock source • The input clock divide-by-1 ratio selected • Bus frequency of 8 MHz • Long sample time disabled • High-speed conversion disabled KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 701
Equation 1 on page 699. Table 33-14. Typical conversion time Variable Time SFCAdder 3 ADCK cycles + 5 bus clock cycles AverageNum 34 ADCK cycles LSTAdder 20 ADCK cycles HSCAdder KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 702
When hardware averaging is selected, the completion of a single conversion will not set SC1n[COCO]. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 703
CV2. Greater than Outside range, inclusive Compare true if the result is greater than or equal to CV1 Or the result is less than or equal to CV2. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 704
Prior to calibration, the user must configure the ADC's clock source and frequency, low power configuration, voltage reference selection, sample time, and high speed configuration according to the application's clock source availability and needs. If the KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 705
When calibration is complete, the user may reconfigure and use the ADC as desired. A second calibration may also be performed, if desired, by clearing and again setting SC3[CAL]. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 706
ADC error specifications may not be met. Storing the value generated by the calibration function in memory before overwriting with a user- specified value is recommended. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 707
• m is referred as temperature sensor slope in the device data sheet. It is the hot or cold voltage versus temperature slope in V/°C. For temperature calculations, use the V and temperature sensor slope values from TEMP25 the ADC Electricals table. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 708
33.5.10 MCU Normal Stop mode operation Stop mode is a low-power consumption Standby mode during which most or all clock sources on the MCU are disabled. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 709
Therefore, the module must be re-enabled and re-configured following exit from Low-Power Stop mode. NOTE For the chip specific modes of operation, see the power management information for the device. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 710
5. Update SC1:SC1n registers to select whether conversions will be single-ended or differential and to enable or disable conversion complete interrupts. Also, select the input channel which can be used to perform conversions. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 711
Bit 4:0 ADCH 00001 Input channel 1 selected as ADC input channel. RA = 0xxx Holds results of conversion. CV = 0xxx Holds compare value when compare function enabled. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 712
33.7.1 External pins and routing 33.7.1.1 Analog supply pins Depending on the device, the analog power and ground supplies, V and V , of the ADC module are available as: KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 713
V and V loop. The REFH REFL best external component to meet this current demand is a 0.1 μF capacitor with good KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 714
RAS + RADIN =SC / (FMAX * NUMTAU * CADIN) Figure 33-4. Sampling equation Where: RAS = External analog source resistance SC = Number of ADCK cycles used during sample window KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 715
REFL plane. • Operate the MCU in Wait or Normal Stop mode before initiating (hardware-triggered conversions) or immediately after initiating (hardware- or software-triggered conversions) the ADC conversion. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 716
12-bit modes. As a consequence, however, the code width of the first (0x000) conversion is only 1/2 LSB and the code width of the last (0xFF or 0x3FF) is 1.5 LSB. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 717
However, even small amounts of system noise can cause the converter to be indeterminate, between two codes, for a range of input voltages around the transition voltage. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 718
• Missing codes: Missing codes are those values never converted for any input value. In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and have no missing codes. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 719
PMC_REGSC[BGBE] bit. Refer to the device data sheet for the bandgap voltage (V ) specification. 34.1.2 CMP external references The 6-bit DAC sub-block supports only one reference as follows: • VDD - V input • VDD - V input KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 720
V and V . The 6-bit DAC from a comparator is available as an on-chip internal signal only and is not available externally to a pin. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 721
• The window and filter functions are not available in the following modes: • Stop • VLPS • LLS • VLLSx 34.2.2 6-bit DAC key features The 6-bit DAC has the following features: • 6-bit resolution KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 722
• Two 8-to-1 channel mux • Operational over the entire supply range 34.2.4 CMP, DAC and ANMUX diagram The following figure shows the block diagram for the High-Speed Comparator, DAC, and ANMUX modules. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 723
ANMUX and filter control CMPO MSEL[2:0] Figure 34-1. CMP, DAC and ANMUX block diagram 34.2.5 CMP block diagram The following figure shows the block diagram for the CMP module. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 724
CR0[FILTER_CNT] is set greater than 0x01. • If CR1[SE] = 1, the external SAMPLE input is used as sampling clock • If CR1[SE] = 0, the divided bus clock is used as sampling clock KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 725
One sample must agree. The comparator output is simply sampled. 2 consecutive samples must agree. 3 consecutive samples must agree. 4 consecutive samples must agree. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 726
CMP and DAC are configured to CMP Trigger mode when CMP_CR1[TRIGM] is set to 1. In addition, the CMP should be enabled. If the DAC is to be used as a reference to the CMP, it should also be enabled. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 727
When the user selects the same input from analog mux to the positive and negative port, the comparator is disabled automatically. Analog Comparator is disabled. Analog Comparator is enabled. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 728
Comparator Interrupt Enable Rising Enables the CFR interrupt from the CMP. When this field is set, an interrupt will be asserted when CFR is set. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 729
Enables the DAC. When the DAC is disabled, it is powered down to conserve power. DAC is disabled. DAC is enabled. Supply Voltage Reference Source Select VRSEL Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 730
NOTE: When an inappropriate operation selects the same input for both muxes, the comparator automatically shuts down to prevent itself from becoming a noise generator. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 731
The external sample input is enabled using CR1[SE]. When set, the output of the comparator is sampled only on rising edges of the sample input. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 732
SAMPLE=1 to generate COUTA, which is then resampled and filtered to generate COUT. See the Windowed/Filtered mode (#7). All other combinations of CR1[EN], CR1[WE], CR1[SE], CR0[FILTER_CNT], and FPR[FILT_PER] are illegal. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 733
CMPO COUT To other system functions WINDOW/SAMPLE bus clock Clock COUTA CMPO to prescaler divided FILT_PER CGMUX clock Figure 34-3. Comparator operation in Continuous mode KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 734
In Sampled, Non-Filtered mode, the analog comparator block is powered and active. The path from analog inputs to COUTA is combinational unclocked. Windowing control is completely bypassed. COUTA is sampled whenever a rising-edge is detected on the filter block clock input. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 735
COUTA is sampled whenever a rising edge is detected on the filter block clock input. The only difference in operation between Sampled, Non-Filtered (# 3A) and Sampled, Filtered (# 4A) is that, now, CR0[FILTER_CNT]>1, which activates filter operation. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 736
CMPO COUT To other SOC functions WINDOW/SAMPLE bus clock Clock COUTA CMPO to prescaler divided FILT_PER CGMUX clock SE=1 Figure 34-6. Sampled, Filtered (# 4A): sampling point externally driven KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 737
WINDOW signal is high. In actual operation, COUTA may lag the analog inputs by up to one bus clock cycle plus the combinational path delay through the comparator and polarity select logic. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 738
Clock CMPO to divided prescaler FILT_PER CGMUX clock SE=0 Figure 34-9. Windowed mode For control configurations which result in disabling the filter block, see Filter Block Bypass Logic diagram. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 739
Configuration for this mode is virtually identical to that for the Windowed/Filtered Mode shown in the next section. The only difference is that the value of CR0[FILTER_CNT] must be 1. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 740
Figure 34-11. Windowed/Filtered mode 34.4.2 Power modes 34.4.2.1 Wait mode operation During Wait and VLPW modes, the CMP, if enabled, continues to operate normally and a CMP interrupt can wake the MCU. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 741
The filter delay is specified in the Low-pass filter. • During operation, the propagation delay of the selected data paths must always be considered. It may take many bus clock cycles for COUT and SCR[CFR]/SCR[CFF] KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 742
In other words, SCR[COUT] will be 0 for some initial period, even when COUTA is at logic 1. Setting both CR1[SE] and FPR[FILT_PER] to 0 disables the filter and eliminates switching current associated with the filtering process. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 743
Sampled, Filtered mode + (CR0[FILTER_CNT] * ) + T SAMPLE > 0x01 > 0x00 + (CR0[FILTER_CNT] * FPR[FILT_PER] x T ) + T Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 744
DMA transfer request and clears the flag to allow a subsequent change on comparator output to occur and force another DMA request. The comparator can remain functional in STOP modes. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 745
STOP modes. After the data transfer has finished, system will go back to STOP modes. Refer to DMA chapters in the device reference manual for the asynchronous DMA function for details. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 746
34.9.1 Voltage reference source select • V connects to the primary voltage source as supply reference of 64 tap resistor ladder • V connects to an alternate voltage source KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 747
This module has a single reset input, corresponding to the chip-wide peripheral reset. 34.11 DAC clocks This module has a single clock input, the bus clock. 34.12 DAC interrupts This module has no interrupts. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 749
The 12-bit digital-to-analog converter (DAC) is a low-power, general-purpose DAC. The output of the DAC can be placed on an external pin or set as one of the inputs to the analog comparator, op-amps, or ADC. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 750
• Static operation in Normal Stop mode • 16-word data buffer supported with configurable watermark and multiple operation modes • DMA support 35.4 Block diagram The block diagram of the DAC module is as follows: KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 751
DACBBIEN DACBFMD DACTRGSE Figure 35-1. DAC block diagram 35.5 Memory map/register definition The DAC has registers to control analog comparator and programmable voltage divider to perform the digital-to-analog functions. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 752
DAC Data High Register (DAC0_DAT15H) 35.5.2/753 4003_F020 DAC Status Register (DAC0_SR) 35.5.3/754 4003_F021 DAC Control Register (DAC0_C0) 35.5.4/755 4003_F022 DAC Control Register 1 (DAC0_C1) 35.5.5/756 4003_F023 DAC Control Register 2 (DAC0_C2) 35.5.6/757 KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 753
When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage based on the following formula. V * (1 + DACDAT0[11:0])/4096 When the DAC buffer is enabled, DATA[11:0] is mapped to the 16-word buffer. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 754
DAC trigger making the DAC read pointer increase. Write to this bit is ignored in FIFO mode. The DAC buffer read pointer is not equal to C2[DACBFUP]. The DAC buffer read pointer is equal to C2[DACBFUP]. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 755
The DAC buffer read pointer top flag interrupt is disabled. The DAC buffer read pointer top flag interrupt is enabled. DAC Buffer Read Pointer Bottom Flag Interrupt Enable DACBBIEN Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 756
Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 757
When both the DAC and the buffer are enabled, the DAC converts the data in the data buffer to analog output voltage. The data buffer read pointer advances to the next word whenever a hardware or software trigger event occurs. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 758
FIFO access, address bit[1] needs to be 0; otherwise, the write is ignored. For any 32bit FIFO access, the Write_Pointer needs to be an EVEN number; otherwise, the write is ignored. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 759
During reset, the DAC is configured in the default mode and is disabled. 35.6.4 Low-Power mode operation The following table shows the wait mode and the stop mode operation of the DAC module. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 760
In low-power stop modes, the DAC is fully shut down. NOTE The assignment of module modes to core modes is chip- specific. For module-to-core mode assignments, see the chapter that describes how modules are configured. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 762
• PDB channel 0 trigger/pre-trigger 0 acknowledgement input: ADC0SC1B_COCO • PDB channel 0 trigger/pre-trigger 1 acknowledgement input: ADC0SC1A_COCO So, the back-to-back chain is connected as a ring: KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 763
The following table shows the comparison of pulse-out enable register at the module and chip level. Table 36-3. PDB pulse-out enable register Register Module implementation Chip implementation POnEN 7:0 - POEN 31:8 - Reserved KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 764
• One channel flag and one sequence error flag per pre-trigger • DMA support • Up to 8 pulse outputs (pulse-out's) • Pulse-out's can be enabled or disabled independently • Programmable pulse width KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 765
PDB back-to-back operation acknowledgment connections are chip-specific. For implementation, see the chip configuration information. 36.2.4 DAC External Trigger Input Connections The implementation of DAC external trigger inputs is chip-specific. See the chip configuration information for details. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 767
36.3.2/771 4003_6008 Counter register (PDB0_CNT) 0000_0000h 36.3.3/772 4003_600C Interrupt Delay register (PDB0_IDLY) 0000_FFFFh 36.3.4/772 4003_6010 Channel n Control register 1 (PDB0_CH0C1) 0000_0000h 36.3.5/773 Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 768
Reset PDBx_SC field descriptions Field Description 31–20 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 769
Selects the trigger input source for the PDB. The trigger input source can be internal or external (EXTRG pin), or the software trigger. Refer to chip configuration details for the actual PDB input trigger connections. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 770
Continuous Mode Enable CONT Enables the PDB operation in Continuous mode. PDB operation in One-Shot mode PDB operation in Continuous mode Load OK LDOK Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 771
Specifies the period of the counter. When the counter reaches this value, it will be reset back to zero. If the PDB is in Continuous mode, the count begins anew. Reading this field returns the value of the internal register that is effective for the current cycle of PDB. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 772
PDB cycle. If enabled, a PDB interrupt is generated, when the counter is equal to the IDLY. Reading this field returns the value of internal register that is effective for the current cycle of the PDB. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 773
PDB Channel Pre-Trigger Enable Enables the PDB ADC pre-trigger outputs. Only lower M pre-trigger fields are implemented in this MCU. PDB channel's corresponding pre-trigger disabled. PDB channel's corresponding pre-trigger enabled. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 774
The value in this register's internal buffer is loaded into this register only after "1" is written to the SC[LDOK] bit. Address: 4003_6000h base + 18h offset + (40d × i), where i=0d to 0d Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 775
These bits specify the delay value for the channel's corresponding pre-trigger. The pre-trigger asserts when the counter is equal to DLY. Reading these bits returns the value of internal register that is effective for the current PDB cycle. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 776
The value in this register's internal buffer is loaded into this register only after "1" is written to the SC[LDOK] bit. Address: 4003_6000h base + 154h offset + (8d × i), where i=0d to 0d Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 777
The value in this register's internal buffer is loaded into this register only after "1" is written to the SC[LDOK] bit. Address: 4003_6000h base + 194h offset + (4d × i), where i=0d to 0d DLY1 DLY2 Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 778
When a pre-trigger m is asserted, the ADC conversion is triggered with set m of the configuration and result registers. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 779
If SC[PDBEIE] is set, then the sequence error interrupt is generated. A sequence error typically happens because the delay m is set too short and the pre-trigger m asserts before the previously triggered ADC conversion finishes. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 780
ADC pre-trigger/trigger outputs and Pulse-Out generation have the same time base, because they both share the PDB counter. The pulse-out connections implemented in this MCU are described in the device's chip configuration details. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 782
The following diagrams show the cases of the internal registers being updated with SC[LDMOD] is 00 and x1. CHnDLY1 CHnDLY0 PDB counter SC[LDOK] Ch n pre-trigger 0 Ch n pre-trigger 1 Figure 36-5. Registers update with SC[LDMOD] = 00 KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 783
36.4.6 DMA If SC[DMAEN] is set, PDB can generate a DMA transfer request when SC[PDBIF] is set. When DMA is enabled, the PDB interrupt is not issued. 36.5 Application information KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 784
If the applications need a really long delay value and use a prescaler set to 128, then the resolution would be limited to 128 peripheral clock cycles. Therefore, use the lowest possible prescaler and multiplication factor for a given application. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 785
As there are only 2 channels (channel 0-1) available on TPM1/ TPM2, channel 2-5 related registers (such as Status and Control register, Value register) are not applicable for TPM1/TPM2 on this device. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 787
• TPM clock mode is selectable • Can increment on every edge of the asynchronous counter clock • Can increment on rising edge of an external clock input synchronized to the asynchronous counter clock KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 788
During stop mode, the TPM counter clock can remain functional and the TPM can generate an asynchronous interrupt to exit the MCU from stop mode. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 789
(generation of channel N outputs signals in output signal output compare, EPWM and CPWM modes) Figure 37-1. TPM block diagram 37.3 TPM Signal Descriptions Table 37-3 shows the user-accessible signals for the TPM. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 790
TPM Global Register (TPM0_GLOBAL) 0000_0000h 37.4.3/794 4003_8010 Status and Control (TPM0_SC) 0000_0000h 37.4.4/795 4003_8014 Counter (TPM0_CNT) 0000_0000h 37.4.5/796 4003_8018 Modulo (TPM0_MOD) 0000_FFFFh 37.4.6/797 Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 791
4003_9034 Channel (n) Value (TPM1_C2V) 0000_0000h 37.4.9/801 4003_9038 Channel (n) Status and Control (TPM1_C3SC) 0000_0000h 37.4.8/799 4003_903C Channel (n) Value (TPM1_C3V) 0000_0000h 37.4.9/801 Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 792
Channel (n) Status and Control (TPM2_C5SC) 0000_0000h 37.4.8/799 4003_A04C Channel (n) Value (TPM2_C5V) 0000_0000h 37.4.9/801 37.4.10/ 4003_A064 Combine Channel Register (TPM2_COMBINE) 0000_0000h 37.4.11/ 4003_A06C Channel Trigger (TPM2_TRIG) 0000_0000h Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 793
Standard feature set with Filter and Combine registers implemented. 0x0007 Standard feature set with Filter, Combine and Quadrature registers implemented. 37.4.2 Parameter Register (TPMx_PARAM) Address: Base address + 4h offset WIDTH TRIG CHAN Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 794
Reset all internal logic and registers, except the Global Register. Remains set until cleared by software. Module is not reset. Module is reset. This field is reserved. Reserved This read-only field is reserved and always has the value 0. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 795
TOF remains set indicating another overflow has occurred. In this case a TOF interrupt request is not lost due to a delay in clearing the previous TOF. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 796
When debug is active, the TPM counter does not increment unless configured otherwise. Reading the CNT register adds two wait states to the register access due to synchronization delays. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 797
This field must be written with single 16-bit or 32-bit access. 37.4.7 Capture and Compare Status (TPMx_STATUS) The STATUS register contains a copy of the status flag, CnSC[CHnF] for each TPM channel, as well as SC[TOF], for software convenience. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 798
This field is reserved. Reserved This read-only field is reserved and always has the value 0. Channel 5 Flag CH5F See the register description. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 799
Table 37-4. Mode, Edge, and Level Selection CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration None Channel disabled Software compare Pin not used for TPM Input capture Capture on Rising Edge Only Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 800
TPMx_CnSC field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Channel Flag Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 801
CnV Register Update Additional writes to the CnV write buffer are ignored until the register has been updated. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 802
This field is reserved. Reserved This read-only field is reserved and always has the value 0. Combine Channels 4 and 5 Swap COMSWAP2 Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 803
In PWM modes, the even channel match is used for the 1st compare and odd channel match for the 2nd compare. Channels 0 and 1 are independent. Channels 0 and 1 are combined. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 804
The input trigger is used for input capture and modulates output (for output compare and PWM). Channel 0 Trigger TRIG0 No effect. The input trigger is used for input capture and modulates output (for output compare and PWM). KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 805
POL1 The channel polarity is active high. The channel polarity is active low. Channel 0 Polarity POL0 The channel polarity is active high. The channel polarity is active low. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 806
Selects the filter value for the channel input and the delay value for the channel output. The filter/delay is disabled when the value is zero, otherwise the filter/delay is configured as (CH0FVAL * 4) clock cycles. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 807
Selects the encoding mode used in the quadrature decoder mode. Phase encoding mode. Count and direction encoding mode. Counter Direction in Quadrature Decode Mode QUADIR Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 808
Reset TPMx_CONF field descriptions Field Description 31–28 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 809
When enabled, the counter will pause incrementing while the trigger remains asserted (level sensitive). This field should only be changed when the TPM counter is disabled. Counter Reload On Trigger CROT Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 810
Global timebase synchronization disabled. Global timebase synchronization enabled. 7–6 Debug Mode DBGMODE Configures the TPM behavior in debug mode. All other configurations are reserved. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 811
CMOD[1:0] bits does not affect the TPM counter value or other registers, but must be acknowledged by the TPM counter clock domain before they read as zero. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 812
The value of zero is loaded into the TPM counter, and the counter increments until the value of MOD is reached, at which point the counter is reloaded with zero. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 813
The TPM period when using up-down counting is 2 × MOD × period of the TPM counter clock. The TOF bit is set when the TPM counter changes from MOD to (MOD – 1). KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 814
The TPM counter can be configured to start, stop or reset in response to a hardware trigger input. The trigger input is synchronized to the asynchronous counter clock, so there is a 3 counter clock delay between the trigger assertion and the counter responding. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 815
4, which is required to meet Nyquist criteria for signal sampling. Writes to the CnV register are ignored in input capture mode. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 816
(logic 0 for set/toggle/pulse high and logic one for clear/ pulse low). The CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1) at the channel (n) match (TPM counter = CnV). KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 817
(n) interrupt is generated (if CHnIE = 1), however the channel (n) output is not modified and controlled by TPM. 37.5.6 Edge-Aligned PWM (EPWM) Mode The edge-aligned mode is selected when (CPWMS = 0), and (MSnB:MSnA = 1:0). KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 818
If (ELSnB:ELSnA = X:1), then the channel (n) output is forced low at the counter overflow (when zero is loaded into the TPM counter), and it is forced high at the channel (n) match (TPM counter = CnV) (see the following figure). KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 819
The other channel modes are not designed to be used with the up-down counter (CPWMS = 1). Therefore, all TPM channels should be used in CPWM mode when (CPWMS = 1). KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 820
(n) match in channel (n) match in down counting up counting down counting channel (n) output CHnF bit previous value TOF bit Figure 37-14. CPWM signal with ELSnB:ELSnA = X:1 KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 821
= C(n)V). It is forced high or low at the channel (n+1) match (TPM counter = C(n+1)V). The channel (n+1) output is generated the same as the channel (n) output, but the output polarity is controlled by the channel (n+1) ELSnB:ELSnA configuration. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 822
C(n)V Zero channel (n) output with ELSnB:ELSnA = X:1 channel (n) output with ELSnB:ELSnA = 1:0 Figure 37-17. Channel (n) output if (C(n)V < MOD) and (C(n+1)V = MOD) KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 824
In the Combine Input Capture mode, only channel (n) input is used and channel (n+1) input is ignored, when COMSWAPn=1 then only channel (n+1) input is used and channel (n) input is ignored. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 825
As long as the new state is stable on the input, the counter continues to increment. When the counter is equal to (CHnFVAL[3:0] × 4), the state change of the input signal is validated. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 826
(TPM counter = C(n)V) occurs, the channel (n) output remains at the high value until the end of the deadtime delay when the channel (n) output is cleared. Similarly, KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 827
0 (phase A) and channel 1 (phase B) input signals to control the TPM counter increment and decrement. The following figure shows the quadrature decoder block diagram. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 828
In this mode, the channel 1 input value indicates the counting direction, and the channel 0 input defines the counting rate. The TPM counter is updated when there is a rising edge at channel 0 input signal. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 829
• there is a rising edge at channel 1 signal and channel 0 signal is at logic zero; • there is a rising edge at channel 0 signal and channel 1 signal is at logic one. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 830
TPM counter changes from zero to MOD, TOF bit is set and TOFDIR bit is cleared. TOF bit indicates the TPM counter overflow occurred. TOFDIR indicates the counting was down when the TPM counter overflow occurred. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 831
• If the selected mode is output compare then CnV register is updated on the next TPM counter increment (end of the prescaler counting) after CnV register was written. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 832
The TPM generates output triggers for the counter and each channel that can be used to trigger events in other peripherals. The counter trigger asserts whenever the TOF is set and remains asserted until the next increment. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 833
The timer overflow interrupt is generated when (TOIE = 1) and (TOF = 1). 37.5.17.2 Channel (n) Interrupt The channel (n) interrupt is generated when (CHnIE = 1) and (CHnF = 1). KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 835
SIM_SOPT7[ADCxTRGSEL] fields. For more details, refer to SIM chapter. 38.2 Introduction The PIT module is an array of timers that can be used to raise interrupts and trigger DMA channels. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 836
The main features of this block are: • Ability of timers to generate DMA trigger pulses • Ability of timers to generate interrupts • Maskable interrupts • Independent timeout periods for each timer KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 837
Timer Load Value Register (PIT_LDVAL3) 0000_0000h 38.4.4/840 4003_7134 Current Timer Value Register (PIT_CVAL3) 0000_0000h 38.4.5/840 4003_7138 Timer Control Register (PIT_TCTRL3) 0000_0000h 38.4.6/841 4003_713C Timer Flag Register (PIT_TFLG3) 0000_0000h 38.4.7/842 KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 838
Disables the standard timers. This field must be enabled before any other setup is done. Clock for standard PIT timers is enabled. Clock for standard PIT timers is disabled. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 839
CVAL1 at the time of the first access, LTMR64L will have the value of CVAL0 at the time of the first access, therefore the application does not need to worry about carry-over effects of the running counter. Access: User read only KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 840
38.4.5 Current Timer Value Register (PIT_CVALn) These registers indicate the current timer position. Access: User read only Address: 4003_7000h base + 104h offset + (16d × i), where i=0d to 3d Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 841
To avoid this, the associated TFLGn[TIF] must be cleared first. Interrupt requests from Timer n are disabled. Interrupt will be requested whenever TIF is set. Timer Enable Enables or disables the timer. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 842
TCTRLn[TIE] = 1, TIF causes an interrupt request. Timeout has not yet occurred. Timeout has occurred. 38.5 Functional description This section provides the functional description of the module. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 843
It is also possible to change the counter period without restarting the timer by writing LDVAL with the new load value. This value will then be loaded after the next trigger event. See the following figure. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 844
(timer 0) cannot be chained to any other timer. 38.6 Initialization and application information In the example configuration: • The PIT clock has a frequency of 50 MHz. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 845
• Timers 1 and 2 are available. • An interrupt shall be raised every 1 minute. The PIT module needs to be activated by writing a 0 to MCR[MDIS]. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 847
PIT_LDVAL0 = 0xFFFFFFFF; // setup timer 0 for maximum counting period PIT_TCTRL0 = TEN; // start timer 0 To access the lifetime, read first LTMR64H and then LTMR64L. current_uptime = PIT_LTMR64H<<32; current_uptime = current_uptime + PIT_LTMR64L; KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 848
Example configuration for the lifetime timer KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 849
LPO — 1 kHz clock (not available in VLLS0 mode) ERCLK32K — secondary external reference clock OSCERCLK_UNDIV — Undivided external reference clock (not available in VLLS0 mode) Clock Distribution for more details on these clocks. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 850
The following table describes the operation of the LPTMR module in various modes. Table 39-1. Modes of operation Modes Description The LPTMR operates normally. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 851
CNR to increment. Timing Assertion or deassertion may occur at any time; input may assert asynchronously to the bus clock. 39.4 Memory map and register definition KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 852
LPTMR is disabled. The input connections vary by device. See the for information on the connections to these inputs. Pulse counter input 0 is selected. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 853
LPTMR is disabled and internal logic is reset. LPTMR is enabled. 39.4.2 Low Power Timer Prescale Register (LPTMRx_PSR) Address: 4004_0000h base + 4h offset = 4004_0004h Reset PRESCALE PBYP Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 854
LPTMR is disabled. The clock connections vary by device. NOTE: See the chip configuration details for information on the connections to these inputs. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 855
Reset LPTMRx_CNR field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 856
NOTE The clock source or pulse input source selected for the LPTMR should not exceed the frequency f defined in the device LPTMR datasheet. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 857
The selected input source remains asserted for at least 2 The glitch filter output will also assert. consecutive prescaler clock rising-edges NOTE The input is only sampled on the rising clock edge. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 858
The CNR continues incrementing when the core is halted in Debug mode when configured for Pulse Counter mode, the CNR will stop incrementing when the core is halted in Debug mode when configured for Time Counter mode. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 859
The LPTMR interrupt is generated asynchronously to the system clock and can be used to generate a wakeup from any low-power mode, including the low-leakage modes, provided the LPTMR is enabled as a wakeup source. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 861
RTC 32kHz clock RTC_CLKOUT RTC 1Hz clock SIM_SOPT2[RTCCLKOUTSEL] Figure 40-1. RTC_CLKOUT generation 40.2 Introduction 40.2.1 Features The RTC module features include: • Independent power supply, POR, and 32 kHz crystal oscillator KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 862
40.2.3.1 RTC clock output The clock to the seconds counter is available on the RTC_CLKOUT signal. It is a 1 Hz square wave output. See RTC_CLKOUT options for details. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 864
SR[TOF] or SR[TIF] are set. When the time counter is disabled, the TPR can be read or written. The TSR[TSR] increments when bit 14 of the TPR transitions from a logic one to a logic zero. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 865
Configures the number of 32.768 kHz clock cycles in each second. This register is double buffered and writes do not take affect until the end of the current compensation interval. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 866
Reset RTC_CR field descriptions Field Description 31–24 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 867
Registers can be written when locked under limited conditions. Supervisor Access Non-supervisor mode write accesses are not supported and generate a bus error. Non-supervisor mode write accesses are supported. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 868
Time alarm flag is set when the TAR[TAR] equals the TSR[TSR] and the TSR[TSR] increments. This bit is cleared by writing the TAR register. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 869
Lock Register is not locked and writes complete as normal. Status Register Lock After being cleared, this bit can be set only by VBAT POR or software reset. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 870
The wakeup pin is optional and not available on all devices. Whenever the wakeup pin is enabled and this bit is set, the wakeup pin will assert. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 871
Time invalid flag does not generate an interrupt. Time invalid flag does generate an interrupt. 40.3.9 RTC Write Access Register (RTC_WAR) Address: 4003_D000h base + 800h offset = 4003_D800h Reset IERW LRW SRW CRW Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 872
After being cleared, this bit is set only by system reset. It is not affected by VBAT POR or software reset. Writes to the Time Seconds Register are ignored. Writes to the Time Seconds Register complete as normal. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 873
Time Alarm Register Read TARR After being cleared, this bit is set only by system reset. It is not affected by VBAT POR or software reset. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 874
An attempt to access an RTC register, except the access control registers, results in a bus error when: • VBAT is powered down, • the RTC is electrically isolated, or • VBAT POR is asserted. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 876
0x3FFF and then increments. The compensation interval is used to adjust the frequency at which the time compensation value is used, that is, from once a second to once every 256 seconds. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 877
VBAT POR or software reset. Locking the Control register (CR) will disable the software reset. Locking LR will block future updates to LR. Write accesses to a locked register are ignored and do not generate a bus error. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 878
RTC clock gate control bit. The RTC seconds interrupt does not cause the RTC wakeup pin to assert. This interrupt is optional and may not be implemented on all devices. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 879
USBVDD Figure 41-1. USB FS/LS Subsystem Overview NOTE Use the following code sequence to select USB clock source, USB clock divide ratio, and enable its clock gate to avoid KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 880
LPUART0) will be connected to the FS USB physical layer. This configures the FS USB DP/DM signals to be configured as normal UART signals, which do not operate in differential mode. When UARTCHLS bit in the USBx_USBCTRL register is set to 1’b0, KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 881
The chip can be powered by two AA/AAA cells. In this case, the MCU is powered through VDD which is within the 1.8 to 3.0 V range. After USB cable insertion is detected, the off-chip regulator is enabled to power the USB transceiver. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 882
Figure 41-3. USB regulator Li-ion usecase 41.1.1.3.3 USB bus power supply The chip can also be powered by the USB bus directly. In this case, the regulator supplies VDD and USBVDD supply inputs. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 883
Related module Reference Full description USB controller USB controller System memory map System memory map Clocking Clock Distribution Transfers Crossbar switch Crossbar switch Signal Multiplexing Port control Signal Multiplexing KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 884
• Device Capacitance (USB Engineering Change Notice) • USB 2.0 Connect Timing Update (USB Engineering Change Notice as of April 4, 2013) • USB 2.0 VBUS Max Limit (USB Engineering Change Notice) KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 885
The device sends and receives data to and from the host using a standard USB data format. USB 2.0 full-speed /low-speed peripherals operate at 12Mbit/s or 1.5 Mbit/s. For additional information, see the USB 2.0 specification. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 886
OTG protocols to assume the role of host or peripheral based on the task to be accomplished. For additional information, see the On-The-Go and Embedded Host Supplement to the USB 2.0 Specification. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 887
• IRC48M with clock-recovery is supported to eliminate the 48 MHz crystal. It is used for USB device-only implementation. 41.3 Functional description USBOTG communicates with the processor core through status registers, control registers, and data structures in memory. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 888
SOC, while the USBVDD supply must be 3.3v nominal for USB compliance. For more details, see the Kinetis Peripheral Module Quick Reference(KQRUG). KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 889
External 5v to 3.3v regulator 3.3v USBVDD VBUS 33 Ω USB_DM 33 Ω USB_DP USB connector Place resistors close to the processor Figure 41-9. Typical Device-only diagram (bus-powered with external regulator) KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 890
Software should manage buffers for USBFS by updating the BDT when needed. This allows USBFS to efficiently manage data transmission and reception, while the microprocessor performs communication overhead processing and other function KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 891
For this reason, a USBFS core-centric nomenclature is used to describe the direction of the data transfer between the USBFS core and USB: KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 892
31:24 23:16 15:9 BDT_PAGE_03 BDT_PAGE_02 BDT_PAGE_01[7:1] Endpoint Table 41-4. BDT address calculation fields Field Description BDT_PAGE BDT_PAGE registers in the Control Register Block Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 893
• Where the buffer resides in system memory The format for the BD is shown in the following figure. Table 41-5. Buffer descriptor format 31:26 25:16 15:8 Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 894
FIFO. 0 USBFS writes bit 2 of the current token PID to the BD. 1 This bit is unchanged by USBFS. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 895
These bits are unchanged by USBFS. 41.4.5 USB transaction When USBFS transmits or receives data, it computes the BDT address using the address generation shown in "Addressing Buffer Descriptor Entries" table. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 896
The memory latency may be too high and cause the receive FIFO to overflow. This is predominantly a hardware performance issue, usually caused by transient memory access issues. Oversized Packets KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 897
Peripheral Revision register (USB0_REV) 41.5.3/901 4007_200C Peripheral Additional Info register (USB0_ADDINFO) 41.5.4/901 4007_2010 OTG Interrupt Status register (USB0_OTGISTAT) 41.5.5/902 4007_2014 OTG Interrupt Control register (USB0_OTGICR) 41.5.6/903 Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 898
4007_20CC Endpoint Control register (USB0_ENDPT3) 41.5.23/ 4007_20D0 Endpoint Control register (USB0_ENDPT4) 41.5.23/ 4007_20D4 Endpoint Control register (USB0_ENDPT5) 41.5.23/ 4007_20D8 Endpoint Control register (USB0_ENDPT6) Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 899
USB Clock recovery control 41.5.34/ 4007_2140 (USB0_CLK_RECOVER_CTRL) PROCESS PHIRC48M oscillator enable register 41.5.35/ 4007_2144 (USB0_CLK_RECOVER_IRC_EN) Clock recovery combined interrupt enable 41.5.36/ 4007_2154 (USB0_CLK_RECOVER_INT_EN) Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 900
Write Reset USBx_IDCOMP field descriptions Field Description 7–6 This field is reserved. Reserved This read-only field is reserved and always has the value 1. Ones' complement of PERID[ID] bits. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 901
This read-only field is reserved and always has the value 0. 2–1 This field is reserved. Reserved This read-only field is reserved and always has the value 0. This bit is set if host mode is enabled. IEHOST KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 902
This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved. Reserved Software must not change the value of this bitfield. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 903
This field is reserved. Reserved This read-only field is reserved and always has the value 0. Software must not change the value of this bitfield. Reserved This field is reserved. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 904
This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved. Reserved This read-only field is reserved and always has the value 0. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 905
If HOST_MODE is 1 the D+ and D– Data Line pull-down resistors are engaged. The pull-up and pull-down controls in this register are used. Reserved This field is reserved. This read-only field is reserved and always has the value 0. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 906
In Host mode this field is set when the SOF threshold is reached (MISCCTRL[SOFBUSSET]=0), or when the SOF counter reaches 0 (MISCCTRL[SOFBUSSET]=1), so that software can prepare for the next SOF. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 907
TOKDNE Interrupt Enable TOKDNEEN Disables the TOKDNE interrupt. Enables the TOKDNE interrupt. SOFTOK Interrupt Enable SOFTOKEN Disbles the SOFTOK interrupt. Enables the SOFTOK interrupt. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 908
OUT TOKEN or the data and handshake phases of a IN TOKEN. If more than 16 bit times are counted from the previous EOP before a transition from IDLE, a bus turnaround timeout error occurs. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 909
This field is valid when the USB module is operating in peripheral mode (CTL[HOSTMODEEN]=0). Disables the OWNERR interrupt. Enables the OWNERR interrupt. DMAERR Interrupt Enable DMAERREN Disables the DMAERR interrupt. Enables the DMAERR interrupt. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 910
STAT value. If the data in the STAT holding register is valid, the SIE immediately reasserts to TOKDNE interrupt. Address: 4007_2000h base + 90h offset = 4007_2090h Read ENDP Write Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 911
(CTL[HOSTMODEEN]=1). Software must set RESET to 1 for the required amount of time and then clear it to 0 to end reset signaling. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 912
Informs the USB module that the next token command written to the token register must be performed at low speed. This enables the USB module to perform the necessary preamble required for low-speed data transmissions. ADDR USB Address Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 913
This 8-bit field and the 3-bit field in the Frame Number Register High are used to compute the address where the current Buffer Descriptor Table (BDT) resides in system memory. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 914
The endpoint control register determines the handshake and retry policies used during the transfer. Address: 4007_2000h base + A8h offset = 4007_20A8h Read TOKENPID TOKENENDPT Write Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 915
Typical values for the SOF threshold are: • 64-byte packets=74; • 32-byte packets=42; • 16-byte packets=26; • 8-byte packets=18. Address: 4007_2000h base + ACh offset = 4007_20ACh Read Write Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 916
USBx_BDTPAGE3 field descriptions Field Description BDTBA Provides address bits 31 through 24 of the BDT base address that defines the location of Buffer Descriptor Table resides in system memory. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 917
Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 HOSTWOHUB (ENDPT0) only. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 918
Weak pulldowns are enabled on D+ and D–. UART Signal Channel Select UARTCHLS This field is valid only when USB signals are selected to be used as UART signals. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 919
Provides observability of the D- Pulldown enable at the USB transceiver. DMPD D– pulldown disabled. D– pulldown enabled. Reserved This field is reserved. This read-only field is reserved and always has the value 0. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 920
USB receptacle VBUS pin is connected to VREGIN. Address: 4007_2000h base + 10Ch offset = 4007_210Ch Read VFEDG_DET USBRESMEN Write USBRESET Reset USB_CLK_ Read VREDG_DET SYNC_DET USB_RESUME_INT RECOVERY_INT Write Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 921
SYNC_DET Synchronous interrupt has not been detected. Synchronous interrupt has been detected. USB Asynchronous Interrupt USB_RESUME_ No interrupt was generated. Interrupt was generated because of the USB asynchronous interrupt. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 922
6–5 This field is reserved. Reserved This read-only field is reserved and always has the value 0. VREGIN Falling Edge Interrupt Enable VFEDG_EN Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 923
STALL_I_ STALL_I_ Write DIS7 DIS6 DIS5 DIS4 DIS3 DIS2 DIS1 DIS0 Reset USBx_STALL_IL_DIS field descriptions Field Description Disable endpoint 7 IN direction. STALL_I_DIS7 Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 924
IN direction of the endpoints 15 to 8. Address: 4007_2000h base + 134h offset = 4007_2134h Read STALL_I_ STALL_I_ STALL_I_ STALL_I_ STALL_I_ STALL_I_ STALL_I_ STALL_I_ Write DIS15 DIS14 DIS13 DIS12 DIS11 DIS10 DIS9 DIS8 Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 925
(MISCCTRL[STL_ADJ_EN]=1). When an endpoint is stalled (ENDPTn[END_STALL]=1), the fields in this register enable or disable stalling of the OUT direction for the endpoints 7 to 0. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 926
41.5.33 Peripheral mode stall disable for endpoints 15 to 8 in OUT direction (USBx_STALL_OH_DIS) This register is valid only in Peripheral mode(CTL[HOSTMODEEN]=0) and when stall adjust enable bit is set (MISCCTRL[STL_ADJ_EN]=1). KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 927
Endpoint 9 OUT direction stall is enabled. Endpoint 9 OUT direction stall is disabled. Disable endpoint 8 OUT direction. STALL_O_DIS8 Endpoint 8 OUT direction stall is enabled. Endpoint 8 OUT direction stall is disabled. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 928
This bit is for NXP use only. Customers should not change this bit from its default state. This field is reserved. Reserved This bit is for NXP use only. Customers should not change this bit from its default state. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 929
This bit is used to enable the local analog regulator for IRC48M module. This bit must be set if user wants to use the crystal-less USB clock configuration. IRC48M local regulator is disabled IRC48M local regulator is enabled (default) KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 930
A Write operation with value high at 1'b1 on any combination of individual bits will clear those bits. Address: 4007_2000h base + 15Ch offset = 4007_215Ch OVF_ Read Reserved Reserved ERROR Write Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 931
USB-FS core. For more information about these procedures, see the Universal Serial Bus Specification, Revision 2.0, "Chapter 9 USB Device Framework." To enable host mode and discover a connected device: KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 932
5. Set the USB device address of the peripheral device in the address register (ADDR[6:0]). After the USB bus reset, the device USB address is zero. It is set to some other value usually 1 by the Set Address device framework command. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 933
BDT is written with the handshake from the device and a Token Done (ISTAT[TOKDNE]) interrupt is asserted. This completes the data phase of the setup transaction. To send a full speed bulk data transfer to a peripheral device: KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 934
Negotiation Protocol (HNP) and Session Request Protocol (SRP) and give access to the OTG protocol control signals. The following state machines show the OTG operations involved with HNP and SRP protocols from either end of the USB cable. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 935
After 200 ms without Attach or ID Interrupt. (This could wait forever Go to A_WAIT_FALL if desired.) Turn off DRV_VBUS A_VBUS_VLD Interrupt and B device attaches Go to A_HOST Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 936
A dual role B device operates as the following flow diagram and state description table illustrates. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 937
If ID\ Interrupt or B_SESS_VLD\ Interrupt Go to B_IDLE If the cable changes or if VBUS goes away, the host doesn't support If B application is done or A disconnects Go to B_PERIPHERAL KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 938
5. The USB clock source must choose the output of the divided clock. For chip-specific details, see the USB FS OTG controller clocking information in the "Clock Distribution" chapter. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 939
CAN_CTRL1[CLKSRC] register bit selects between clocking the FlexCAN from the internal bus clock or the input clock (OSCERCLK). In this case, a clock source with PLL FM jitter must not be used. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 940
The FlexCAN module can be configured to generate a wakeup interrupt in STOP and VLPS modes. When the FlexCAN is configured to generate a wakeup, a recessive to dominant transition on the CAN bus generates an interrupt. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 941
FlexCAN module, including one associated memory for storing message buffers, Receive Global Mask registers, Receive Individual Mask registers, Receive FIFO filters, and Receive FIFO ID filters. The functions of the submodules are described in subsequent sections. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 942
The message buffers are stored in an embedded RAM dedicated to the FlexCAN module. See the chip configuration details for the actual number of message buffers configured in the chip. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 943
DMA support • Transmission abort capability • Flexible message buffers (MBs), totaling 16 message buffers of 8 bytes data length each, configurable as Rx or Tx KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 944
• Powerful Rx FIFO ID filtering, capable of matching incoming IDs against either 128 extended, 256 standard, or 512 partial (8 bit) IDs, with up to 32 individual masking capability • 100% backward compatibility with previous FlexCAN version KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 945
BIT0 error (without changing the REC), as if it was trying to acknowledge the message. For low-power operation, the FlexCAN module has: • Module Disable mode: KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 946
42.3.1 CAN Rx This pin is the receive pin from the CAN bus transceiver. Dominant state is represented by logic level 0. Recessive state is represented by logic level 1. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 947
Interrupt Masks 1 register (CAN_IMASK1) Interrupt Flags 1 register (CAN_IFLAG1) Control 2 Register (CAN_CTRL2) Error and Status 2 Register (CAN_ESR2) CRC Register (CAN_CRCR) Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 948
4002_4038 Error and Status 2 register (CAN0_ESR2) 0000_0000h 42.4.14/ 4002_4044 CRC Register (CAN0_CRCR) 0000_0000h 42.4.15/ 4002_4048 Rx FIFO Global Mask register (CAN0_RXFGMASK) Undefined Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 952
This register defines global system configurations, such as the module operation modes and the maximum message buffer configuration. Address: Base address + 0h offset MDIS FRZ RFEN IRMQ Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 953
This bit can be written in Freeze mode only because it is blocked by hardware in other modes. Rx FIFO not enabled. Rx FIFO enabled. Halt FlexCAN HALT Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 954
This bit configures the FlexCAN to be either in Supervisor or User mode. The registers affected by this bit are marked as S/U in the Access Type column of the module memory map. Reset value of this bit is 1, so Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 955
FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus. FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus. Doze Mode Enable DOZE Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 956
CAN bus without notification. This bit can be written only in Freeze mode because it is blocked by hardware in other modes. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 957
Rx bit, Loop Back mode, Listen-Only mode, Bus Off recovery behavior and interrupt enabling (Bus-Off, Error, Warning). It also determines the Division Factor for the clock prescaler. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 958
One time quantum is equal to the Sclock period. The valid programmable values are 0–3. This field can be written only in Freeze mode because it is blocked by hardware in other modes. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 959
NOTE: In this mode, the CAN_MCR[SRXDIS] cannot be asserted because this will impede the self reception of a transmitted message. Loop Back disabled. Loop Back enabled. Tx Warning Interrupt Mask TWRNMSK Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 960
Mailbox, according to CAN_CTRL2[RFFN] setting, is used for timer synchronization instead of MB0. This bit can be written in Freeze mode only because it is blocked by hardware in other modes. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 961
The timer value is captured when the second bit of the identifier field of any frame is on the CAN bus. This captured value is written into the Time Stamp entry in a message buffer after a successful reception or transmission of a message. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 963
Reset * Notes: • x = Undefined at reset. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 964
The corresponding bit in the filter is "don’t care." The corresponding bit in the filter is checked. 42.4.8 Error Counter (CANx_ECR) This register has two 8-bit fields reflecting the value of the FlexCAN error counters: KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 965
At the next successful message reception, the counter is set to a value between 119 and 127 to resume to "Error Active" state. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 966
• Write 1 to clear the interrupt bit that has triggered the interrupt request. • Write 1 to clear the ERR_OVR bit if it is set. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 967
CPU to serve the interrupt request, the ERR_OVR bit is set to indicate that errors from different frames had accumulated. SYNCH IDLE FlexCAN State Not synchronized to CAN bus Idle Transmitting Receiving Address: Base address + 20h offset Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 968
This bit indicates that an error condition occurred when any error flag is already set. This bit is cleared by writing it to 1. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 969
No such occurrence. At least one bit sent as recessive is received as dominant. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 970
This bit indicates when CAN bus is in IDLE state. See the table in the overall CAN_ESR1 register IDLE description. No such occurrence. CAN bus is now IDLE. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 971
When CAN_MCR[SLFWAK] is negated, this flag is masked. The CPU must clear this flag before disabling the bit. Otherwise it will be set when the SLFWAK is set again. Writing 0 has no effect. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 972
The interrupt flag must be cleared by writing 1 to it. Writing 0 has no effect. There is an exception when DMA for Rx FIFO is enabled, as described below. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 973
MB value is greater than the CAN_MCR[MAXMB] to be updated; otherwise, they will remain set and be inconsistent with the number of MBs available. Address: Base address + 30h offset BUF31TO8I Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 974
Buffer MB5 Interrupt Or "Frames available in Rx FIFO" BUF5I When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags the interrupt for MB5. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 975
Freeze Mode, for extending FIFO filter quantity, and for adjust the operation of internal FlexCAN processes like matching and arbitration. The contents of this register are not affected by soft reset. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 976
SETUP_MB is the least between the parameter NUMBER_OF_MB and CAN_MCR[MAXMB]. The number of remaining Mailboxes available will be: (SETUP_MB - 8) - (RFFN × 2) Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 977
Matching starts from Rx FIFO and continues on Mailboxes. Matching starts from Mailboxes and continues on Rx FIFO. Remote Request Storing Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 978
This read-only field is reserved and always has the value 0. 42.4.13 Error and Status 2 register (CANx_ESR2) This register reports some general status information. Address: Base address + 38h offset LPTM Reset Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 979
If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one. Reserved This field is reserved. This read-only field is reserved and always has the value 0. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 980
RXIMR according to CAN_CTRL2[RFFN] field setting. This register can only be written in Freeze mode as it is blocked by hardware in other modes. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 981
Rx FIFO as well as its output is updated whenever the output of the Rx FIFO is updated with the next message. See Section "Rx FIFO" for instructions on reading this register. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 982
The contents of this register are not affected by soft reset. NOTE The CAN bit variables in CAN_CTRL1 and in CAN_CBT are stored in the same register. Address: Base address + 50h offset EPRESDIV ERJW Reset KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 983
Freeze mode because it is blocked by hardware in other modes. Propagation Segment Time = (EPROPSEG + 1) × Time-Quanta. Time-Quantum = one Sclock period. 9–5 Extended Phase Segment 1 EPSEG1 Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 984
Reset * Notes: • x = Undefined at reset. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 985
This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. The encoding is shown in Table 42-4 Table 42-5. See Functional description for additional information. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 986
CPU has serviced the MB, when a new frame is moved to the MB then the code returns to FULL. Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 987
2. A frame is considered a successful reception after the frame to be moved to MB (move-in process). See Move-in details. 3. Remote Request Stored bit, see "Control 2 Register (CAN_CTRL2)" for details. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 988
RTR bit value. See Matching process Arbitration process details. SRR - Substitute Remote Request KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 989
This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. PRIO - Local priority KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 990
This output contains the oldest message that has been received but not yet read. The region 0x90-0xDC is reserved for internal use of the FIFO engine. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 991
See Rx FIFO for more information. Table 42-8. ID table structure Format RXIDA (standard = 29–19, extended = 29–1) RXIDB_0 RXIDB_1 Table continues on the next page... KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 992
This 9-bit field indicates which Identifier Acceptance Filter was hit by the received message that is in the output of the Rx FIFO. See Rx FIFO for more information. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 993
CAN_IFLAG register or by the interrupt request if enabled by the respective IMASK bit. Then read back the CODE field to check if the transmission was aborted or transmitted (see Transmission abort mechanism). If backwards compatibility is KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 994
• During the Overload Delimiter field of a CAN frame. • When the winner is inactivated and the CAN bus has still not reached the first bit of the Intermission field. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 995
If two or more Mailboxes have equivalent arbitration values, the Mailbox with the lowest number is the arbitration winner. The composition of the arbitration value depends on CAN_MCR[LPRIOEN] bit setting. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 996
This operation is called move-out and after it is done, write access to the C/S word of the corresponding MB is blocked (if the AEN bit in CAN_MCR register is asserted). Write access is restored in the following events: KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 997
• It was not possible to finish arbitration process in time • C/S write during arbitration if write is performed in a MB whose number is lower than the Tx arbitration pointer KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 998
Section Message buffer structure). 6. A status flag is set in the Interrupt Flag Register and an interrupt is generated if allowed by the corresponding Interrupt Mask Register bit. KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 999
Available in Rx FIFO interrupt (see the description of the BUF5I bit "Frames available in Rx FIFO" bit in the CAN_IFLAG1 register), the CPU should service the received frame using the following procedure: KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 NXP Semiconductors...
Page 1000
The matching process start point depends on the following conditions: • If the received frame is a remote frame, the start point is the CRC field of the frame KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016 1000 NXP Semiconductors...
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