NXP Semiconductors MCF5272 ColdFire User Manual

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MCF5272 ColdFire

Microprocessor

User's Manual

ColdFire

Microcontrollers

MCF5272UM

Rev. 3

03/2007

freescale.com

Integrated

Table of Contents

Summary of Contents for NXP Semiconductors MCF5272 ColdFire

Page 1 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual ® ColdFire Microcontrollers MCF5272UM Rev. 3 03/2007 freescale.com...
Page 3 Overview ColdFire Core Hardware Multiply/Accumulate (MAC) Unit Local Memory Debug Support System Integration Module (SIM) Interrupt Controller Chip-Select Module SDRAM Controller DMA Controller Module Ethernet Module Universal Serial Bus (USB) Physical Layer Interface Controller (PLIC) Queued Serial Peripheral Interface (QSPI) Module Timer Module UART Modules General-Purpose I/O Module...
Page 4 Overview ColdFire Core Hardware Multiply/Accumulate (MAC) Unit Local Memory Debug Support System Integration Module (SIM) Interrupt Controller Chip-Select Module SDRAM Controller DMA Controller Module Ethernet Module Universal Serial Bus (USB) Physical Layer Interface Controller (PLIC) Queued Serial Peripheral Interface (QSPI) Module Timer Module UART Modules General-Purpose I/O Module...
Page 5: Table Of Contents
Command Sequence..................5-22 RAREG RDREG 5-19 Command Format ..................5-23 WAREG WDREG 5-20 Command Sequence ..................5-23 WAREG WDREG 5-21 Command/Result Formats ................... 5-24 READ 5-22 Command Sequence ....................5-24 READ ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 6 Chip Select Base Registers (CSBRn) ..................8-3 Chip Select Option Registers (CSORn) ................. 8-5 SDRAM Controller Signals...................... 9-2 54-Pin TSOP SDRAM Pin Definition..................9-3 SDRAM Configuration Register (SDCR)................. 9-6 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 7 Hash Table Low (HTLR) ....................11-29 11-24 Pointer-to-Receive Descriptor Ring (ERDSR)..............11-30 11-25 Pointer-to-Transmit Descriptor Ring (ETDSR) ..............11-31 11-26 Receive Buffer Size (EMRBR) .................... 11-32 11-27 Receive Buffer Descriptor (RxBD) ..................11-35 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 8 B2 Receive Data Registers P0B2RR – P3B2RR ..............13-16 13-15 D Receive Data Registers P0DRR–P3DRR ............... 13-16 13-16 B1 Transmit Data Registers P0B1TR–P3B1TR..............13-17 13-17 B2 Transmit Data Registers P0B2TR–P3B2TR..............13-17 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 viii Freescale Semiconductor...
Page 9 Timer Capture Registers (TCAP0–TCAP3) ................15-4 15-5 Timer Counter (TCN0–TCN3) ....................15-4 15-6 Timer Event Registers (TER0–TER3)................... 15-5 16-1 Simplified Block Diagram ...................... 16-1 16-2 UART Mode Registers 1 (UMR1n)..................16-4 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 10 MCF5272 Block Diagram with Signal Interfaces..............19-2 20-1 Internal Operand Representation..................20-5 20-2 MCF5272 Interface to Various Port Sizes................20-5 20-3 Longword Read; EBI = 00; 32-Bit Port; Internal Termination..........20-8 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 11 Real-Time Trace AC Timing....................23-13 23-8 BDM Serial Port AC Timing....................23-13 23-9 SDRAM Signal Timing ......................23-15 23-10 SDRAM Self-Refresh Cycle Timing ..................23-16 23-11 MII Receive Signal Timing Diagram..................23-17 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 12 23-21 General-Purpose I/O Port Timing..................23-28 23-22 USB Interface Timing ......................23-29 23-23 IEEE 1149.1 (JTAG) Timing....................23-30 23-24 QSPI Timing........................23-31 23-25 PWM Timing........................23-32 Buffering and Termination.......................B-2 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 13 2.1.1.2.3 Hardware Divide Unit.................. 2-4 2.1.2 Debug Module Enhancements .................... 2-4 2.2 Programming Model ........................2-4 2.2.1 User Programming Model ....................2-4 2.2.1.1 Data Registers (D0–D7) ..................2-5 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor xiii...
Page 14: Paragraph Page
3.1.1 MAC Programming Model ....................3-2 3.1.2 General Operation ......................3-3 3.1.3 MAC Instruction Set Summary ..................3-4 3.1.4 Data Representation ......................3-4 3.2 MAC Instruction Execution Timings ..................... 3-4 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 15 5.4.1 Revision A Shared Debug Resources ................. 5-7 5.4.2 Address Attribute Trigger Register (AATR) ..............5-7 5.4.3 Address Breakpoint Registers (ABLR, ABHR) ..............5-9 5.4.4 Configuration/Status Register (CSR) ................5-10 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 16 Chapter 6 System Integration Module (SIM) 6.1 Features ............................6-1 6.2 Programming Model ........................6-2 6.2.1 SIM Register Memory Map ....................6-2 6.2.2 Module Base Address Register (MBAR) ................6-3 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 17 8.1.3 Boot CS0 Operation ......................8-2 8.2 Chip Select Registers ........................8-2 8.2.1 Chip Select Base Registers (CSBR0–CSBR7) ..............8-3 8.2.2 Chip Select Option Registers (CSOR0–CSOR7) ............... 8-5 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor xvii...
Page 18 11.4 FEC Frame Transmission ......................11-4 11.4.1 FEC Frame Reception ....................11-5 11.4.2 CAM Interface ........................ 11-6 11.4.3 Ethernet Address Recognition ..................11-6 11.4.4 Hash Table Algorithm ..................... 11-8 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 xviii Freescale Semiconductor...
Page 19 11.6.1 FEC Buffer Descriptor Tables ..................11-35 11.6.1.1 Ethernet Receive Buffer Descriptor (RxBD) ..........11-35 11.6.1.2 Ethernet Transmit Buffer Descriptor .............. 11-37 11.7 Differences between MCF5272 FEC and MPC860T FEC ............11-39 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 20 12.3.3.1 Configuration RAM Content ................12-28 12.3.3.2 USB Device Configuration Example .............. 12-29 12.3.4 USB Module Access Times ..................12-30 12.3.4.1 Registers ......................12-30 12.3.4.2 Endpoint FIFOs ....................12-30 12.3.4.3 Configuration RAM ..................12-30 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 21 13.2.5 GCI/IDL Interrupts ......................13-9 13.2.5.1 GCI/IDL Periodic Frame Interrupt ..............13-9 13.2.5.2 GCI Aperiodic Status Interrupt ..............13-10 13.2.5.3 Interrupt Control ..................... 13-11 13.3 PLIC Timing Generator ......................13-11 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 22 13.6.3 Example 1: ISDN SOHO PBX with Ports 0, 1, 2, and 3 ..........13-38 13.6.4 Example 2: ISDN SOHO PBX with Ports 1, 2, and 3 ..........13-40 13.6.5 Example 3: Two-Line Remote Access with Ports 0 and 1 ........... 13-41 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 xxii Freescale Semiconductor...
Page 23 15.3.1 Timer Mode Registers (TMR0–TMR3) ................15-3 15.3.2 Timer Reference Registers (TRR0–TRR3) ..............15-4 15.3.3 Timer Capture Registers (TCAP0–TCAP3) ..............15-4 15.3.4 Timer Counters (TCN0–TCN3) ..................15-4 15.3.5 Timer Event Registers (TER0–TER3) ................15-5 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor xxiii...
Page 24 16.5.3 Looping Modes ......................16-26 16.5.3.1 Automatic Echo Mode ..................16-27 16.5.3.2 Local Loop-Back Mode .................. 16-27 16.5.3.3 Remote Loop-Back Mode ................16-27 16.5.4 Multidrop Mode ......................16-28 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 xxiv Freescale Semiconductor...
Page 25 19.4 Data Bus (D[31:0]) ........................19-19 19.4.1 Dynamic Data Bus Sizing .................... 19-19 19.5 Chip Selects (CS7/SDCS, CS[6:0]) ..................19-19 19.6 Bus Control Signals ......................... 19-20 19.6.1 Output Enable/Read (OE/RD) ..................19-20 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 26 19.12.2 Timer Output (TOUT0)/PB7 ..................19-27 19.12.3 Timer Input 1 (TIN1)/PWM Mode Output 2 (PWM_OUT2) ........19-27 19.12.4 Timer Output 1 (TOUT1)/PWM Mode Output 1 (PWM_OUT1) ......19-27 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 xxvi Freescale Semiconductor...
Page 27 19.16.2.1 GCI/IDL Data Clock (DCL1/GDCL1_OUT) ..........19-32 19.16.2.2 GCI/IDL Data Out (DOUT1) ............... 19-33 19.16.2.3 GCI/IDL Data In (DIN1) ................19-33 19.16.2.4 GCI/IDL Frame Sync (FSC1/FSR1/DFSC1) ..........19-33 19.16.2.5 D-Channel Request (DREQ1/PA14) ............19-33 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor xxvii...
Page 28 20.6.2 Interface for FLASH/SRAM Devices without Byte Strobes ........20-12 20.7 Burst Data Transfers ........................ 20-17 20.8 Misaligned Operands ....................... 20-18 20.9 Interrupt Cycles ........................20-19 20.10 Bus Errors ..........................20-19 20.11 Bus Arbitration ........................20-21 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 xxviii Freescale Semiconductor...
Page 29 23.6.2 MII Transmit Signal Timing (E_TxD[3:0], E_TxEN, E_TxER, E_TxCLK) ....23-18 23.6.3 MII Async Inputs Signal Timing (CRS and COL) ............23-19 23.6.4 MII Serial Management Channel Timing (MDIO and MDC) ........23-20 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor xxix...
Page 30 23.13 QSPI Electrical Specifications ....................23-31 23.14 PWM Electrical Specifications ....................23-32 Appendix A List of Memory Maps A.1 List of Memory Map Tables......................A-1 Appendix B Buffering and Impedance Matching Index 1 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 31 Rev. A Shared BDM/Breakpoint Hardware ................5-7 AATR Field Descriptions ......................5-7 ABLR Field Description ......................5-9 ABHR Field Description ......................5-9 CSR Field Descriptions ......................5-10 DBR Field Descriptions ......................5-12 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor xxxi...
Page 32 Configurations for 16-Bit Data Bus..................9-4 Configurations for 32-Bit Data Bus..................9-4 Internal Address Multiplexing (16-Bit Data Bus) ..............9-5 Internal Address Multiplexing (32-Bit Data Bus) ..............9-5 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 xxxii Freescale Semiconductor...
Page 33 EMRBR Field Descriptions....................11-32 11-30 Hardware Initialization......................11-33 11-31 ETHER_EN = 0........................11-33 11-32 User Initialization Process (before ETHER_EN) ..............11-33 11-33 User Initialization (after ETHER_EN) .................. 11-34 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor xxxiii...
Page 34 QSPI_CLK Frequency as Function of CPU Clock and Baud Rate ........14-7 14-3 QMR Field Descriptions ......................14-9 14-4 QDLYR Field Descriptions ....................14-11 14-5 QWR Field Descriptions...................... 14-12 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 xxxiv Freescale Semiconductor...
Page 35 16-Bit Data Bus—SRAM Cycles19-21 19-5 Byte Strobe Operation for 16-Bit Data Bus—SDRAM Cycles19-21 19-6 Connecting BS[3:0] to DQMx ....................19-21 19-7 Processor Status Encoding....................19-37 19-8 MCF5272 Bus Width Selection19-38 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor xxxv...
Page 36 23-25 PWM Modules AC Timing Specifications................23-32 On-Chip Module Base Address Offsets from MBAR...............A-1 CPU Space Registers Memory Map ..................A-2 On-Chip Peripherals and Configuration Registers Memory Map ..........A-2 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 xxxvi Freescale Semiconductor...
Page 37 A-12 SDRAM Controller Memory Map.....................A-7 A-13 Timer Module Memory Map ....................A-7 A-14 PLIC Module Memory Map .....................A-8 A-15 Ethernet Module Memory Map....................A-9 A-16 USB Module Memory Map ....................A-10 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor xxxvii...
Page 38: Mcf5272 Coldfire ® Integrated Microprocessor User's Manual,
® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 xxxviii Freescale Semiconductor...
Page 39 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.freescale.com/...
Page 40: Overview
— Section 4.5, “Instruction Cache Overview,” describes the MCF5272 cache implementation, including organization, configuration, and coherency. It describes cache operations and how the cache interacts with other memory structures. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 41 0, 1, 2 and 3. • Chapter 16, “UART Modules,” describes the use of the universal asynchronous/synchronous receiver/transmitters (UARTs) implemented on the MCF5272, including example register values for typical configurations. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 42 Maps,” provides the entire address-map for MCF5272 memory-mapped registers. • Appendix B, “Buffering and Impedance Matching,” provides some suggestions regarding interface circuitry between the MCF5272 and SDRAMs. This manual also includes an index. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 xlii Freescale Semiconductor...
Page 43: General Information
Additional literature on ColdFire implementations is being released as new processors become available. For a current list of ColdFire documentation, refer to the World Wide Web at http://www.freescale.com. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor xliii...
Page 44 1. The only exceptions to this appear in the discussion of serial communication modules that support variable-length data transmission units. To simplify the discussion these units are referred to as words regardless of length. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 xliv...
Page 45: Acronyms And Abbreviations
LIFO Last-in, first-out Least recently used Least-significant byte Least-significant bit Multiply accumulate unit, also Media access controller MBAR Memory base address register Most-significant byte Most-significant bit Multiplex No operation ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 46 Queued serial peripheral interface RISC Reduced instruction set computing Receive System integration module Start of frame Test access port Transistor transistor logic Transmit UART Universal asynchronous/synchronous receiver transmitter Universal serial bus ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 xlvi Freescale Semiconductor...
Page 47 Program counter Status register Port Name DDATA Debug data port Processor status port Miscellaneous Operands #<data> Immediate data following the 16-bit operation word of the instruction <ea> Effective address ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor xlvii...
Page 48 ‘else’ clause is present, the operations after ‘else’ are performed. If the condition is false and else is else <operations> omitted, the instruction performs no operation. Refer to the Bcc instruction description as an example. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 xlviii Freescale Semiconductor...
Page 49 Least significant bit (example: lsb of D0) Least significant byte Least significant word Most significant bit Most significant byte Most significant word Condition Code Register Bit Names Carry Negative Overflow Extend Zero ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor xlix...
Page 50 CS Base Register 0 CSBR0 No change 0x0044 CS Option Register 0 CSOR0 No change 0x0048 CS Base Register 1 CSBR1 No change 0x004C CS Option Register 1 CSOR1 No change ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 51 Table vii. QSPI Module Memory Map MBAR Register Name Old Mnemonic New Mnemonic Offset 0x00A0 QSPI Mode Register SPMODE 0x00A4 QSPI Delay Register SPDELAY QDLYR 0x00A8 QSPI Wrap Register SPWRAP ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 52 UART0 Status U1SR U0SR 0x0104 UART0 Clock Select Register U1CSR U0CSR 0x0108 UART0 Command Register U1CR U0CR 0x010C UART0 Receive Buffer U1RxB U0RxB 0x010C UART0 Transmit Buffer U1TxB U0TxB ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 53 0x015C UART1 Baud Prescaler LSB U2BG2 U1BG2 0x0160 UART1 AutoBaud MSB Register U2ABR1 U1ABR1 0x0164 UART1 AutoBaud LSB Register U2ABR2 U1ABR2 0x0168 UART1 TxFIFO Control/Status Register U2TxFCSR U1TxFCSR ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor liii...
Page 54 TCN2 0x0250 Timer 2 Event Register TER3 TER2 0x0260 Timer 3 Mode Register TMR4 TMR3 0x0264 Timer 3 Reference Register TRR4 TRR3 0x0268 Timer 3 Capture Register TCR4 TCAP3 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 55 PLTB21 P1B2TR 0x0340 Port2 B2 Data Transmit PLTB22 P2B2TR 0x0344 Port3 B2 Data Transmit PLTB23 P3B2TR 0x0348 Port0-3 D Data Transmit PLTD0 P0DTR PLTD1 P1DTR PLTD2 P2DTR PLTD3 P3DTR ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 56 PLLCR PLCR 0x0392 D Channel Request PLDRQ PDRQR 0x0394 Port0-1 Sync Delay PLSD0 P0SDR PLSD1 P1SDR 0x0398 Port2-3 Sync Delay PLSD2 P2SDR PLSD3 P3SDR 0x039C Clock Select PLCKSEL PCSR ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 57 USB Frame Number Register USBFNR 0x1006 USB Frame Number Match Register USBFNMR FNMR 0x100A USB Real-time Frame Monitor Register USBRTFMR RFMR 0x100E USB Real-time Frame Monitor Match Register USBRTFMMR RFMMR ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor lvii...
Page 58 EP5ISR 0x1086 USB Endpoint 6 Interrupt Status Register USBEPISR6 EP6ISR 0x108A USB Endpoint 7 Interrupt Status Register USBEPISR7 EP7ISR 0x108C USB Endpoint 0 Interrupt Mask Register USBEPIMR0 EP0IMR ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 lviii Freescale Semiconductor...
Page 59 1, 2, or 3 bytes from the offset address shown above. Refer to the appropriate discussions in this document for actual positioning of 16- or 8-bit registers in a 32-bit long word. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 60 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 61: Mcf5272 Key Features
— Based on MC68681 dual-UART (DUART) programming model — Flexible baud rate generator — Modem control signals available (CTS and RTS) — Processor interrupt and wakeup capability — Enhanced Tx, Rx FIFOs, 24 bytes each ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 62: Mcf5272 Block Diagram
PIWR SDRAM Timer PIVR Two UARTs SDTR Four General- 32-Bit Data Bus Purpose DRAM Controller Outputs CS[7:0] 32-Bit Address Bus INT[6:1] Timers Control Signals Figure 1-1. MCF5272 Block Diagram ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 63 — Software watchdog can generate interrupt before reset — Processor interrupt for each timer • Pulse-width modulation (PWM) unit — Three identical channels — Independent prescaler TAP point — Period/duty range variable ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 64: Mcf5272 Architecture
MAC unit for DSP applications • Supervisor/user modes for system protection • Vector base register to relocate exception-vector table • Special core interfacing signals for integrated memories • Full debug support ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 65: System Integration Module (Sim)
A software watchdog timer is also provided for system protection. If programmed, the timer causes a reset to the MCF5272 if it is not refreshed periodically by software. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 66: Power Management
Using a programmable prescaler or an external source, the MCF5272 system clock supports various baud rates. Modem support is provided with request-to-send (RTS) and clear-to-send (CTS) lines available externally. Full-duplex autoecho loopback, local loopback, and remote loopback modes can be selected. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 67: Timer Module
The physical layer interface controller (PLIC) allows the MCF5272 to connect at a physical level with external CODECs and other peripheral devices that use either the general circuit interface (GCI), or ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 68: Pulse-Width Modulation (Pwm) Unit
The USB uses a tiered star topology with a hub at the center of each star. Each wire segment is a point-to-point connection between the host connector and a peripheral connector. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 69: Coldfire Core
— Decode, select/operand fetch (DSOC) decodes the instruction and selects the required components for the effective address calculation, or the operand fetch cycle. — Address generation/execute (AGEX) calculates the operand address, or performs the execution of the instruction. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 70: Instruction Fetch Pipeline (Ifp)
The operand address is generated using the execute engine (AG). • The memory operand is fetched while any register operand is simultaneously fetched (OC). • The instruction is executed (EX). ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 71: Illegal Opcode Handling
The MAC provides functionality in the following three related areas, which are described in detail in Chapter 3, “Hardware Multiply/Accumulate (MAC) Unit.” • Signed and unsigned integer multiplies • Multiply-accumulate operations with signed and unsigned fractional operands • Miscellaneous register operations ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 72: Hardware Divide Unit
Figure 2-3 shows, the user programming model consists of the following registers: • 16 general-purpose 32-bit registers, D0–D7 and A0–A7 • 32-bit program counter • 8-bit condition code register ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 73: Data Registers (D0-D7)
The stack pointer is implicitly referenced by certain operations and can be explicitly referenced by any instruction specifying an address register. The initial value of A7 is loaded ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 74: Program Counter (Pc)
Carry condition code bit. Set if a carry-out of the data operand msb occurs for an addition or if a borrow occurs in a subtraction; otherwise cleared. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 75: Mac Programming Model
Access control register 0 (ACR0) 0x005 Access control register 1 (ACR1) 0x801 Vector base register (VBR) 0xC00 ROM base address register 0xC04 RAM base address register (RAMBAR) 0xC0F Module base address register (MBAR) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 76: Status Register (Sr)
R/W Written from a BDM serial command or from the CPU using the MOVEC instruction. VBR can be read from the debug module only. The upper 12 bits are returned, the low-order 20 bits are undefined. Rc[11–0] 0x801 Figure 2-6. Vector Base Register (VBR) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 77: Cache Control Register (Cacr)
Table 2-4. Integer Data Formats Operand Data Format Size 1 bit Byte integer 8 bits Word integer 16 bits Longword integer 32 bits ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 78: Organization Of Data In Registers
All operations to the SR and CCR are word-size operations. For all CCR operations, the upper byte is read as all zeros and is ignored when written, regardless of privilege mode. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 2-10...
Page 79: Organization Of Integer Data Formats In Memory
Word 0x0000_0006 Byte 0x0000_0004 Byte 0x0000_0005 Byte 0x0000_0006 Byte 0x0000_0007 Longword 0xFFFF_FFFC Word 0xFFFF_FFFC Word 0xFFFF_FFFE Byte 0xFFFF_FFFC Byte 0xFFFF_FFFD Byte 0xFFFF_FFFE Byte 0xFFFF_FFFF Figure 2-9. Memory Operand Addressing ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 2-11...
Page 80: Addressing Mode Summary
, PC) — Program counter indirect with scaled index , PC, — 8-bit displacement Xi*SF) Absolute data addressing Short (xxx).W — Long (xxx).L — Immediate #<xxx> — — ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 2-12 Freescale Semiconductor...
Page 81: Instruction Set Summary
Program counter Status register Port Names DDATA Debug data port Processor status port Miscellaneous Operands #<data> Immediate data following the 16-bit operation word of the instruction <ea> Effective address ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 2-13...
Page 82 If the else <operations> condition is false and the else clause is omitted, the instruction performs no operation. Refer to the Bcc instruction description as an example. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 2-14 Freescale Semiconductor...
Page 83 MSB → (Dx >> Dy) → X/C Dy,Dx MSB → (Dx >> #<data>) → X/C #<data>,Dx → PC <label> .B,.W If condition true, then PC + 2 + d ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 2-15...
Page 84 Ry,RxSF,<ea-1>y,Rw .L + (.L × .L) → .L, .L ACC + (Ry × Rx){<< 1 | >> 1} → ACC; (<ea-1>y{&MASK}) → <ea>y → <ea>x MOVE <ea>y,<ea>x .B,.W,.L ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 2-16 Freescale Semiconductor...
Page 85 Dx/<ea>y → Dw {32-bit remainder} REMU <ea-1>,Dx Unsigned operation (SP) → PC; SP + 4 → SP none Unsized If condition true, then 1s ⎯ destination; Else 0s → destination ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 2-17...
Page 86: Supervisor-Mode Instruction Set Summary
Immediate data → SR; enter stopped state STOP #<data> <ea-2>y → debug module WDEBUG <ea-2>y The HALT instruction can be configured to allow user-mode execution by setting CSR[UHE]. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 2-18 Freescale Semiconductor...
Page 87: Instruction Timing
(r) and writes (w) required by the instruction. An operation performing a read-modify write function is denoted as (1/1). ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 2-19...
Page 88: Move Instruction Execution Times
3(1/1) — — — (d16,PC) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) — — (d8,PC,Xi*SF) 4(1/0) 4(1/1) 4(1/1) 4(1/1) — — — #<xxx> 1(0/0) 3(0/1) 3(0/1) 3(0/1) — — — ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 2-20 Freescale Semiconductor...
Page 89: Move Long Execution Times
1(0/0) — — — — — — — move.l MACSR,Rx 1(0/0) — — — — — — — move.l MASK,Rx 1(0/0) — — — — — — — ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 2-21...
Page 90: Execution Timings-One-Operand Instructions
1(0/0) — — — — — — 1(0/0) bchg Dy,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) — bchg #imm,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) — — — ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 2-22 Freescale Semiconductor...
Page 91 35(0/0) 38(1/0) 38(1/0) 38(1/0) 38(1/0) — — — remu.l <ea>,Dx 35(0/0) 38(1/0) 38(1/0) 38(1/0) 38(1/0) — — — sub.l <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 2-23...
Page 92: Miscellaneous Instruction Execution Times
PEA execution times are the same for (d16,PC). PEA execution times are the same for (d8,PC,Xi*SF). The execution time for STOP is the time required until the processor begins sampling continuously for interrupts. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 2-24 Freescale Semiconductor...
Page 93: Branch Instruction Execution Times
(IACK) bus cycle to obtain the vector number from a peripheral device. The IACK cycle is mapped to a special acknowledge address space with the interrupt level encoded in the address. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 2-25...
Page 94: Exception Vector Assignments
Format error Next Uninitialized interrupt 16–23 040–05C — Reserved Next Spurious interrupt 25–31 064–07C Next Level 1–7 autovectored interrupts 32–47 080–0BC Next Trap #0–15 instructions 48–60 0C0–0F0 — Reserved ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 2-26 Freescale Semiconductor...
Page 95: Exception Stack Frame Definition
Fault status field—The 4-bit field, FS[3–0], at the top of the system stack is defined for access and address errors along with interrupted debug service routines. See Table 2-20. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 2-27...
Page 96: Processor Exceptions
(Xi.w) or a scale factor of 8 on an indexed effective addressing mode, or attempted execution of an instruction with a full-format indexed addressing mode. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 2-28 Freescale Semiconductor...
Page 97 4 Transfers control to the instruction address defined by the second longword operand in the stack frame. TRAP Executing TRAP always forces an exception and is useful for implementing system calls. The trap instruction may be used to change from user to supervisor mode. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 2-29...
Page 98 If a ColdFire processor encounters any type of fault during the exception processing of another fault, the processor immediately halts execution with the catastrophic fault-on-fault condition. A reset is required to force the processor to exit this halted state. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 2-30 Freescale Semiconductor...
Page 99: Hardware Multiply/Accumulate (Mac) Unit
Each of the three areas of support is addressed in detail in the succeeding sections. Logic that supports this functionality is contained in a MAC module, as shown in Figure 3-1. Operand Y Operand X Shift 0,1,-1 Accumulator Figure 3-1. ColdFire MAC Multiplication and Accumulation ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 100: Mac Programming Model
MAC instructions. Unless noted otherwise, the setting of MACSR indicator flags is based on the final result, that is, the result of the final operation involving the product and accumulator. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 101: General Operation
Negative, zero, and overflow flags are also provided. The three program-visible MAC registers, a 32-bit accumulator (ACC), the MAC mask register (MASK), and MACSR, are described in Section 3.1.1, “MAC Programming Model.” ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 102: Mac Instruction Set Summary
0x7FFF or (1 - 2 ); the most positive longword is 0x7FFF_FFFF or (1 - 2 Execution Timings MAC Instruction For information on MAC instruction execution timings, refer to Section 2.7, “Instruction Timing.” ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 103: Local Memory
SRAM supplies data to the processor if (ROM “hits”) ROM supplies data to the processor else if (cache “hits”) cache supplies data to the processor else system memory reference to access data ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 104: Local Memory Registers
Modules,” describes priorities when an access address hits multiple local memory resources. 4.3.2 SRAM Programming Model The MCF5272 implements the SRAM base address register (RAMBAR), shown in Figure 4-1 described in the following section. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 105: Sram Base Address Register (Rambar)
SRAM module and are processed like other non-SRAM references. Valid. Enables/disables the SRAM module. V is cleared at reset. 0 RAMBAR contents are not valid. 1 RAMBAR contents are valid. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 106: Sram Initialization
Table 4-3 of typical RAMBAR settings: Table 4-3. Examples of Typical RAMBAR Settings Data Contained in SRAM RAMBAR[7–0] Instructions only 0x2B Data only 0x35 Both instructions and data 0x21 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 107: Rom Overview
— — — — W for CPU; R/W for debug Address CPU space + 0xC00 Figure 4-2. ROM Base Address Register (ROMBAR) ROMBAR fields are described in Table 4-4. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 108: Programming Rombar For Power Management
Data Contained In ROM ROMBAR[7–0] Instructions only 0x2B Data only 0x35 Both instructions and data 0x21 RAMBAR can be configured similarly, as described in Section 4.3.2.3, “Programming RAMBAR for Power Management.” ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 109: Instruction Cache Overview
Generally, longword references are used for sequential fetches. If the processor branches to an odd word address, a word-sized fetch is generated. The memory array of the instruction cache is enabled only if CACR[CENB] is asserted. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 110: Instruction Cache Operation
The instruction cache does not monitor ColdFire core data references for accesses to cached instructions. Therefore, software must maintain cache coherency by invalidating the appropriate cache entries after modifying code segments. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 111: Caching Modes
(for example, registers shown with an MBAR offset). If the corresponding ACRn[CM] or CACR[DCM] indicates cache-inhibited the access is cache-inhibited. The caching operation is identical for both cache-inhibited modes, which differ only regarding recovery from an external bus error. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 112: Reset
CLNF bits, the miss address, and the size of the external fetch. Depending on the run-time characteristics of the application and the memory response speed, overall performance may be increased by programming CLNF to values {00, 01}. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 4-10 Freescale Semiconductor...
Page 113: Instruction Cache Operation As Defined By Cacr[Cenb,Ceib]
Noncacheable Cache and line buffer are enabled; CACR[CLNF] defines fetch size; fetches are loaded into the line-fill buffer but never into the cache memory array. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 4-11...
Page 114: Instruction Cache Programming Model
0000_0000_0000_0000 Write (R/W by debug module) Field — CEIB DCM DBWE — — CLNF Reset 0000_0000_0000_0000 Write (R/W by debug module) 0x002 Figure 4-4. Cache Control Register (CACR) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 4-12 Freescale Semiconductor...
Page 115: Cacr Field Descriptions
Operand write cycles are effectively decoupled between the processor's local bus and the external bus. 7–6 — Reserved, should be cleared. Default write protect. 0 Read and write accesses permitted 1 Write accesses not permitted 4–2 — Reserved, should be cleared. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 4-13...
Page 116: Access Control Registers (Acr0 And Acr1)
00 Match addresses only in user mode 01 Match addresses only in supervisor mode 1x Execute cache matching on all accesses 12–7 — Reserved; should be cleared. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 4-14 Freescale Semiconductor...
Page 117 Reserved, should be cleared. Write protect. Selects the write privilege of the memory region. 0 Read and write accesses permitted 1 Write accesses not permitted 1–0 — Reserved, should be cleared. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 4-15...
Page 118 Local Memory ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 4-16 Freescale Semiconductor...
Page 119: Debug Support
External development systems can access saved data because the hardware supports concurrent operation of the processor and BDM-initiated commands. See Section 5.6, “Real-Time Debug Support.” ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 120: Signal Description
The PST value is updated each processor cycle. Figure 5-2 shows PSTCLK timing with respect to PST and DDATA. PSTCLK DDATA Figure 5-2. PSTCLK Timing ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 121: Real-Time Trace Support
PST marker value preceding the DDATA nibble that begins the data output. See Section 5.3.1, “Begin Execution of Taken Branch (PST = 0x5).” 0110 Reserved 0111 Begin execution of return from exception (RTE) instruction. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 122: Begin Execution Of Taken Branch (Pst = 0X5)
3. The new target address is optionally available on subsequent cycles using the DDATA port. The number of bytes of the target address displayed on this port is configurable (2, 3, or 4 bytes). ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 123: Programming Model
CSR[IPW]). BDM commands must not be issued if the MCF5272 is using the WDEBUG instruction to access debug module registers or the resulting behavior is undefined. These registers, shown in Figure 5-4, are treated as 32-bit quantities, regardless of the number of implemented bits. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 124: Debug Programming Model
CPU through the WDEBUG instruction. CSR is write-only from the programming model. It can be read or written through the BDM port using the commands. RDMREG WDMREG ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 125: Revision A Shared Debug Resources
Read/write. R is compared with the R/W signal of the processor’s local bus. 6–5 Size. Compared to the processor’s local bus size signals. 00 Longword 01 Byte 10 Word 11 Reserved ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 126 TT = 11 (acknowledge/CPU space transfers): 000 CPU space access 001–111 Interrupt acknowledge levels 1–7 These bits also define the TM encoding for BDM memory commands (for backward compatibility). ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 127: Address Breakpoint Registers (Ablr, Abhr)
Table 5-7 describes ABHR fields. Table 5-7. ABHR Field Description Bits Name Description 31–0 Address High address. Holds the 32-bit address marking the upper bound of the address breakpoint range. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 128: Configuration/Status Register (Csr)
Reserved, should be cleared. Inhibit processor writes. Setting IPW inhibits processor-initiated writes to the debug module’s programming model registers. IPW can be modified only by commands from the external development system. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 5-10 Freescale Semiconductor...
Page 129 On receipt of the command, the processor executes the next instruction and halts again. This process continues until SSM is cleared. 3–0 — Reserved, should be cleared. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 5-11...
Page 130: Data Breakpoint/Mask Registers (Dbr, Dbmr)
32-bit data bus. Table 5-11. Access Size and Operand Data Location A[1:0] Access Size Operand Location Byte D[31:24] Byte D[23:16] Byte D[15:8] Byte D[7:0] Word D[31:16] Word D[15:0] Longword D[31:0] ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 5-12 Freescale Semiconductor...
Page 131: Program Counter Breakpoint/Mask Registers (Pbr, Pbmr)
PC breakpoint mask. A zero in a bit position causes the corresponding PBR bit to be compared to the appropriate PC bit. Set PBMR bits cause PBR bits to be ignored. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 132: Trigger Definition Register (Tdr)
— Reserved, should be cleared. 29/13 Enable breakpoint. Global enable for the breakpoint trigger. Setting TDR[EBL] enables a breakpoint trigger. Clearing it disables all breakpoints at that level. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 5-14 Freescale Semiconductor...
Page 133: Background Debug Mode (Bdm)
Although some BDM operations, such as CPU register accesses, require the CPU to be halted, other BDM commands, such as memory accesses, can be executed while the processor is running. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 134: Cpu Halt
STOP opcode. CSR[27–24] indicates the halt source, showing the highest priority source for multiple halt conditions. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 5-16 Freescale Semiconductor...
Page 135: Bdm Serial Interface
C4—DSO changes to next value. NOTE A not-ready response can be ignored except during a memory-referencing cycle. Otherwise, the debug module can accept a new serial transfer after 32 processor clock periods. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 5-17...
Page 136: Receive Packet Format
Control. This bit is reserved. Command and data transfers initiated by the development system should clear C. 15–0 Data Contains the data to be sent from the development system to the debug module. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 5-18 Freescale Semiconductor...
Page 137: Bdm Command Set
0x4 is a three-bit field. Unassigned command opcodes are reserved by Freescale. All unused command formats within any revision level perform a and return the illegal command response. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 5-19...
Page 138: Coldfire Bdm Command Format
Operands and addresses are transferred most-significant word first. In the following descriptions of the BDM command set, the optional set of extension words is defined as address, data, or operand data. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 5-20...
Page 139: Command Sequence Diagrams
NOTE A not-ready response can be ignored except during a memory-referencing cycle. Otherwise, the debug module can accept a new serial transfer after 32 processor clock periods. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 5-21...
Page 140: Command Set Descriptions
"NOT READY" BERR Figure 5-18. RAREG RDREG Command Sequence Operand Data: None Result Data: The contents of the selected register are returned as a longword value, most-significant word first. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 5-22 Freescale Semiconductor...
Page 141: Write A/D Register ( Wareg / Wdreg )
Longword data is written into the specified address or data register. The data is supplied most-significant word first. Result Data Command complete status is indicated by returning 0xFFFF (with S cleared) when the register write is complete. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 5-23...
Page 142: Read Memory Location ( Read )
Word results return 16 bits of data; longword results return 32. Bytes are returned in the LSB of a word result, the upper byte is undefined. 0x0001 (S = 1) is returned if a bus error occurs. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 5-24 Freescale Semiconductor...
Page 143: Write Memory Location ( Write )
Command Formats: Byte A[31:16] A[15:0] D[7:0] Word A[31:16] A[15:0] D[15:0] Longword A[31:16] A[15:0] D[31:16] D[15:0] Figure 5-23. WRITE Command Format ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 5-25...
Page 144: Write Command Sequence
Command complete status is indicated by returning 0xFFFF (with S cleared) when the register write is complete. A value of 0x0001 (with S set) is returned if a bus error occurs. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 5-26 Freescale Semiconductor...
Page 145: Dump Memory Block ( Dump )
DUMP (LONG) MEMORY "NOT READY" LOCATION NEXT CMD NEXT CMD LS RESULT MS RESULT NEXT CMD NEXT CMD "ILLEGAL" "NOT READY" BERR "NOT READY" Figure 5-26. Command Sequence DUMP ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 5-27...
Page 146: Fill Memory Block ( Fill )
The size field is examined each time a command is processed, allowing the operand size to be altered FILL dynamically. Command Formats: Byte D[7:0] Word D[15:0] Longword D[31:16] D[15:0] Figure 5-27. Command Format FILL ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 5-28 Freescale Semiconductor...
Page 147: Resume Execution ( Go )
Command Format Command Sequence: NEXT CMD "CMD COMPLETE" Figure 5-30. Command Sequence Operand Data: None Result Data: The command-complete response (0xFFFF) is returned during the next shift operation. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 5-29...
Page 148: No Operation ( Nop )
Program register (PC) 0x801 Vector base register (VBR) 0xC04 RAM base address register (RAMBAR) 0x804 MAC status register (MACSR) 0xC0F Module base address (MBAR) 0x805 MAC mask register (MASK) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 5-30 Freescale Semiconductor...
Page 149: Write Control Register ( Wcreg )
"NOT READY" WRITE WRITE LS DATA MEMORY CONTROL "NOT READY" "NOT READY" LOCATION REGISTER NEXT CMD "CMD COMPLETE" BERR NEXT CMD "NOT READY" Figure 5-36. Command Sequence WCREG ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 5-31...
Page 150: Read Debug Module Register ( Rdmreg )
Command Sequence RDMREG Operand Data: None Result Data: The contents of the selected debug register are returned as a longword value. The data is returned most-significant word first. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 5-32 Freescale Semiconductor...
Page 151: Write Debug Module Register ( Wdmreg )
WDEBUG instruction. Only CSR is readable using the external development system. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 5-33...
Page 152: Theory Of Operation
The core enters emulator mode when exception processing begins. After the standard 8-byte exception stack is created, the processor fetches a unique exception vector, 12, from the vector table. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 5-34 Freescale Semiconductor...
Page 153: Emulator Mode
After the debug module bus cycle, the processor reclaims the bus. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 5-35...
Page 154: Processor Status, Ddata Definition
In this definition, the ‘y’ suffix generally denotes the source and ‘x’ denotes the destination operand. For a given instruction, the optional operand data is displayed only for those effective addresses referencing memory.The ‘DD’ nomenclature refers to the DDATA outputs. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 5-36 Freescale Semiconductor...
Page 155: Pst/Ddata Specification For User-Mode Instructions
PST = 0x5, {PST = [0x9AB], DD = target address}, {PST = 0xB , DD = destination operand} <ea>y,Ax PST = 0x1 link.w Ay,#imm PST = 0x1, {PST = 0xB, DD = destination operand} ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 5-37...
Page 156 PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination} ori.l #imm,Dx PST = 0x1 <ea>y PST = 0x1, {PST = 0xB, DD = destination operand} pulse PST = 0x4 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 5-38 Freescale Semiconductor...
Page 157 For all types of exception processing, the PST = 0xC value is driven at all times, unless the PST output is needed for one of the optional marker values or for the taken branch indicator (0x5). ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 158: Supervisor Instruction Set
Similar to the exception processing mode, the stopped state (PST = 0xE) and the halted state (PST = 0xF) display this status throughout the entire time the ColdFire processor is in the given mode. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 5-40...
Page 159: Freescale-Recommended Bdm Pinout
PST3 PST1 PST2 DDATA3 PST0 DDATA1 DDATA2 DDATA0 Freescale reserved Freescale reserved PSTCLK Core-Voltage 1Pins reserved for BDM developer use. 2Supplied by target Figure 5-41. Recommended BDM Connector ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 5-41...
Page 160 Debug Support ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 5-42 Freescale Semiconductor...
Page 161: System Integration Module (Sim)
CSORs CSBRs PIWR Four SDRAM Timer General- PIVR SDTR Purpose Timers 32-Bit Data Bus DRAM Controller Outputs CS[7:0] 32-Bit Address Bus INT[6:1] Control Signals Figure 6-1. SIM Block Diagram ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 162: Programming Model
Section 6.2.2, “Module Base Address Register (MBAR).” Because SIM registers depend on the base address defined in MBAR[BA], MBAR must be programmed before SIM registers can be accessed. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 163: Module Base Address Register (Mbar)
All internal peripheral registers occupy a single relocatable memory block along 64-Kbyte boundaries. If MBAR[V] is set, MBAR[BA] is compared to the upper 16 bits of the full 32-bit internal address to ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 164: Module Base Address Register (Mbar)
The following example shows how to set the MBAR to location 0x1000_0000 using the D0 register. Setting MBAR[V] validates the MBAR location. This example assumes all accesses are valid: move.1 #0x10000001,DO movec DO,MBAR ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 165: System Configuration Register (Scr)
GPIO module, and SDRAM controller, and asserts RSTO. The CPU is not reset. The reset remains asserted for 128 clock cycles. This bit is automatically cleared on negation of the reset. 5–4 — Reserved, should be cleared. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 166: System Protection Register (Spr)
PE, PEEN Peripheral error. This bit is set when an access to an on-chip peripheral is terminated with a transfer error. If PEEN is also set, the bus cycle is terminated with an access error exception. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 167: Power Management Register (Pmr)
Reset 0000_0000 R/W, Supervisor mode only Field — SLPEN — Reset 0000_0000 R/W, Supervisor mode only Address MBAR+0x008 Figure 6-5. Power Management Register (PMR) Table 6-5 describes PMR fields. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 168: Timer Module
UART0RxD, at which time this bit is automatically cleared. 0 Clock enabled. 1 Clock disabled. 15-11 — Reserved, should be cleared. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 169: Usb And Usart Power Down Modes
Module in power down and can only be reactivated by clearing PDN. Module in power down and can be reactivated by clearing PDN or detecting signal on the receive pins. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 170: Activate Low-Power Register (Alpr)
Exit Stop USB Wake-on-Ring Interrupts, INT6–INT2 Interrupt, INT1 USART1, USART2 Yes, interrupt and Rx signal change QSPI Yes, interrupt and Rx signal change PLIC Yes, interrupt General purpose I/O ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 6-10 Freescale Semiconductor...
Page 171: Device Identification Register (Dir)
If this periodic servicing action does not occur, the timer counts until it reaches the reset timeout value, resulting in a hardware reset with RSTO driven low for 16 clocks. SCR[RSTSRC] is updated to indicate that the software watchdog caused the reset. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 6-11...
Page 172: Watchdog Reset Reference Register (Wrrr)
6-9, contains the reference value for the software watchdog timeout causing an interrupt. Field Reset 1111_1111_1111_1110 Address MBAR + 0x284 Figure 6-9. Watchdog Interrupt Reference Register (WIRR) Table 6-10 describes WIRR fields. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 6-12 Freescale Semiconductor...
Page 173: Watchdog Counter Register (Wcr)
WIE is cleared by writing a 1 to it. The timer does not negate the interrupt request to the interrupt controller until WIE is cleared. WIE is set regardless of the state of WIRR[IEN]; however, an interrupt is not asserted to the controller unless WIRR[IEN] = 1. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 6-13...
Page 174 System Integration Module (SIM) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 6-14 Freescale Semiconductor...
Page 175: Interrupt Controller
CPU from low-power sleep or stop mode. • The programmable interrupt vector register (PIVR) specifies which vector number is returned in response to an interrupt acknowledge cycle. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 176: Interrupt Controller Registers
(vectors 64–255). The location of these vectors is programmable through the PIVR. For more information on the servicing of interrupts, see ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 177: Coldfire Core
Ethernet module non-time-critical interrupt QSPI Queued serial peripheral interface IPL2, IPL1, IPL0 Interrupt priority level bits 2–0 Pending interrupt Power down enable Wakeup enable SWTO Software watchdog timer time out ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 178: Interrupt Control Registers (Icr1-Icr4)
000 The corresponding INT source is inhibited and cannot generate interrupts. The state of the signal 18–16, can still be read in the ISR. 14-12, 001–111The corresponding INT source is enabled and generates an interrupt with the indicated priority 10–8, level. 6–4, 2–0 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 179: Interrupt Control Register 2 (Icr2)
Field QSPIPI QSPIIPL INT5PI INT5IPL INT6PI INT6IPL SWTOPI SWTOIPL Reset 0000_0000_0000_0000 Field — Reset 0000_0000_0000_0000 Addr MBAR + 0x02C Figure 7-5. Interrupt Control Register 4(ICR4) Table 7-3 describes ICR4 fields. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 180: Interrupt Source Register (Isr)
ISR fields. Table 7-4. ISR Field Descriptions Bits Field Description 31–4 — 0 Interrupt source is high. 1 Interrupt source is low. 3–0 — Reserved, should be cleared. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 181: Programmable Interrupt Transition Register (Pitr)
0 Triggering edge of external interrupt input is high-to-low (negative edge triggered). 6, 5 1 Triggering edge of external interrupt input is low -to-high (positive edge triggered). 27–7, — Reserved, should be cleared. 4–0 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 182: Programmable Interrupt Wakeup Register (Piwr)
31–4 — 0 Interrupt cannot wake up the CPU when interrupt source is active. 1 Interrupt wakes up the CPU from low-power modes. 3–0 — Reserved, should be cleared. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 183: Programmable Interrupt Vector Register (Pivr)
These bits provide the high three bits of the interrupt vector for interrupt acknowledge cycles from all sources. To conform to the core interrupt vector allocation, these bits should be set equal to or greater than 010. See Table 2-3. — Reserved, should be cleared. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 184: Mcf5272 Interrupt Vector Table
Queued Serial Peripheral Interface 11010 INT5 External Interrupt Input 5 11011 INT6 External Interrupt Input 6 11100 SWTO Software Watchdog Timer Timeout 11101 Reserved Reserved 11110 Reserved Reserved 11111 Reserved Reserved ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 7-10 Freescale Semiconductor...
Page 185: Chip Select Module
CS7 must be used for enabling an external SDRAM array. In this mode, it is referred to as SDCS. NOTE A detailed description of each bus access type supported by the MCF5272 device is given in Chapter 20, “Bus Operation.” ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 186: Boot Cs0 Operation
+ 0x07C CSOR7 CS option register 7 0xFFFF_F078 The nibble shown as x resets as 00xx, where the undefined bits represent the BW field. QSPI_CS0/BUSW0 and QSPI_CLK/BUSW1 program the bus width for CS0 at reset ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 187: Chip Select Base Registers (Csbr0-Csbr7)
Transfer type. TT and TM may be used to further qualify the address match. If CTM is set, TT and TM must match the access types for the chip select to assert. See the description of TM. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 188: Output Read/Write Strobe Levels Versus Chip Select Ebi Code
The MCF5272 compares the address for the current bus transfer with the address and mask bits in the CSBRs and CSORs looking for a match. The priority is listed in Table 8-4 (from highest priority to lowest priority): ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 189: Chip Select Option Registers (Csor0-Csor7)
0 Do not hold address, data, and attribute signals an extra cycle after chip select and R/W negate on writes. 1 Hold address, data, and attribute signals an extra cycle after CSx and R/W negate on writes. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 190 0 Memory covered by chip select is read/write. The memory covered by the chip select is neither read nor write protected. 1 RW determines whether memory covered by chip select is read only or write only. A conflict causes either a read or write protect violation. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 191: Sdram Controller
RAS0, CAS0, SDWE, SDBA[0:1], SDCLKE, A10_PRECHG, and the SDRAM bank selects are dedicated SDRAM signals. Figure 9-1 shows the SDRAM controller signal configuration. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 192 SDRAM controller bank address select outputs. Assigned to internal high-order address signals by programming SDCR[BALOC]. This allows using SDRAM devices of different sizes without changing the board layout. See Table 9-7. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 193: Pin Tsop Sdram Pin Definition
DQ15 DQ14 DQ14 DQ14 DQ13 DQ13 DQ13 DQ12 DQ12 DQ12 DQ11 DQ11 DQ11 DQ10 DQ10 DQ10 DQML DQML DQML DQMH DQMH DQMH Figure 9-2. 54-Pin TSOP SDRAM Pin Definition ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 194: Interface To Sdram Devices
16 or 32 bits by appropriate configuration of the WSEL signal during reset. See Section 19.18, “Operating Mode Configuration Pins.” The following tables describe address pin connections and internal address multiplexing. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 195: Internal Address Multiplexing (16-Bit Data Bus)
A7/A15 A7/A16 A7/A16 A7/A15 A7/A15 A8/A17 A8/A17 A8/A16 A8/A16 A8/A17 A8/A17 A8/A16 A8/A16 A9/A18 A9/A18 A9/A17 A9/A17 A9/A18 A9/A18 A9/A17 A9/A17 A10/A19 A10/A19 A10/A19 A10/A19 A10_PRECHG A10/AP SDBA0 SDBA1 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 196: Sdram Banks, Page Hits, And
Write — MCAS — BALOC — INV SLEEP ACT INIT Reset Read/Write Read-only Addr MBAR + 0x0182 Figure 9-3. SDRAM Configuration Register (SDCR) Table 9-7 describes SDCR fields. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 197: Sdcr Field Descriptions
Initialization starts after the first dummy write access to the SDRAM. CSOR7, CSBR7, and SDTR must be configured before setting INIT. CAUTION: CSOR7[WAITST] must equal 0x1F when CS7/SDCS is configured for SDRAM. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 198: Sdram Timing Register (Sdtr)
Reserved, should be cleared. 5–4 Precharge time. Specifies number of clock cycles taken for a precharge (RP + 1). 00 1 cycle 01 2 cycles (default) 10 3 cycles 11 4 cycles ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 199: Auto Initialization
In self-refresh mode, SDRAM devices can refresh themselves without an external clock. After power-down completes, SDCR[SLEEP] is set, the SDRAM clock output is driven high, and SDCLKE is driven low. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 200: Performance
8-1-1-1 = 11 Page hit 5-1-1-1 = 8 6-1-1-1 = 9 Burst write Page miss 5-1-1-1 = 8 5-1-1-1 = 8 Page hit 3-1-1-1 = 6 3-1-1-1 = 6 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 9-10 Freescale Semiconductor...
Page 201: Sdram Controller Performance (Rcd = 1, Rp = 1), 16-Bit Port
Page miss 8-1-1-1-1-1-1-1 = 15 9-1-1-1-1-1-1-1 = 16 Page hit 5-1-1-1-1-1-1-1 = 12 6-1-1-1-1-1-1-1 = 13 Burst write Page miss 6-1-1-1-1-1-1-1 = 13 6-1-1-1-1-1-1-1 = 13 Page hit 3-1-1-1-1-1-1-1 = 10 3-1-1-1-1-1-1-1 = 10 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 9-11...
Page 202: Solving Timing Issues With Sdcr[Inv]
Internal CLK Data bus Data setup delay SDCLK External delay of SDCLK Figure 9-5. Example Setup Time Violation on SDRAM Data Input during Write ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 9-12 Freescale Semiconductor...
Page 203: Timing Refinement With Inverted Sdclk
SDRAM read access time Delay SDCLK to CLK Shifted delay of SDCLK < 0 => true CAS latency SDCLK_to_CLK Figure 9-7. Timing Refinement with True CAS Latency and Inverted SDCLK ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 9-13...
Page 204: Sdram Interface
If SDRAM EBI mode is used, CSOR7[WAITST] should be programmed for 0x1F to ensure that the internal bus cycle termination signal is sourced from the SDRAM controller and not the chip select module. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 9-14 Freescale Semiconductor...
Page 205: Sdram Read Accesses
SDTR[RCD]. For lower clock speed systems the RCD value could be written as 00 and this clock cycle can be removed. Consult the data sheets of the SDRAM devices being used. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 206: Sdram Burst Read, 32-Bit Port, Page Miss, Access = 9-1-1-1
Bank y Bank y CASL = 2 Data Data Data Data D[31:0] SDCS RAS0 CAS0 SDWE BS[3:0] Figure 9-9. SDRAM Burst Read, 32-Bit Port, Page Miss, Access = 9-1-1-1 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 9-16 Freescale Semiconductor...
Page 207: Sdram Burst Read, 32-Bit Port, Page Hit, Access = 5-1-1-1
Miss? SDCLKE SDADR[13:0] A10_PRECHG SDBA[1:0] Bank SDCS RAS0 CAS0 SDWE BS[3:0] Data Data Data Data D[31:0] Figure 9-10. SDRAM Burst Read, 32-Bit Port, Page Hit, Access = 5-1-1-1 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 9-17...
Page 208: Sdram Write Accesses
Bank x Bank y Bank y SDCS RAS0 CAS0 SDWE BS[3:0] Data Data Data Data D[31:0] Figure 9-11. SDRAM Burst Write, 32-Bit Port, Page Miss, Access = 7-1-1-1 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 9-18 Freescale Semiconductor...
Page 209: Sdram Burst Write, 32-Bit Port, Page Hit, Access = 3-1-1-1
Miss? SDCLKE SDADR[13:0] A10_PRECHG SDBA[1:0] Bank SDCS RAS0 CAS0 SDWE BS[3:0] Data Data Data Data D[31:0] Figure 9-12. SDRAM Burst Write, 32-Bit Port, Page Hit, Access = 3-1-1-1 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 9-19...
Page 210: Sdram Refresh Timing
Note that self refresh occurs during T3. In refresh state, SDRAM cannot accept any other command. SDCLK Next Command Precharge Auto All Banks Refresh SDCLKE SDADR[13:0] A10_PRECHG SDBA[1:0] SDCS RAS0 CAS0 SDWE Figure 9-13. SDRAM Refresh Cycle ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 9-20 Freescale Semiconductor...
Page 211: Enter Sdram Self-Refresh Mode
Internal Clock SDCLK Precharge Self All Banks NOP Refresh SDCR[SLEEP] SDCLKE SDADR[13:0] A10_PRECHG SDBA[1:0] SDCS RAS0 CAS0 SDWE Figure 9-14. Enter SDRAM Self-Refresh Mode ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 9-21...
Page 212: Exit Sdram Self-Refresh Mode
If it is 0, as it is here, SDRAM controller signals become active on the following negative clock edge. Internal Clock SDCLK SDCR[GSL] SDCR[SLEEP] SDCLKE SDADR[13:0] A10_PRECHG SDBA[1:0] SDCS RAS0 CAS0 SDWE Figure 9-15. Exit SDRAM Self-Refresh Mode ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 9-22 Freescale Semiconductor...
Page 213: Dma Controller
Byte (8 bits) Word (16 bits) Longword (32 bits) Burst (4 x longword) Note that transfers to on-chip peripherals are limited by the transfer type supported by a specific peripheral. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 10-1...
Page 214: Dma Address Modes
DMA interrupt flags (see Section 10.3.2, “DMA Interrupt Register (DIR)”) do not prevent transfers from going ahead. 29–20 — Reserved, should be cleared. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 10-2 Freescale Semiconductor...
Page 215 CSCRn[TM] value used for external RAM or peripheral device access. 000 Reserved 001 User data access 010 User code access 011 Reserved 100 Reserved 101 Supervisor data access 110 Supervisor code access 111 Reserved ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 10-3...
Page 216: Dma Interrupt Register (Dir)
0 TE interrupt is disabled. 1 TE interrupt is enabled. TCEN Transfer complete interrupt enable. 0 TC interrupt is disabled. 1 TC interrupt is enabled. 7–5 — Reserved, should be cleared. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 10-4 Freescale Semiconductor...
Page 217: Dma Source Address Register (Dsar)
The address value is altered after each read access according to the addressing mode. Field SRCADR Reset 0000_0000_0000_0000_0000_0000_0000_0000 Addr MBAR + 0x00EC Figure 10-3. DMA Source Address Register (DSAR) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 10-5...
Page 218: Dma Destination Address Register (Ddar)
ASC flag. 24 23 Field — BYTCNT Reset 0000_0000_0000_0000_0000_0000_0000_0000 Addr MBAR + 0x00E8 Figure 10-5. DMA Byte Count Register (DBCR) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 10-6 Freescale Semiconductor...
Page 219: Ethernet Module
Automatic internal flushing of the receive FIFO for runts and collisions with no processor bus use 11.2 Module Operation The FEC is implemented using a combination of hardware and microcode. Figure 11-1 shows a functional block diagram of this module. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 11-1...
Page 220: Ethernet Block Diagram
FIFO Controller Controller RAM I/F Descriptor Controller CSRs Receive Transmit E_RxCLK E_TxCLK E_RxDV E_TxEN E_MDC E_RxD[3:0] E_TxD[3:0] E_MDIO E_RxER E_TxER E_CRS,E_COL Figure 11-2. Fast Ethernet Module Block Diagram ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 11-2 Freescale Semiconductor...
Page 221: Transceiver Connection
Transmit error E_TxER Collision E_COL Carrier sense E_CRS Receive clock E_RxCLK Receive enable E_RxDV Receive data E_RxD[3:0] Receive error E_RxER Management channel clock E_MDC Management channel serial data E_MDIO ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 11-3...
Page 222: Fec Frame Transmission
(carrier sense is active). Before transmitting, the controller waits for carrier sense to become inactive. When carrier sense goes inactive, the controller waits to verify that it ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 11-4...
Page 223: Fec Frame Reception
After bit time 21, the data sequence is monitored for a valid start-of-frame delimiter (SFD) of 11. If a 00 is detected, the frame is rejected. When a 11 is detected, the PA/SFD sequence is complete. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 224: Cam Interface
The difference between an individual address and a group address is determined by the I/G bit in the destination address field. A flowchart for address recognition on received frames is illustrated in Figure 11-4 and summarized in Table 11-3. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 11-6 Freescale Semiconductor...
Page 225: Ethernet Address Recognition Flowchart
True Perfect Match Receive Frame True (RCR[PROM] = 1) Promiscuous Mode False Receive Frame (RCR[PROM] = 0) Set Miss Bit Discard Frame Figure 11-4. Ethernet Address Recognition Flowchart ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 11-7...
Page 226: Hash Table Algorithm
For internal loopback, set LOOP and clear DRT. E_TxEN and E_TxER cannot assert during internal loopback. For external loopback, clear LOOP, set DRT, and configure the external transceiver for loopback. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 11-8 Freescale Semiconductor...
Page 227: Ethernet Error-Handling Procedure
When the receive frame length exceeds R_HASH[MAX_FRAME_LENGTH], EIR[BABR] is set indicating Violation babbling receive error, and the LG bit in the end of frame RxBD is set. Note: Receive frames exceeding 2047 bytes are truncated. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 11-9...
Page 228: Programming Model
Pointer to transmit descriptor ring, [p. 11-31] 0xC18 EMRBR Maximum receive buffer size, [p. 11-32] 0xC40– EFIFO FIFO RAM space 0xDFF The following sections describe each register in detail. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 11-10 Freescale Semiconductor...
Page 229: Ethernet Control Register (Ecr)
This bit is automatically cleared by hardware once the reset sequence is complete (approximately 16 clock cycles after being set). ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 11-11...
Page 230: Interrupt Event Register (Eir)
FEC bus error. A bus error occurred when the FEC was accessing an internal bus. UMINT Unmasked interrupt status. An interrupt is currently being asserted to the interrupt controller. This bit is not maskable. 20–0 — Reserved, should be cleared. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 11-12 Freescale Semiconductor...
Page 231: Interrupt Mask Register (Eimr)
EIR bit reflects the state of the interrupt signal even if the corresponding EIMR bit is set. 0 The corresponding interrupt source is masked . 1 The corresponding interrupt source is not masked. 21–0 — Reserved, should be cleared. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 11-13...
Page 232: Interrupt Vector Status Register (Ivsr)
00 No pending FEC interrupt 01 Non-time critical interrupt (All interrupts except TXB, TXF, RXB, and RXF.) 10 Transmit interrupt 11 Receive interrupt 1–0 — Reserved, should be cleared. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 11-14 Freescale Semiconductor...
Page 233: Receive Descriptor Active Register (Rdar)
Set when this register is written, regardless of the value written. Cleared by the FEC whenever no additional empty descriptors remain in the receive ring. 23–0 — Reserved, should be cleared. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 11-15...
Page 234: Transmit Descriptor Active Register (Tdar)
Set to one when this register is written, regardless of the value written. Cleared by the FEC whenever no additional ready descriptors remain in the transmit ring. 23–0 — Reserved, should be cleared. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 11-16 Freescale Semiconductor...
Page 235: Mii Management Frame Register (Mmfr)
Once the write management frame operation completes, the MII interrupt is generated. At this time, the contents of the MMFR register match the original value written. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 236: Mii Speed Control Register (Mscr)
Any non-zero value results in an E_MDC frequency given by the following formula: MDC_FREQUENCY = system frequency / (4 * MII_SPEED) — Reserved, should be cleared. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 11-18 Freescale Semiconductor...
Page 237: Fifo Receive Bound Register (Frbr)
— Reserved, should be cleared. 10–2 R_BOUND End of FIFO RAM. This field contains the ending address of the FIFO RAM, exclusive. 1–0 — Reserved, should be cleared. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 11-19...
Page 238: Fifo Receive Start Register (Frsr)
Reserved, should be set. 9–2 R_FSTART Receive FIFO starting address. Address of first receive FIFO location. Acts as delimiter between receive and transmit FIFOs. 1–0 — Reserved, should be cleared. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 11-20 Freescale Semiconductor...
Page 239: Transmit Fifo Watermark (Tfwr)
FIFO is full before the selected number of bytes are written. The options are: 0X 64 bytes written to transmit FIFO 10 128 bytes written to transmit FIFO 11 192 bytes written to transmit FIFO ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 11-21...
Page 240: Fifo Transmit Start Register (Tfsr)
— Reserved, should be cleared. — Reserved, should be set. 9–2 X_FSTART Transmit FIFO starting address. Address of first transmit FIFO location. 1–0 — Reserved, should be cleared. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 11-22 Freescale Semiconductor...
Page 241: Receive Control Register (Rcr)
Internal loopback. If set, transmitted frames are looped back internal to the FEC and the transmit output signals are not asserted. The system clock is substituted for the E_TxCLK when LOOP is asserted. DRT must be set to zero when asserting LOOP. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 11-23...
Page 242: Maximum Frame Length Register (Mflr)
(up to 2k-1). The recommended default value to be programmed by the user is 1518 or 1522 (if VLAN Tags are supported). ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 11-24 Freescale Semiconductor...
Page 243: Transmit Control Register (Tcr)
The frame is transmitted again once GTS is cleared. Note that there may be old frames in the transmit FIFO that are transmitted when GTS is reasserted. To avoid this, deassert ETHER_EN following the GRA interrupt. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 11-25...
Page 244: Ram Perfect Match Address Low (Malr)
Table 11-23. MALR Field Descriptions Bits Name Description 31–0 ADDR_LOW Bytes 0 (bits 31–24), 1 (bits 23–16), 2 (bits 15:8), and 3 (bits 7–0) of the 6-byte address. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 11-26 Freescale Semiconductor...
Page 245: Ram Perfect Match Address High (Maur)
Figure 11-21. RAM Perfect Match Address High (MAUR) Table 11-24. MAUR Field Descriptions Bits Name Description 31–0 ADDR_HIGH Bytes 4 (bits 31–24) and 5 (bits 23–16) of the 6-byte address. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 11-27...
Page 246: Hash Table High (Htur)
The HTUR register contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. Bit 31 of HTUR contains hash index bit 63. Bit 0 of HTUR contains hash index bit 32. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 11-28 Freescale Semiconductor...
Page 247: Hash Table Low (Htlr)
The HTLR register contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. Bit 31 of HTLR contains hash index bit 31. Bit 0 of HTLR contains hash index bit 0. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 11-29...
Page 248: Pointer-To-Receive Descriptor Ring (Erdsr)
Figure 11-24. Pointer-to-Receive Descriptor Ring (ERDSR) Table 11-27. ERDSR Field Descriptions Bits Name Description 31–2 R_DES_START Pointer to start of receive buffer descriptor queue. 1–0 — Reserved, should be cleared. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 11-30 Freescale Semiconductor...
Page 249: Pointer-To-Transmit Descriptor Ring (Etdsr)
Figure 11-25. Pointer-to-Transmit Descriptor Ring (ETDSR) Table 11-28. ETDSR Field Descriptions Bits Name Description 31–2 X_DES_START Pointer to start of transmit buffer descriptor queue. 1–0 — Reserved, should be cleared. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 11-31...
Page 250: Receive Buffer Size Register (Emrbr)
Figure 11-26. Receive Buffer Size (EMRBR) Table 11-29. EMRBR Field Descriptions Bits Name Description 31–11 — Reserved, should be cleared. 10–4 R_BUFF_SIZE Receive buffer size. 3–0 — Reserved, should be cleared. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 11-32 Freescale Semiconductor...
Page 251: 11.5.22 Initialization Sequence
11-32. Table 11-32. User Initialization Process (before ETHER_EN) Step Description Set EIMR Clear EIR Set IVSR (define ILEVEL) Set FRSR (optional) Set TFSR (optional) Set MAUR and MALR ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 11-33...
Page 252: 11.5.24 Fec Initialization
The FEC uses status and control fields in the BDs to inform the core that the buffers have been serviced, to confirm reception and transmission events, or to indicate error conditions. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 11-34...
Page 253: Fec Buffer Descriptor Tables
Rx Data Buffer Pointer A[31–16] Rx Data Buffer Pointer A[15–0] Figure 11-27. Receive Buffer Descriptor (RxBD) The first word of the RxBD contains control and status bits. Its format is detailed below. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 11-35...
Page 254: Rxbd Field Descriptions
16. The buffer must reside in memory external to the FEC. NOTE Anytime the software driver sets an E bit in a receive descriptor, the driver should immediately write to RDAR. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 11-36 Freescale Semiconductor...
Page 255: Ethernet Transmit Buffer Descriptor
Defer indication. Written by the FEC and is only valid if L = 1. The FEC had to defer while trying to transmit a frame. This bit is not set if a collision occurs during transmission. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 256 This situation can occur if the FEC cannot access an internal bus, or if the next BD in the frame is not available. NOTE Anytime the software driver sets an R bit in a transmit descriptor, the driver should immediately write to TDAR. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 11-38 Freescale Semiconductor...
Page 257: Differences Between Mcf5272 Fec And Mpc860T Fec
MCF5272 ethernet controller signal names are generally identical to those used in the MPC860T, except for a prefix of ‘E_’. For example, MDC in the MPC860T corresponds to E_MDC in the MCF5272. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 11-39...
Page 258 Ethernet Module ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 11-40 Freescale Semiconductor...
Page 259: Universal Serial Bus (Usb)
USB device controller with protocol control and administration for up to eight endpoints, 16 interfaces, and 16 configurations • Programmable endpoint types with support for up to eight control, interrupt, bulk, or isochronous endpoints • Independent interrupts for each endpoint ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 12-1...
Page 260: Module Operation
A block diagram of the USB module is shown in Figure 12-2. The module is partitioned into five functional blocks. These blocks are USB internal transceiver, clock generator, USB control logic, USB request processor, and endpoint controllers. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 12-2 Freescale Semiconductor...
Page 261: Usb Transceiver Interface
A if these pins are configured for USB, using the PACNT register, 17.2.1, “Port A Control Register (PACNT)”. The USB module has separate power pins for the internal transceiver. NOTE USB_GND should always be grounded. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 12-3...
Page 262: Clock Generator
— Serial-to-parallel conversion — CRC validation — NRZI decoding — Bit unstuffing • For error detection: — Bad CRC — Timeout waiting for end-of-packet — Bit stuffing violations ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 12-4 Freescale Semiconductor...
Page 263: Endpoint Controllers
The string descriptors must be stored in external memory and not the configuration RAM. get_interface Returns the selected alternate setting for the specified interface. No user notification is provided. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 12-5...
Page 264 NOTE: The user must read the descriptor structure to determine which endpoints correspond to a given interface. sync_frame Passed to the user as a vendor specific request. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 12-6 Freescale Semiconductor...
Page 265: Register Description And Programming Model
USB Endpoint 4 Control Register (EP4CTL) 0x1060 Reserved USB Endpoint 5 Control Register (EP5CTL) 0x1064 Reserved USB Endpoint 6 Control Register (EP6CTL) 0x1068 Reserved USB Endpoint 7 Control Register (EP7CTL) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 12-7...
Page 266 USB Endpoint 5 Data Present Register (EP5DPR) 0x10E4 Reserved USB Endpoint 6 Data Present Register (EP6DPR) 0x10E8 Reserved USB Endpoint 7 Data Present Register (EP7DPR) 0x1400 – USB Configuration RAM, 1 K Bytes 0x17FF ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 12-8 Freescale Semiconductor...
Page 267: Register Descriptions
10–0 FRM_MAT Frame number match value. Contains the USB frame number match value. When the FNR value equals the value in the register, a FRM_MAT interrupt is generated. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 12-9...
Page 268: Usb Real-Time Frame Monitor Register (Rfmr)
USB bit time and is reset when a SOF packet from the host is detected or an artificial start of frame (ASOF) interrupt is generated. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 12-10 Freescale Semiconductor...
Page 269: Usb Real-Time Frame Monitor Match Register (Rfmmr)
USB function address. This field holds the USB address of the device. The USB module writes this field with the USB address assigned to the device with a SET_ADDRESS device request. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 270: Usb Alternate Settings Register (Asr)
USB alternate settings for interface n. This field indicates which alternate setting is active for each interface. 00 Alternate Setting 0 01 Alternate Setting 1 10 Alternate Setting 2 11 Alternate Setting 3 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 12-12 Freescale Semiconductor...
Page 271: Usb Device Request Data 1 And 2 Registers (Drr1/ 2)
Figure 12-9. USB Device Request Data 1 Register (DRR1) Field wLength Reset 0000_0000_0000_0000 Read Field wIndex Reset 0000_0000_0000_0000 Read Addr MBAR + 0x101C Figure 12-10. USB Device Request Data 2 Register (DRR2) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 12-13...
Page 272: Usb Specification Number Register (Specr)
0 Disabled. The USB host has issued the CLEAR_FEATURE request with the remote wakeup feature selector set, or has not set this feature since a USB or system reset has occurred. 10–3 — Reserved, should be cleared. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 12-14 Freescale Semiconductor...
Page 273: Usb Endpoint 0 In Configuration Register (Iep0Cfg)
Starting address in the FIFO buffer memory for the endpoint’s FIFO. Reading this field returns the current write pointer for IN endpoints or the read pointer for OUT endpoints for the FIFO. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 274: Usb Endpoint 0 Out Configuration Register (Oep0Cfg)
FIFO_ADDR Reset 0000_0000_0000_0000 Addr MBAR + 0x1030, 0x1034, 0x1038, 0x103C, 0x1040, 0x1044, 0x1048 Figure 12-15. USB Endpoint 1–7 Configuration Register Table 12-11 for a description of the fields. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 12-16 Freescale Semiconductor...
Page 275: Usb Endpoint 0 Control Register (Ep0Ctl)
0 Clock is retrieved from the clock selected at reset. 1 Clock is retrieved from the internal system clock. Note: the selected clock must have a frequency of 48 MHz. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 12-17...
Page 276 This command bit is write only and always returns 0 when read. Note: CMD_OVER and CMD_ERR have to be written simultaneously. The CMD_OVER and CMD_ERR bits control the status stage response for vendor and class specific requests. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 12-18 Freescale Semiconductor...
Page 277 NAK responses if the FIFO contains less than a maximum size packet. This bit is set at Reset and on an EOT event. — Reserved, should be cleared. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 12-19...
Page 278: Usb Endpoint 1-7 Control Register (Epnctl)
The FIFO_LVL interrupt is generated when the FIFO fills above (OUT) or falls below (IN) the selected level. IN FIFOOUT FIFO 00 FIFO emptyFIFO full 01 FIFO emptyFIFO full 10 FIFO emptyFIFO full 11 FIFO emptyFIFO full ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 12-20 Freescale Semiconductor...
Page 279 OUT token by the USB host controller. The STALL handshake causes the endpoint to be halted. The STALL bit is not valid for isochronous endpoints. This command bit is write-only and always returns 0 when read. 0 Default 1 Send STALL handshake ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 12-21...
Page 280: Registers (Ep0Isr)
DEV_CFG interrupt is still generated. If debug mode is enabled, a change in FAR also generates an interrupt. 0 No interrupt pending 1 Device configuration change received ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 12-22 Freescale Semiconductor...
Page 281 OUT FIFO threshold level. Indicates that the FIFO level has risen above the level set in the EPCTL0 register. 0 No interrupt pending 1 OUT FIFO threshold level reached ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 12-23...
Page 282 IN FIFO threshold level. This bit indicates that the FIFO level has fallen below the level set in the EPCTL0 register. 0 No interrupt pending 1 IN FIFO threshold level reached ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 12-24 Freescale Semiconductor...
Page 283: Usb Endpoints 1-7 Status / Interrupt Registers (Epnisr)
0 No interrupt pending 1 Packet sent or received successfully UNHALT Endpoint unhalt interrupt. Set when the endpoint n HALT_ST bit is cleared. 0 No interrupt pending 1 Endpoint n unhalted ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 12-25...
Page 284: Usb Endpoint 1-7 Interrupt Mask Registers (Epnimr)
Interrupt mask. These bits are set when the user wants to activate the interrupt source for the specific bit. Refer to Table 12-15 for a description of each interrupt source. 1 Interrupt Enabled 0 Interrupt Disabled ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 12-26 Freescale Semiconductor...
Page 285: Usb Endpoint 0-7 Data Registers (Epndr)
FIFO returns undefined data. These registers can be accessed using 8-, 16-, or 32-bit accesses in order to read/write 1, 2, or 4 bytes from/to the FIFO at one time. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 286: Usb Endpoint 0-7 Data Present Registers (Epndpr)
The MCF5272 uses big endian format for words and longwords. The user must make sure that any word or longword fields are stored in the correct byte order. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 12-28 Freescale Semiconductor...
Page 287: Usb Device Configuration Example
2. Configuration #1 Descriptor 3. Interface #0 Descriptor 4. Endpoint #1 Descriptor 5. Endpoint #2 Descriptor 6. Interface #1 Descriptor 7. Endpoint #3 Descriptor 8. Configuration #2 Descriptor ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 12-29...
Page 288: Usb Module Access Times
Clock cycle access times for back-to-back writes to the configuration RAM are 3-5-5-5-5-5... Access times for writes separated by at least 1 clock cycle are 3-3-3-3-3-3… ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 12-30...
Page 289: Software Architecture And Application Notes
5. Clear all interrupt bits in the EPnISR registers for all active endpoints. 6. Enable the desired interrupt sources in the EPnIMR registers. 7. Clear the DEV_CFG interrupt bit to allow the USB module to access the FIFOs. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 12-31...
Page 290: Fifo Configuration
An example of streaming data is voice. The other endpoint types transfer message based, or bursted data where integrity of the data is more important than timely delivery. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 12-32 Freescale Semiconductor...
Page 291: Control, Bulk, And Interrupt Endpoints
Isochronous endpoints support packet sizes up to 1023 bytes and isochronous packets are never resent. In order to support the large packet sizes, the FIFO size can be less than two times the ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 292: In Endpoints
USB request processor. When the USB module receives a class or vendor request, the parameters for the request are written to the DRR1 and DRR2 registers and the user is notified of the ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 12-34...
Page 293: Endpoint Halt Feature
CLEAR FEATURE • A USB reset signal. • request. CONFIGURATION INTERFACE • On control endpoints, a SETUP token for the next request. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 12-35...
Page 294: Line Interface
Use short, low inductance traces for the analog circuitry to reduce inductive, capacitive, and radio frequency noise sensitivities. • Use short, low inductance traces for digital circuitry to reduce inductive, capacitive, and radio frequency radiated noise. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 12-36 Freescale Semiconductor...
Page 295: Recommended Usb Protection Circuit
ESD protection circuit for the USB. +3.3V +3.3V Schottky Diode 2 x MMBD301LT1 USB Port 1.5K D – 0.1μF Zener Diode 22pF 22pF BZX84C3V3LT1 Figure 12-25. USB Protection Circuit ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 12-37...
Page 296 Universal Serial Bus (USB) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 12-38 Freescale Semiconductor...
Page 297: Physical Layer Interface Controller (Plic)
See Section 13.6, “Application Examples” for further information. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 13-1...
Page 298: Plic System Diagram
DFSC3, is derived from FSC1 and is fed to the port 3 IDL/GCI block. Programming the port 3 sync delay register, P3SDR, allows it to be synchronized with an offset ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 13-2...
Page 299: Gci/Idl Block
CPU services these registers in a timely manner. The MCF5272 has 4 GCI/IDL interfaces. Thus the theoretical maximum is twelve 32-bit data registers to be read. For most applications the typical number is less. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 13-3...
Page 300: Gci/Idl B- And D-Channel Transmit Data Registers
2-KHz rate. It is expected that a common interrupt service routine services the transmit and receive registers. After reset, the B- and D-channel shift registers and shadow registers are initialized to all ones. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 13-4 Freescale Semiconductor...
Page 301: Gci/Idl B- And D-Channel Bit Alignment
(LSB) position. See Section 13.5.1, “B1 Data Receive Registers (P0B1RR–P3B1RR),” or Section 13.5.5, “B2 Data Transmit Registers (P0B2TR–P3B2TR),” for more information about some of these registers. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 13-5...
Page 302: B-Channel Hdlc Encoded Data
The Soft HDLC expects the first bit received to be aligned in the lsb position of a byte, with the last bit received aligned in the msb position. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 13-6 Freescale Semiconductor...
Page 303: D-Channel Unencoded Data
, the next two D-channel bits from the second frame in B and B , and so on, until the last two D-channel bits in the fourth frame are aligned in B and B ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 13-7...
Page 304: Gci/Idl D-Channel Contention
Similarly, in local-loopback mode, the information transmitted on the Dout pin is echoed back on Din during the same time slot. The PLIC transmitter and receiver should both be disabled when switching between modes. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 13-8 Freescale Semiconductor...
Page 305: Automatic Echo Mode
Each of the B- and D-channel transmit and receive registers should be written and read prior to the next 2-KHz interrupt for underrun or overrun conditions to be prevented. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 306: Gci Aperiodic Status Interrupt
C/I channel transmit: ASR defines which port or ports have generated a C/I channel transmit interrupt. The interrupt service routine must then read the appropriate GCIT register or registers to clear the C/I channel transmit interrupt. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 13-10 Freescale Semiconductor...
Page 307: Interrupt Control
(Gen_FSC) must be set. (A Gen_FSC of 8 KHz is assumed). This division ratio is selected by means of FDIV[2-0]. Finally, the clock generation block should be taken out of bypass by setting PCSR[NBP]. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 13-11...
Page 308: Plic Internal Timing Signal Routing
Port 3 GCI/IDL DFSC3 Figure 13-11. PLIC Internal Timing Signal Routing GDCL DCL0/URT1_CLK Gen_FSC Multiply Divider PA8/FSC0/FSR0 Block Block O192K CKI[1:0] CMULT[2:0] FDIV[2:0] Figure 13-12. PLIC Clock Generator ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 13-12 Freescale Semiconductor...
Page 309: Super Frame Sync Generation
Port1 B1 Data Transmit (P1B1TR) 0x0330 Port2 B1 Data Transmit (P2B1TR) 0x0334 Port3 B1 Data Transmit (P3B1TR) 0x0338 Port0 B2 Data Transmit (P0B2TR) 0x033C Port1 B2 Data Transmit (P1B2TR) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 13-13...
Page 310 0x0390 Reserved D-Channel Request (PDRQR) 0x0394 Port0 Sync Delay (P0SDR) Port1 Sync Delay (P1SDR) 0x0398 Port2 Sync Delay (P2SDR) Port3 Sync Delay (P3SDR) 0x039C Reserved Clock Select (PCSR) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 13-14 Freescale Semiconductor...
Page 311: Plic Registers
Field Frame 2 Frame 3 Reset 1111_1111 1111_1111 Read Only Addr MBAR + 0x300 (P0B1RR); 0x304 (P1B1RR); 0x308 (P2B1RR); 0x30C (P3B1RR) Figure 13-13. B1 Receive Data Registers P0B1RR–P3B1RR ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 13-15...
Page 312: B2 Data Receive Registers (P0B2Rr-P3B2Rr)
Read Only Field P2DRR P3DRR Reset 1111_1111 1111_1111 Read Only Addr MBAR + 0x320 (P0DRR); 0x321 (P1DRR); 0x322 (P2DRR); 0x323 (P3DRR) Figure 13-15. D Receive Data Registers P0DRR–P3DRR ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 13-16 Freescale Semiconductor...
Page 313: B1 Data Transmit Registers (P0B1Tr-P3B1Tr)
1111_1111 1111_1111 Read/Write Field Frame2 Frame3 Reset 1111_1111 1111_1111 Read/Write Addr MBAR + 0x338 (P0B2TR); 0x33C (P1B2TR); 0x340 (P2B2TR); 0x344 (P3B2TR) Figure 13-17. B2 Transmit Data Registers P0B2TR–P3B2TR ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 13-17...
Page 314: D Data Transmit Registers (P0Dtr-P3Dtr)
PnCR are registers containing configuration information for each of the four ports on the MCF5272. All bits in these registers are read/write and are cleared on hardware or software reset. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 13-18...
Page 315: P0Cr–P3Cr Field Descriptions
All 1s High Impedance Operational (data on Din visible) Open drain 1 Enables the B2 data channel for the respective port. ENB1 Enable B1 data channel. See ENB2. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 13-19...
Page 316: Loopback Control Register (Plcr)
MBAR + 0x0358 (P0ICR); 0x035A (P1ICR); 0x035C (P2ICR); 0x035E (P3ICR) Figure 13-21. Interrupt Configuration Registers (P0ICR–P3ICR) The PnICR registers contain interrupt configuration bits for each of the four ports on the MCF5272. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 13-20 Freescale Semiconductor...
Page 317: P0Icr–P3Icr Field Descriptions
1 Interrupt enabled. Interrupt occurs when the corresponding PnPSR[B2RDF] or PnPSR[B2ROE] is set. B1RIE B1 receive interrupt enable. 0 Interrupt masked 1 Interrupt enabled.Interrupt occurs when the corresponding PnPSR[B1RDF] or PnPSR[B1ROE] is set. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 13-21...
Page 318: Periodic Status Registers (P0Psr-P3Psr)
B1 data transmit data empty. This bit is set when the data in the PnB1TR transmit data register for the respective port has been transferred to the transmit shadow register. This bit is cleared when the CPU writes data to PnB1TR. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 13-22 Freescale Semiconductor...
Page 319: Aperiodic Status Register (Pasr)
An interrupt is queued when this bit is set if the GMT interrupt enable bit has been set in the corresponding PnICR register. The GMT bit and associated interrupt are automatically cleared when the PGMTS register has been read by the CPU. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 13-23...
Page 320: Gci Monitor Channel Receive Registers (P0Gmr-P3Gmr)
Automatically cleared by the CPU when the PnGMR register has been read. Clearing this bit by reading this register also clears the aperiodic GMR interrupt. 7–0 Monitor channel data byte. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 13-24 Freescale Semiconductor...
Page 321: Gci Monitor Channel Transmit Registers (P0Gmt-P3Gmt)
Automatically cleared by the GCI controller when it generates a transmit acknowledge (ACK bit in PGMTS register) or when the L bit is reset. 7–0 Monitor channel data byte. Written by the CPU when a byte is ready for transmission. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 13-25...
Page 322: Gci Monitor Channel Transmit Abort Register
E bit. Automatically cleared by the monitor channel controller on receiving an abort, that is, when PGMTS[AB] is set. Abort request, port 2. See AR3. Abort request, port 1. See AR3. Abort request, port 0. See AR3. 3–0 — Reserved, should be cleared. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 13-26 Freescale Semiconductor...
Page 323: Gci Monitor Channel Transmit Status Register
PGMTA register, the ACK bit in the GMTS register, and the L and R bits in the PnGMT register. Abort, port 2. See AB3. Abort, port 1. See AB3. Abort, port 0. See AB3. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 13-27...
Page 324: Gci C/I Channel Receive Registers (P0Gcir-P3Gcir)
CPU, via this register. A maskable interrupt is generated when data is written into any of the four available positions. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 13-28 Freescale Semiconductor...
Page 325: Gci C/I Channel Transmit Registers (P0Gcit-P3Gcit)
A maskable interrupt is generated when this data has been successfully transmitted ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 326: Gci C/I Channel Transmit Status Register
C/I words. The ACK bit is automatically cleared by the CPU when the PGCITSR register has been read. ACK2 Acknowledge, port 2. See ACK3. ACK1 Acknowledge, port 1. See ACK3. ACK0 Acknowledge, port 0. See ACK3. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 13-30 Freescale Semiconductor...
Page 327: D-Channel Status Register (Pdcsr)
1 Indicates that a value other than 0xFF (all ones) exists the D-channel receive register. D-channel change, port 2. See DC3. D-channel change, port 1. See DC3. D-channel change, port 0. See DC3. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 13-31...
Page 328: D-Channel Request Register (Pdrqr)
The value written to these bits is driven onto the DREQ pins associated with port 0 and port 1. When set, a logic high, 1, is driven on to the corresponding pin. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 13-32...
Page 329: Sync Delay Registers (P0Sdr-P3Sdr)
The 8-bit frame-sync-width should not be confused with long frame sync mode. The PLIC only supports short frame sync in IDL8 and IDL10 bit modes for interfacing to external transceivers. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 13-33...
Page 330: Clock Select Register (Pcsr)
Clock multiplication ratio. Sets the ratio of the reference clock frequency to the GDCL frequency. 000 x 2 001 x 4 010 x 8 011 x 16 100 x 32 101 x 64 110 x 128 111 x 256 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 13-34 Freescale Semiconductor...
Page 331: Application Examples
Port 1 is active as slave using IDL10 mode • 2-KHz frame interrupt derived from port 1 • msb first on B1 and B2 • B1 and B2 disabled. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 13-35...
Page 332: Port 1 Configuration Register (P1Cr)
;port 1 config ON, IDL10, SLAVE, port1 FSM ;msb first on B1 and B2, B1 and B2 disabled move.w d0,P1CR(A5) ;write to P1CR register The above code segment is an example only. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 13-36 Freescale Semiconductor...
Page 333: Interrupt Configuration Example
P1CR example: move.w #0x8024,d0 ; port 1 IE and D-channel interrupts enabled move.w d0,P1ICR(A5) ; write value to PnICR ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 13-37...
Page 334: Example 1: Isdn Soho Pbx With Ports 0, 1, 2, And 3
IDL interface. CODECs 1 and 2 are connected to frame sync 1, FSC1. CODECs 3 and 4 are connected to DFSC2 which is the output of programmable ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 13-38...
Page 335: Standard Idl2 10-Bit Mode
Only the port 0 D-channel is used in this example; DREQ0 and DGNT0 are connected to the S/T transceiver. The GCI mode of operation is analogous. In GCI mode, port 0 can be configured to support the SCIT channel. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 13-39...
Page 336: Example 2: Isdn Soho Pbx With Ports 1, 2, And 3
MC14LC5480 data sheet for further information). Figure 13-40 shows the IDL bus timing relationship of the CODECs and U transceiver when in standard IDL2 10-bit mode with a common frame sync. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 13-40 Freescale Semiconductor...
Page 337: Standard Idl2 10-Bit Mode
Dout0 FSC0 IDL SYNC DCL0 IDL CLK MC145574 #2 DGNT1 DGrant DREQ1 DRequest Interface 1 Din1 Dout1 FSC1 IDL SYNC DCL1 IDL CLK Figure 13-41. Two-Line Remote Access ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 13-41...
Page 338: Standard Idl2 8-Bit Mode
IDL bus timing relationship of the S/T transceivers when in standard IDL2 8-bit mode with a common frame sync. FSC0 FSC1 MC145574 #1 Din0/ Dout0 Din1/ Dout1 MC145574 #2 Figure 13-42. Standard IDL2 8-Bit Mode ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 13-42 Freescale Semiconductor...
Page 339: Queued Serial Peripheral Interface (Qspi) Module
The QSPI module communicates with the integrated ColdFire CPU using internal memory mapped registers located starting at MBAR + 0xA0. See also Section 14.5, “Programming Model.” A block diagram of the QSPI module is shown in Figure 14-1. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 14-1...
Page 340: Qspi Block Diagram
Regs Rx/Tx Data Reg. Logic Array Control QSPI_Dout Regs Command QSPI_CS[3:0] Delay Counter Internal Bus Baud Rate CLKIN Divide by 2 QSPI_CLK Generator Figure 14-1. QSPI Block Diagram ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 14-2 Freescale Semiconductor...
Page 341: Interface And Pins
RAM, and then enabling the QSPI data transfer. The QSPI executes the queued commands and sets the completion flag in the QSPI interrupt register (QIR[SPIF]) to signal their completion. Optionally, QIR[SPIFE] can be enabled to generate an interrupt. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 14-3...
Page 342: Qspi Ram
The command and data RAM in the QSPI is indirectly accessible with QDR and QAR as 48 separate locations that comprise 16 words of transmit data, 16 words of receive data and 16 bytes of commands. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 14-4...
Page 343: Receive Ram
‘word’ regardless of length. QWR[CPTQP] shows which queue entries have been executed. The user can query this field to determine which locations in receive RAM contain valid data. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 14-5...
Page 344: Transmit Ram
A baud rate value of zero turns off the QSPI_CLK. The desired QSPI_CLK baud rate is related to CLKIN and QMR[BAUD] by the following expression: QMR[BAUD] = CLKIN / [2 × (desired QSPI_CLK baud rate)] ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 14-6 Freescale Semiconductor...
Page 345: Transfer Delays
QSPI module requires time to load a transmit RAM entry for transfer. If CLKIN is operating at a slower rate, the delay between transfers must be increased proportionately. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 346: Transfer Length
QWR[WREN] is cleared. After QWR[HALT] is set, the QSPI finishes the current transfer, then stops executing commands. After the QSPI stops, QDLYR[SPE] can be cleared. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 14-8...
Page 347: Programming Model
Data output high impedance enable. Selects QSPI_Dout mode of operation. 0 Default value after reset. QSPI_Dout is actively driven between transfers. 1 QSPI_Dout is high impedance between transfers. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 14-9...
Page 348: Qspi Clocking And Data Transfer Example
QMR[CPOL] = 0 Chip selects are active low QMR[CPHA] = 1 A = QDLYR[QCD] QCR[CONT] = 0 B = QDLYR[DTL] Figure 14-4. QSPI Clocking and Data Transfer Example ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 14-10 Freescale Semiconductor...
Page 349: Qspi Delay Register (Qdlyr)
QSPI_CLK transition. 7–0 Delay after transfer.When the DT bit in the command RAM sets this field determines the length of delay after the serial transfer. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 14-11...
Page 350: Qspi Wrap Register (Qwr)
This field is read only. 3–0 NEWQP Start of queue pointer. This 4-bit field points to the first entry in the RAM to be executed on initiating a transfer. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 14-12 Freescale Semiconductor...
Page 351: Qspi Interrupt Register (Qir)
16 words of transmit data, 16 words of receive data and 16 bytes of commands. A write to QDR causes data to be written to the RAM entry specified by QAR[ADDR]. This also causes the value in QAR to increment. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 14-13...
Page 352: Qspi Address Register (Qar)
QSPI RAM through this register. A read or write to QDR causes the value in QAR to increment. Field DATA Reset 0000_0000_0000_0000 Address MBAR + 0x00B4 Figure 14-10. QSPI Data Register ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 14-14 Freescale Semiconductor...
Page 353: Command Ram Registers (Qcr0-Qcr15)
In order to keep the chip setects asserted for all transfers, the QWR[CSIV] bit must be set to control the level that the chip selects return to after the first transfer. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 354: Programming Example
12. Write QAR with 0x0010 to select the first receive RAM entry. 13. Read QDR to get the received data for each transfer. 14. Repeat steps 5 through 13 to do another transfer. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 14-16 Freescale Semiconductor...
Page 355: Timer Module
The free run/restart bit, TMRn[FRR], selects each mode. Upon reaching the reference value, the TER0 or TER1 bit is set, and an interrupt is issued if the output reference interrupt enable bit, TMR[ORI], is set. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 15-1...
Page 356: Timer Block Diagram
(of TIN0, TIN1, URT0_RxD, or URT1_RxD). The type of transition triggering the capture is selected by the capture edge bits, TMR[CE].A capture or reference event sets the TER bit and generates a maskable interrupt. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 15-2 Freescale Semiconductor...
Page 357: General-Purpose Timer Registers
11 Corresponding TIN pin, TIN0 or TIN1 (falling edge), unused in TMR2 and TMR3 The minimum high and low periods for TIN as the clock source is 1 system clock, which gives a maximum TIN frequency of clock/2. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 15-3...
Page 358: Timer Reference Registers (Trr0-Trr3)
A write cycle to a TCN register causes it to be cleared. Field COUNT (16-bit timer counter value) Reset 0000_0000_0000_0000 Read/Write Addr MBAR + 0x20C (TCN0); 0x22C (TCN1); 0x24C (TCN2); 0x26C (TCN3) Figure 15-5. Timer Counter (TCN0–TCN3) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 15-4 Freescale Semiconductor...
Page 359: Timer Event Registers (Ter0-Ter3)
1 The counter value is latched in the TCAP. TMR[CE] is used to enable capture and the interrupt request caused by this event. Write a 1 to this bit to clear the event condition. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 360 Timer Module ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 15-6 Freescale Semiconductor...
Page 361: Uart Modules
The receiver may be polled- or interrupt-driven. See Section 16.5.2.2, “Receiver.” ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 16-1...
Page 362: Serial Module Overview
“Programming,” describe basic UART module programming. The operation of the UART module is controlled by writing control bytes into the appropriate registers. Table 16-1 is a memory map for UART module registers. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 16-2 Freescale Semiconductor...
Page 363: Uart Module Programming Model
(Write) Do not access. — 0x124 0x164 (Read) UART autobaud — register LSB—(UABLn) [p. 16-17] (Write) Do not access — 0x128 0x168 UART Transmitter FIFO — registers—(UTFn) [p. 16-4] ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 16-3...
Page 364: Uart Mode Registers 1 (Umr1N)
MBAR + 0x100 (UART0), 0x140 (UART1). After UMR1n is read or written, the pointer points to UMR2n. Figure 16-2. UART Mode Registers 1 (UMR1n) Table 16-2 describes UMR1n fields. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 16-4 Freescale Semiconductor...
Page 365: Umr1N Field Descriptions
Bits per character. Select the number of data bits per character to be sent. The values shown do not include start, parity, or stop bits. 00 5 bits 01 6 bits 10 7 bits 11 8 bits ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 16-5...
Page 366: Uart Mode Register 2 (Umr2N)
0.625 0101 1.375 0.875 1001 1.625 1101 1.875 0010 1.188 0.688 0110 1.438 0.938 1010 1.688 1110 1.938 0011 1.250 0.750 0111 1.500 1.000 1011 1.750 1111 2.000 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 16-6 Freescale Semiconductor...
Page 367: Uart Status Registers (Usrn)
1 The transmitter holding register is empty and ready for a character. TxRDY is set when a character is sent to the transmitter shift register and when the transmitter is first enabled. If the transmitter is disabled, characters loaded into the transmitter holding register are not sent. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 16-7...
Page 368: Uart Clock-Select Registers (Ucsrn)
1110 URT_CLK divided by 16 1111 URT_CLK 3–0 Transmitter clock select. Selects the clock source for the transmitter channel. 1101 Prescaled CLKIN 1110 URT_CLK divided by 16 1111 URT_CLK ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 16-8 Freescale Semiconductor...
Page 369: Uart Command Registers (Ucrn)
This command ignores the state of CTS. stop break Causes TxD to go high (mark) within two bit times. Any characters in the transmitter buffer are sent. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 16-9...
Page 370: Uart Receiver Buffers (Urbn)
(see Figure 16-24). RB contains the character in the receiver. Field Reset 0000_0000 Read only Address MBAR + 0x10C,0x14C Figure 16-7. UART Receiver Buffer (URBn) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 16-10 Freescale Semiconductor...
Page 371: Uart Transmitter Buffers (Utbn)
COS is set, which initiates an interrupt if UACRn[IEC] is enabled. 0 The current state of the CTS input is asserted. 1 The current state of the CTS input is negated. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 16-11...
Page 372: Uart Auxiliary Control Registers (Uacrn)
If a UIMRn bit is cleared, the state of the corresponding UISRn bit has no effect on the output. NOTE True status is provided in the UISRn regardless of UIMRn settings. UISRn is cleared when the UART module is reset. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 16-12 Freescale Semiconductor...
Page 373: Uart Interrupt Status/Mask Registers (Uisrn/Uimrn)
0 The transmitter holding register was loaded by the CPU or the transmitter is disabled. Characters loaded into the transmitter holding register when TxRDY = 0 are not sent. 1 The transmitter holding register is empty and ready to be loaded with a character. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 16-13...
Page 374: Uart Divider Upper/Lower Registers (Udun/Udln)
Figure 16-14. UART Autobaud Upper Registers (UABUn) Field Autobaud LSB Reset 0000_0000 Read only Address MBAR + 0x124 (UABL0), 0x164 (UABL1) Figure 16-15. UART Autobaud Lower Registers (UABLn) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 16-14 Freescale Semiconductor...
Page 375: Uart Transmitter Fifo Registers (Utfn)
1 Transmitter FIFO is full. Characters loaded into the transmitter FIFO when it is full are not transmitted. 4–0 Transmitter buffer data level. Indicates the number of bytes, between 0 and 24, stored in the transmitter FIFO. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 16-15...
Page 376: Uart Receiver Fifo Registers (Urfn)
1 Receiver FIFO is full. Characters loaded from the receiver when the FIFO is full are lost. This bit is identical to USRn[FFULL]. 4–0 Receiver buffer data level. Indicates the number of bytes, between 0 and 24, stored in the receiver FIFO. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 16-16 Freescale Semiconductor...
Page 377: Uart Fractional Precision Divider Control Registers (Ufpdn)
UIPCRn[RTS]. 0 The current state of the CTS input is logic 0. 1 The current state of the CTS input is logic 1. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 16-17...
Page 378: Uart Output Port Command Registers (Uop1N/Uop0N)
Logic Receive Buffer Address Bus Interface to CPU Data URT_TxD 24-Character Transmit Buffer To Interrupt Controller (SIM) Figure 16-21. UART Block Diagram Showing External and Internal Interface Signals ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 16-18 Freescale Semiconductor...
Page 379: Operation
16+4-bit divider (UDU, UDL, UFPD) dedicated to the UART. The clock generator cannot produce standard baud rates if CLKIN is used, so the 16-bit divider should be used. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 380: Programmable Divider
When CLKIN is the UART clocking source, it goes through a divide-by-32 prescaler and then passes through the 16-bit divider of the concatenated UDUn and UDLn registers. The UFPD register can be used ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 16-20...
Page 381: External Clock
The receiver and transmitter clock sources must be set to TIMER (UCSR = 0xDD). • Autobaud must be enabled (UCR[ENAB] = 1). • The receiver must be enabled (UCR[RC] = 01). ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 16-21...
Page 382: Transmitter And Receiver Operating Modes
TxEMP is cleared when the CPU loads a new character into the UART transmitter buffer (UTBn). If the transmitter receives a disable command, it continues until any character in the transmitter shift register is completely sent. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 16-22 Freescale Semiconductor...
Page 383: Transmitter Timing
Start C4 Stop break break transmitted Manually asserted Manually command asserted Cn = transmit characters W = write UMR2n[TxCTS] = 1 UMR2n[TxRTS] = 1 Figure 16-25. Transmitter Timing ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 16-23...
Page 384: Receiver
(RHR) and USRn[RB,RxRDY] are set. RxD must return to a high condition for at least one-half bit time before a search for the next start bit begins. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 16-24...
Page 385: Transmitter Fifo
However, errors are not detected until the check is performed at the end of an entire message—the faulting character in the block is not identified. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 386: Looping Modes
The UART’s transmitter and receiver should be disabled when switching between modes, as the selected mode is activated immediately upon mode selection, regardless of whether a character is being received or transmitted. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 16-26 Freescale Semiconductor...
Page 387: Automatic Echo Mode
TxD output. The local CPU-to-transmitter link is disabled. This mode is useful in testing receiver and transmitter operation of a remote channel. For this mode, the transmitter uses the receiver clock. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 16-27...
Page 388: Multidrop Mode
Messages in this mode may still contain error detection and correction information. If 8-bit characters are not required, software can be used to calculate parity and append it to the 5-, 6-, or 7-bit character. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 16-28 Freescale Semiconductor...
Page 389: Bus Operation
16.5.5.3 Interrupt Acknowledge Cycles An internal interrupt request signal notifies the interrupt controller of any unmasked interrupt conditions. The interrupt priority level is programmed in ICR2. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 16-29...
Page 390: Programming
UART module registers can be accessed by word or byte operations, but only data byte D[7:0] is valid. Figure 16-31 shows the UART module initialization sequence. Figure 16-31. UART Mode Programming Flowchart (Sheet 1 of 5) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 16-30 Freescale Semiconductor...
Page 391 UART Modules Figure 16-31. UART Mode Programming Flowchart (Sheet 2 of 5) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 16-31...
Page 392 UART Modules Figure 16-31. UART Mode Programming Flowchart (Sheet 3 of 5) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 16-32 Freescale Semiconductor...
Page 393 UART Modules Figure 16-31. UART Mode Programming Flowchart (Sheet 4 of 5) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 16-33...
Page 394 UART Modules Figure 16-31. UART Mode Programming Flowchart (Sheet 5 of 5) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 16-34 Freescale Semiconductor...
Page 395: General Purpose I/O Module
WSEL during device reset. An additional port, port D, has only a control register which is used to configure the pins that are not multiplexed with any GPIO signals. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 17-1...
Page 396: Port Control Registers
0x008E Reserved Port B Data Register (PBDAT) 0x0094 Port C Data Direction Register (PCDDR) Reserved 0x0096 Reserved Port C Data Register (PCDAT) 0x0098 Port D Control Register (PDCNT) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 17-2 Freescale Semiconductor...
Page 397: Port A Control Register (Pacnt)
01 Reserved 10 QSPI_CS1 11 Reserved 21–20 PACNT10 Configure pin K5 00 PA10 01 DREQ0 1x Reserved 19–18 PACNT9 Configure pin J3 00 PA9 01 DGNT0 1x Reserved ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 17-3...
Page 398 INT6 is always available on pin M3. It can be enabled by programming the appropriate bits in interrupt control register 4, see Section 7.2.2.4, “Interrupt Control Register 4 (ICR4), and the programmable interrupt transition register described in Section 7.2.4, “Programmable Interrupt Transition Register (PITR). ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 17-4 Freescale Semiconductor...
Page 399: Port B Control Register (Pbcnt)
Reset 0000_0000_0000_0000 Read/Write Addr MBAR + 0x0088 Figure 17-2. Port B Control Register (PBCNT) Table 17-5 describes PBCNT fields. Table 17-6 provides the same information organized by function. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 17-5...
Page 400: Pbcnt Field Descriptions
00 PB7 01 TOUT0 1x Reserved 13–12 PBCNT6 Configure pin G4 00 PB6 01 Reserved 1x Reserved 11–10 PBCNT5 Configure pin F3 00 PB5 01 TA 1x Reserved ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 17-6 Freescale Semiconductor...
Page 401: Port B Control Register Function Bits
— E_TxD2 — — PB10 E_TxD1 — — PB11 E_RxD3 — — PB12 E_RxD2 — — PB13 E_RxD1 — — PB14 E_RxER — — PB15 E_MDC — — ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 17-7...
Page 402: Port C Control Register
11–10 PDCNT5 Configure pin P2. 00 High impedance 01 Reserved 10 DIN3 11 INT4 9–8 PDCNT4 Configure pin K1. 00 High impedance 01 DOUT0 10 URT1_TxD 11 Reserved ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 17-8 Freescale Semiconductor...
Page 403: Port D Control Register Function Bits
Pin is high Z PWM_OUT1 TOUT1 — Pin is high Z PWM_OUT2 TIN0 — 8-15 — — — — URT1_RxD is always internally connected to timer 3 (TIN3). ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 17-9...
Page 404: Data Direction Registers
The PBDDR determines the signal direction of each parallel port pin programmed as a GPIO port in the PBCNT. Field PBDDR Reset 0000_0000_0000_0000 Read/Write Addr MBAR + 0x008C Figure 17-5. Port B Data Direction Register (PBDDR) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 17-10 Freescale Semiconductor...
Page 405: Port C Data Direction Register (Pcddr)
Note that PxDAT has no effect on pins which have not been configured for GPIO. Field PxDAT Reset Undefined Read/Write Addr MBAR + 0x0086 (PADAT); 0x008E (PBDAT); 0x0096 (PCDAT) Figure 17-7. Port x Data Register (PADAT, PBDAT, and PCDAT) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 17-11...
Page 406 General Purpose I/O Module ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 17-12 Freescale Semiconductor...
Page 407: Pulse-Width Modulation (Pwm) Module
With a suitable low-pass filter, the PWM can be used as a digital-to-analog converter. SYS CLOCK PWCR[CKSL] PRESCALER COUNTER FRC1 PWM_OUT0 COMPARATOR GENERATOR PWM_OUT1 PWM_OUT2 WIDTH BUFFER Figure 18-1. PWM Block Diagram (3 Identical Modules) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 18-1...
Page 408: Pwm Operation
0x00C8 PWM Control Register 2 Reserved (PWCR2) 0x00D0 PWM Pulse-Width Register 0 Reserved (PWWD0) 0x00D4 PWM Pulse-Width Register 1 Reserved (PWWD1) 0x00D8 PWM Pulse-Width Register 2 Reserved (PWWD2) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 18-2 Freescale Semiconductor...
Page 409: Pwm Control Register (Pwcrn)
Prescale clock. These bits select the clock frequency divider, that is, the output of the divider chain, as shown below. CKSL[3:0] Divisor 0000 1 0001 2 0010 4 ..111132768 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 18-3...
Page 410: Pwm Width Register (Pwwdn)
PWCRn[CKSL] = 0000: T = 1 x CPU clock period PWCRn[CKSL] = 1111: T = 32768 x CPU clock period Figure 18-4. PWM Waveform Examples (PWCRn[EN] = 1) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 18-4 Freescale Semiconductor...
Page 411: Signal Descriptions
MCF5272 block diagram and how the modules and signals interact. Refer also to Table 19-1 Table 19-2 for a list of the signals sorted by function and pin number, respectively. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 19-1...
Page 412: Mcf5272 Block Diagram With Signal Interfaces
QSPI_CS0/BUSW0 PWM_OUT0 PA11/QSPI_CS1 PWM_OUT1/TOUT1 PA7/QSPI_CS3/DOUT3 PWM_OUT2/TIN1 URT1_CTS/QSPI_CS2 TIMER/PIT WATCHDOG NOTE: GPIO pins shown above are multiplexed with most other signals. Figure 19-1. MCF5272 Block Diagram with Signal Interfaces ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 19-2 Freescale Semiconductor...
Page 413: Signal List
A1/SDRAM-32bit A0 — — — — — — — — — SDA2 SDA1 — A3/SDRAM-16bit A2/SDRAM-32bit A1 SDA3 SDA2 — A4/SDRAM-16bit A3/SDRAM-32bit A2 SDA4 SDA3 — A5/SDRAM-16bit A4/SDRAM-32bit A3 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 19-3...
Page 414 WSEL pin — — D16/D0 WSEL pin — — D17/D1 WSEL pin — — D18/D2 WSEL pin — — D19/D3 WSEL pin — — D2/port C bit 2 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 19-4 Freescale Semiconductor...
Page 415 PLIC ports 1, 2, 3 data output DRESETEN — — — DRAM controller reset enable E_COL — — — Collision E_CRS — — — Carrier sense (100 base-T Ethernet only) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 19-5...
Page 416 PWM output compare 2 OUT2 /Timer 1 input INT1/ — — — Interrupt input 1/USB USB_WOR wake-on-ring INT2 — — — Interrupt input 1 INT3 — — — Interrupt input 3 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 19-6 Freescale Semiconductor...
Page 417 Port A bit 9//IDL DGNT0 Port B Cntl URT0_TxD — — Port B bit 0/UART0 Tx data Port B Cntl URT0_RxD — — Port B bit 1/UART0 Rx data ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 19-7...
Page 418 Port B bit 9/Tx data bit 2 (100 Base-T Ethernet only) PST0 — — — Internal processor status PST1 — — — Internal processor status PST2 — — — Internal processor status ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 19-8 Freescale Semiconductor...
Page 419 BDM debug transfer error acknowledge TEST — — — Device test mode enable TIN0 — — — Timer 0 input MTMOD BKPT — — JTAG test mode/BDM select breakpoint input ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 19-9...
Page 420 MTMOD means that pin function is determined by state of the MTMOD signal. Requires external protection circuitry to meet USB 1.1 electrical requirements under all conditions (see 12.5.3, “Recommended USB Protection Circuit”). ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 19-10 Freescale Semiconductor...
Page 421: Signal Name And Description By Pin Number
— — D23/D7 D23/D7 SDWE — — — SDWE SDRAM write enable SDCS/ — — — SDCS / CS7 SDRAM chip select/CS7 SDA11 — — A12/SDA11 A12/SDRAM-16bit A11 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 19-11...
Page 422 Internal processor status 3 TRST DSCLK — — TRST/DSCLK JTAG reset/BDM clock — — TDO/DSO JTAG test data out /BDM data out — — — — — — ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 19-12 Freescale Semiconductor...
Page 423 — — — USB_D- USB line driver low, analog — — PB5/TA Port B bit 5/Transfer acknowledge RSTO — — — RSTO Reset output strobe +3.3V — — ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 19-13...
Page 424 URT0_ — — PB3/URT0_RTS Port B bit 3/UART0 RTS URT0_TxD — — PB0/URT0_TxD Port B bit 0/UART0 Tx data +3.3V — — Ground — — Ground — — ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 19-14 Freescale Semiconductor...
Page 425 — — PA10/DREQ0 Port A bit 10/IDL DREQ0 High Z PWM_ TIN1 — PWM_OUT2/TIN1 PWM output compare 2 OUT2 /Timer 1 input +3.3V — — +3.3V — — ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 19-15...
Page 426 DREQ1 — — PA14/DREQ1 Port A bit 14/PLIC port 1 IDL D-channel request PA15_INT6 DGNT1_INT6 — — PA15_INT6/DGNT1_INT6 Port A bit 15/PLIC port 1 D-channel grant/Interrupt 6 input ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 19-16 Freescale Semiconductor...
Page 427 PB12 E_RxD2 — — PB12/E_RxD2 Port B bit 12/Rx data bit 2 (100 Base-T Ethernet only) E_MDIO — — — E_MDIO Management channel serial data (100 base-T only) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 19-17...
Page 428 Clock (100 Base-T only) — — — Chip select 2 — — — CS6/AEN Chip select 6 OE/RD — — — OE/RD Output enable/Read — — — Read/Write ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 19-18 Freescale Semiconductor...
Page 429: Address Bus (A[22:0]/Sda[13:0])
CS7/SDCS can be configured to access RAM or ROM or one physical bank of SDRAM. Only CS7 can be used for SDRAM chip select. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 19-19...
Page 430: Bus Control Signals
D[15:8] FLASH/SRAM D[7:0] FLASH/SRAM Word D[31:16] FLASH/SRAM D[15:0] FLASH/SRAM Longword D[31:0] SDRAM Byte D[7:0] SDRAM D[15:8] SDRAM D[23:16] SDRAM D[31:24] SDRAM Word D[15:0] SDRAM D[31:16] SDRAM Longword D[31:0] ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 19-20 Freescale Semiconductor...
Page 431: Read/Write (R/W)
R/W acts as a write strobe to external SRAM when the decoded chip select is configured for either of the two SRAM/ROM modes. It is asserted during on-chip peripherals accesses and negated during on-chip SRAM accesses. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 19-21...
Page 432: Transfer Acknowledge (Ta/Pb5)
The SDRAM clock output (SDCLK) is the same frequency as the CPU clock. 19.6.10 SDRAM Write Enable (SDWE) This output is the SDRAM write enable. 19.6.11 SDRAM Clock Enable (SDCLKE) This output is the SDRAM clock enable. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 19-22 Freescale Semiconductor...
Page 433: Sdram Bank Selects (Sdba[1:0])
(high to low) or positive edge (low to high) transitions. In addition to the triggering edge being programmable, the priority can also be programmed. Each interrupt input has a separate programmable interrupt level. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 19-23...
Page 434: General-Purpose I/O (Gpio) Ports
Port B mode: This pin can also be configured as the PB0 I/O. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 19-24 Freescale Semiconductor...
Page 435: Clock (Urt0_Clk/Pb4)
19.11.3 USB Receive Data Negative (USB_RN/PA2) USB mode: USB_RN is the inverted receive data input. Port A mode: This pin can also be configured as the PA2 I/O. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 19-25...
Page 436: Usb Transmit Data Negative (Usb_Tn/Pa3)
The interrupt output of an ISDN transceiver, such as the MC145574, can be connected to INT1/USB_WOR. Before putting the device into sleep mode, the USB module’s wake on ring function ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 19-26...
Page 437: 19.12 Timer Module Signals
These signals are multiplexed with the parallel port B PB15–PB8 signals. 19.13.1 Transmit Clock (E_TxCLK) This is an input clock which provides a timing reference for E_TxEN, E_TxD[3:0] and E_TxER. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 19-27...
Page 438: Collision (E_Col)
Ethernet mode: These pins contain the Ethernet input data transferred from the PHY to the media-access controller when E_RxDV is asserted in MII mode operation. Port B mode: These pins can also be configured as I/O pins PB[13:11]. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 19-28 Freescale Semiconductor...
Page 439: Receive Error (E_Rxer/Pb14)
This section describes signals used by the queued serial peripheral interface (QSPI) module. Four QSPI chip selects, QSPI_CS[3:0], are multiplexed with the physical layer interface pins and GPIO port A. QSPI_CS0 is always available. QSPI_CS3 is multiplexed with DOUT3 and PA7. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 19-29...
Page 440: Qspi Synchronous Serial Data Output (Qspi_Dout/Wsel)
Section 19.16.1.5, “UART1 CTS (URT1_CTS/QSPI_CS2).” 19.15.7 Synchronous Peripheral Chip Select 3 (PA7/DOUT3/QSPI_CS3) Section 19.16.3.3, “QSPI_CS3, Port 3 GCI/IDL Data Out 3, PA7 (PA7/DOUT3/QSPI_CS3).” See description for GPIO ports. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 19-30 Freescale Semiconductor...
Page 441: Physical Layer Interface Controller Tdm Ports And Uart 1
When the UART1 clock is stopped for power-down mode, any transition on this pin restarts it. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 442: Uart1 Cts (Urt1_Cts/Qspi_Cs2)
IDL mode: DCL1 is the data clock used to clock data in and out of the DIN1 and DOUT1 pins for IDL port 1. Data is clocked in to DIN1 on the falling edge of DCL1. Data is clocked out of DOUT1 on the rising edge of DCL1. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 19-32 Freescale Semiconductor...
Page 443: Gci/Idl Data Out (Dout1)
19.16.2.6 D-Channel Grant (DGNT1_INT6/PA15_INT6) This pin can be independently configured as the input, DGNT1, used by a Layer one ISDN S/T transceiver to indicate that D-channel access has been granted. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 19-33...
Page 444: Gci/Idl Delayed Frame Sync 2 (Dfsc2/Pa12)
DOUT3 on the rising edge of DCL1. After device reset port 3 is connected to DOUT1 by setting a bit in the PLIC module configuration register, this pin can be configured as a dedicated output for IDL/GCI port 3. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 19-34 Freescale Semiconductor...
Page 445: Int4 And Port 3 Gci/Idl Data In (Int4/Din3)
1149.1 standard. Connecting TMS to VDD disables the test controller, making all JTAG circuits transparent to the system. BDM mode: The hardware breakpoint input, BKPT, requires a 10-K¾ pullup resistor. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 19-35...
Page 446: Test And Debug Data Out (Tdo/Dso)
19.17.8 Processor Status Outputs (PST[3:0]) PST[3:0] outputs indicate core status, as shown in Table 19-7. Debug mode timing is synchronous with the processor clock; status is unrelated to the current bus transfer. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 19-36 Freescale Semiconductor...
Page 447: Debug Data (Ddata[3:0])
QSPI_CS0/BUSW0. BYPASS is a Freescale test mode signal and should never have a pull-down resistor. The remaining three mode-select signals must each have a 4.7-K¾ pull-up or pull-down resistor. These signals are sampled on the rising edge of Reset Output (RSTO). ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 19-37...
Page 448: 19.19 Power Supply Pins
When the on-chip USB transceiver is not used, USB_GND should be connected to the device GND and USB_VDD left unconnected. Refer to Section 12.2.1.1 USB Transceiver Interface. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 19-38 Freescale Semiconductor...
Page 449: Bus Operation
Table 20-1. ColdFire Bus Signal Summary Signal Name Description A[22:0] Address bus BS[3:0] Byte strobes CS[7:0] Chip selects D[31:0] Data bus INT[6:1] Interrupt request Output enable Read/write Transfer acknowledge Transfer error acknowledge ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 20-1...
Page 450: Address Bus (A[22:0])
TA should be negated on the negating edge of the active chip select. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 20-2 Freescale Semiconductor...
Page 451: Transfer Error Acknowledge (Tea)
SDRAM control signals are BS[3:0], SDBA[1:0], RAS0, CAS0, SDWE, A10_PRECHG, SDCLKE, and CS7/SDCS. The asynchronous INT[6:1] signals are internally synchronized to resolve the input to a valid level before being used. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 20-3...
Page 452: Data Transfer Mechanism
OP0; OP3 is the least significant byte. The two bytes of a word length operand are OP2 (most significant) and OP3. The single byte of a byte length operand is OP3. These designations are used in the figures and descriptions that follow. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 20-4 Freescale Semiconductor...
Page 453: Internal Operand Representation
D[23:16] for interfacing to a 16-bit port, or it can be routed to D[31:24] for interfacing to an 8-bit port. The operand size, address, and port size of the memory being accessed determines the positioning of bytes. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 20-5...
Page 454: Byte Strobe Operation For 32-Bit Data Bus
D[23:16] Word D[31:16] Table 20-5. Byte Strobe Operation for 16-Bit Data Bus—SDRAM Cycles BS3 BS2 Access Type Data Located On None — Byte D[23:16] Byte D[31:24] Word D[31:16] ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 20-6 Freescale Semiconductor...
Page 455: External Bus Interface Types
External Bus Interface Types The MCF5272 supports three types of external bus interfaces. The interface type is programmed using CSBRn[EBI]. The EBI codes are summarized in Table 20-7. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 20-7...
Page 456: Interface For Flash/Sram Devices With Byte Strobes
A[22:0] D[31:0] OE, BS[3:0] Figure 20-3. Longword Read; EBI = 00; 32-Bit Port; Internal Termination NOTE Wait states, if needed, are added immediately after C2 in Figure 20-3. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 20-8 Freescale Semiconductor...
Page 457: Word Write; Ebi = 00; 16-/32-Bit Port; Internal Termination
Figure 20-4. Word Write; EBI = 00; 16-/32-Bit Port; Internal Termination SDCLK A[22:0] D[31:0] OE, BS[3:0] Figure 20-5. Longword Read with Address Setup; EBI = 00; 32-Bit Port; Internal Termination ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 20-9...
Page 458: Longword Write With Address Setup; Ebi = 00; 32-Bit Port; Internal Termination
Figure 20-6. Longword Write with Address Setup; EBI = 00; 32-Bit Port; Internal Termination SDCLK A[22:0] D[31:0] OE, BS[3:0] Figure 20-7. Longword Read with Address Hold; EBI = 00; 32-Bit Port; Internal Termination ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 20-10 Freescale Semiconductor...
Page 459: Longword Write With Address Hold; Ebi = 00; 32-Bit Port; Internal Termination
Figure 20-8. Longword Write with Address Hold; EBI = 00; 32-Bit Port; Internal Termination SDCLK A[22:0] D[31:0] BS[3:0] Figure 20-9. Longword Read; EBI = 00; 32-Bit Port; Terminated by TA with One Wait State ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 20-11...
Page 460: Interface For Flash/Sram Devices Without Byte Strobes
CSORn[WS]. The external transfer acknowledge signal, TA, is provided to allow off-chip control of wait states. External control of wait states is enabled when CSORn[WS] is 0x1F. SDCLK A[22:0] D[31:0] BS[3:0] Figure 20-10. Longword Read; EBI=11; 32-Bit Port; Internal Termination ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 20-12 Freescale Semiconductor...
Page 461: Word Write; Ebi=11; 16/32-Bit Port; Internal Termination
Bus Operation SDCLK A[22:0] D[31:0] BS[1:0] BS[3:2] Figure 20-11. Word Write; EBI=11; 16/32-Bit Port; Internal Termination ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 20-13...
Page 462: Read With Address Setup; Ebi=11; 32-Bit Port; Internal Termination
BS[3:0] Figure 20-12. Read with Address Setup; EBI=11; 32-Bit Port; Internal Termination SDCLK A[22:0] D[31:0] BS[3:0] Figure 20-13. Longword Write with Address Setup; EBI=11; 32-Bit Port; Internal Termination ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 20-14 Freescale Semiconductor...
Page 463: Read With Address Hold; Ebi=11; 32-Bit Port; Internal Termination
BS[3:0] Figure 20-14. Read with Address Hold; EBI=11; 32-Bit Port; Internal Termination SDCLK A[22:0] D[31:0] BS[3:0] Figure 20-15. Longword Write with Address Hold; EBI=11; 32-Bit Port; Internal Termination ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 20-15...
Page 464 Bus Operation SDCLK A[22:0] D[31:0] BS[3:0] Figure 20-16. Longword Read with Address Setup and Address Hold; EBI = 11; 32-Bit Port, Internal Termination ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 20-16 Freescale Semiconductor...
Page 465: Burst Data Transfers
Sixteen byte cache line read bursts from 32-bit wide SDRAM with access times of n-1-1-1. The value of n depends on read, write, page miss, page hit, etc. See Chapter 9, “SDRAM Controller,” ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 20-17...
Page 466: Misaligned Operands
Figure 20-18. Example of a Misaligned Longword Transfer A[2:0] 24 23 16 15 Transfer 1 — — — Byte 0 Transfer 2 Byte 1 — — — Figure 20-19. Example of a Misaligned Word Transfer ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 20-18 Freescale Semiconductor...
Page 467: Interrupt Cycles
An access that requires more than one transfer aborts without completing the remaining transfers if TEA is asserted, regardless of whether the access uses burst or non-burst transfers. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 20-19...
Page 468: Longword Write Access To 32-Bit Port Terminated With Tea Timing
This example shows TEA being asserted during C3. TEA can be asserted earlier or later than C3. NOTE If TA is asserted when debug transfer error-acknowledge (TEA) is asserted, the transfer is terminated with a bus error. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 20-20 Freescale Semiconductor...
Page 469: 20.11 Bus Arbitration
Master reset must be asserted for all power-on resets. This is done by driving RSTI and DRESETEN low simultaneously. Failure to assert master reset during power-on sequences results in unpredictable DRAM controller behavior. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 20-21...
Page 470: 20.12.1 Master Reset
During an external master reset, SCR[RSTSRC] is set to 0b11 to indicate that assertion of RSTI and DRESETEN caused the previous reset. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 20-22...
Page 471: 20.12.2 Normal Reset
During the normal reset period, all outputs are driven to their default levels. Once RSTO negates, all bus signals continue to remain in this state until the ColdFire core begins the first bus cycle for reset exception processing. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 20-23...
Page 472: 20.12.3 Software Watchdog Timer Reset Operation
ColdFire core begins the first bus cycle for reset exception processing. During a software watchdog timer reset, SCE[RSTSRC] is set to 0b10 to indicate the software watchdog as the source of the previous reset. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 20-24 Freescale Semiconductor...
Page 473: 20.12.4 Soft Reset Operation
SDRAM refreshes continue to be generated during and after reset at the programmed rate and with the programmed waveform timing. During the soft reset period, all bus signals continue to operate normally. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 20-25...
Page 474 Bus Operation ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 20-26 Freescale Semiconductor...
Page 475: Ieee 1149.1 Test Access Port (Jtag)
Bypass the MCF5272 for a given circuit board test by effectively reducing the boundary-scan register to a single bit • Disable the output drive to pins during circuit-board testing • Drive output pins to stable levels ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 21-1...
Page 476: Jtag Test Access Port And Bdm Debug Port
TCK. When not outputting data, TDO is placed in high-impedance state. TDO can also be three-stated to allow bused or parallel connections to other devices having JTAG test access ports. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 21-2...
Page 477: Tap Controller
TMS sampled on the rising edge of TCK. For a description of the TAP controller states, refer to the IEEE 1149.1 document. Figure 21-2. TAP Controller State Machine ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 21-3...
Page 478: Boundary Scan Register
To next Shift DR 0 = Otherwise cell Data from system To output logic buffer From last cell Clock DR Update DR Figure 21-3. Output Cell (O.Cell) (BC–1) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 21-4 Freescale Semiconductor...
Page 479: Input Cell (I.cell). Observe Only (Bc–4)
0 = HI-Z 1 = Otherwise To output Output control buffer from system logic I/O direction From last cell Clock DR Update DR Figure 21-5. Output Control Cell (En.Cell) (BC–4) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 21-5...
Page 480: Bidirectional Cell (Io.cell) (Bc–6)
From input Data buffer to system logic From last cell Clock DR Update DR Figure 21-6. Bidirectional Cell (IO.Cell) (BC–6) Figure 21-7. General Arrangement for Bidirectional Pins ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 21-6 Freescale Semiconductor...
Page 481: Instruction Register
TCK in the capture-DR controller state. Therefore, the first bit to be shifted out after selecting the bypass register is always a logic zero. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 21-7...
Page 482: Restrictions
If TMS is unconnected or connected to V , the TAP controller cannot exit test-logic-reset state, regardless of the TCK state. This requires the TMS, TCK, and TDI inputs to be high. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 21-8 Freescale Semiconductor...
Page 483: Mechanical Data
RXDV TXER RSTI BYPASS CLKIN GDCL DREQ DGNT BUSW TOUT QSPI DOUT DRESE DOUT RXCLK MDIO WSEL QSPI QSPI TXEN TOUT DOUT Figure 22-1. MCF5272 Pinout (196 MAPBGA) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 22-1...
Page 484: Package Dimensions
Mechanical Data 22.2 Package Dimensions Figure 22-2 shows MCF5272 package dimensions. Figure 22-2. 196 MAPBGA Package Dimensions (Case No. 1128A-01) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 22-2 Freescale Semiconductor...
Page 485: Electrical Characteristics
Reliability improves when unused inputs are tied to an appropriate logic voltage level (GND or V ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 23-1...
Page 486: Operating Temperature
Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 23-2...
Page 487: Dc Electrical Specifications
10 mA 30 pF 10 mA 30 pF SDBA[1:0] 10 mA 30 pF RAS0 10 mA 30 pF CAS0 10 mA 30 pF SDCLK 10 mA 30 pF ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 23-3...
Page 488 2 mA 30 pF E_TxERR 2 mA 30 pF Requires external protection circuitry to meet USB 1.1 electrical requirements under all conditions (see 12.5.3, “Recommended USB Protection Circuit”). ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 23-4 Freescale Semiconductor...
Page 489: Ac Electrical Specifications
Specification values listed are for maximum frequency of operation. Clock input and output timings listed in Table 23-6 are shown in Figure 23-1. CLKIN (input) Figure 23-1. Clock Input Timing Diagram ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 23-5...
Page 490: Processor Bus Input Timing Specifications
All timing references to SDCLK are given to its rising edge when bit 3 of the SDRAM control register is 0. RSTI, TA, TEA, and INTx are synchronized internally. The setup time must be met only if recognition is needed on a particular clock edge. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 23-6 Freescale Semiconductor...
Page 491: General Input Timing Requirements
= 1.5 nS fall Input Fall Time SDCLK Inputs * The timings are also valid for inputs sampled on the negative clock edge. Figure 23-2. General Input Timing Requirements ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 23-7...
Page 492: Processor Bus Output Timing Specifications
Wait states are inserted for SRAM accesses by programming bits 6–2 of the chip select option registers. A wait state is added for SDRAM read accesses by setting bit 4 of the SDRAM control register. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 23-8 Freescale Semiconductor...
Page 493: Read/Write Sram Bus Timing
Read/write SRAM bus timings listed in Table 23-8 are shown in Figure 23-3, Figure 23-4, Figure 23-5, Figure 23-6. SDCLK A[22:0] BS[3:0] D[31:0] TEA (H) Figure 23-3. Read/Write SRAM Bus Timing ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 23-9...
Page 494: Sram Bus Cycle Terminated By Ta
Figure 23-4 shows an SRAM bus cycle terminated by TA showing timings listed in Table 23-8. SDCLK A[22:0] BS[3:0] D[31:0] Figure 23-4. SRAM Bus Cycle Terminated by TA ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 23-10 Freescale Semiconductor...
Page 495: Sram Bus Cycle Terminated By Tea
Figure 23-5 shows an SRAM bus cycle terminated by TEA showing timings listed in Table 23-8. SDCLK A[22:0] BS[3:0] D[31:0] Figure 23-5. SRAM Bus Cycle Terminated by TEA ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 23-11...
Page 496: Reset And Mode Select/Hiz Configuration Timing
Table 23-8. SDCLK Reset is asynchronous. Assert for at least 2 RSTI consecutive SDCLK rising edges Mode selects (BUSW[1,0], WSEL,HIZ) Figure 23-6. Reset and Mode Select/HIZ Configuration Timing ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 23-12 Freescale Semiconductor...
Page 497: Debug Ac Timing Specifications
Figure 23-7. Real-Time Trace AC Timing Figure 23-8 shows BDM serial port AC timing for the values in Table 23-9. PSTCLK DSCLK Current Next Past Current Figure 23-8. BDM Serial Port AC Timing ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 23-13...
Page 498: Sdram Interface Timing Specifications
Wait states are inserted for SRAM accesses by programming bits 6–2 of the chip select option registers. A wait state is added for SDRAM read accesses by setting bit 4 of the SDRAM control register. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 23-14 Freescale Semiconductor...
Page 499: Sdram Signal Timing
RAS0 CAS0 SDCLKE SDWE DQMx SD14 DATA IN (READ SDCR (b4=1)) SD16 SD15 DATA IN (READ SDCR (b4=0)) SD16 SD13 DATA OUT (WRITE) Figure 23-9. SDRAM Signal Timing ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 23-15...
Page 500: Sdram Self-Refresh Cycle Timing
Electrical Characteristics Figure 23-10 shows SDRAM self-refresh timings listed in Table 23-10. SDCLK SDWE RAS0 CAS0 Figure 23-10. SDRAM Self-Refresh Cycle Timing ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 23-16 Freescale Semiconductor...
Page 501: Mii Receive Signal Timing Diagram
E_RxDV, E_RxCLK, and E_RxD0 have same timing in 10 Mbit 7-wire interface mode. Figure 23-11 shows MII receive signal timings listed in Table 23-11. E_RxCLK (input) E_RxD[3:0] (inputs) E_RxDV E_RxER Figure 23-11. MII Receive Signal Timing Diagram ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 23-17...
Page 502: Mii Transmit Signal Timing Diagram
E_TxCLK, ETxD0, and E_TxEN have the same timing in 10 Mbit 7-wire interface mode. Figure 23-12 shows MII transmit signal timings listed in Table 23-12. E_TxCLK (input) E_TxD[3:0] (outputs) E_TxEN E_TxER Figure 23-12. MII Transmit Signal Timing Diagram ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 23-18 Freescale Semiconductor...
Page 503: Mii Async Inputs Signal Timing (Crs And Col)
E_COL has the same timing in 10 Mbit 7-wire interface mode. Figure 23-13 shows MII asynchronous input timings listed in Table 23-13. E_CRS, E_COL Figure 23-13. MII Async Inputs Timing Diagram ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 23-19...
Page 504: Mii Serial Management Channel Timing (Mdio And Mdc)
MDC period Figure 23-14 shows MII serial management channel timings listed in Table 23-14. MDC (output) MDIO (output) MDIO (input) Figure 23-14. MII Serial Management Channel Timing Diagram ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 23-20 Freescale Semiconductor...
Page 505: Timer Module Ac Timing Specifications
All timing references to SDCLK are given to its rising edge when bit 3 of the SDRAM control register is 0. Figure 23-15 shows timer module timings listed in Table 23-15. SDCLK TIN1 IN (Capture Mode Synchronization) TIN1 IN (Clock Mode) Figure 23-15. Timer Timing ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 23-21...
Page 506: Uart Modules Ac Timing Specifications
All timing references to SDCLK are given to its rising edge when bit 3 of the SDRAM control register is 0. Figure 23-16 shows UART module timings listed in Table 23-16. SDCLK URTn_RxD URTn_CTS URTn_TxD URTn_RTS Figure 23-16. UART Timing ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 23-22 Freescale Semiconductor...
Page 507: Plic Module: Idl And Gci Interface Timing Specifications
Based on generated GDCL1_OUT less than 1/20 of CPU clock frequency. Figure 23-17 shows IDL master timings listed in Table 23-17. DFSC[3:1] GDCL1_OUT DOUT1, DOUT3 DIN1, DIN3 Figure 23-17. IDL Master Timing ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 23-23...
Page 508: Idl Slave Mode Timing, Plic Ports 0–3
— FSR occurs on average every 125 μs. In IDL slave mode, DCL may be any frequency multiple of 8 KHz between 256 KHz and 4.096 MHz inclusive. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 23-24 Freescale Semiconductor...
Page 509: Idl Slave Timing
Data valid on DIN1 or DIN3 before rising edge of DCL1 Data valid on DIN0 after rising edge of DCL0, — Data valid on DIN1 or DIN3 after rising edge of DCL1 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 23-25...
Page 510: Gci Slave Mode Timing
Ports 1, 2, 3. Same as DCL0 and FSC0 if internal clock generator configured for pass-through mode. Based on generated GDCL1_OUT less than 1/20 of CPU clock frequency. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 23-26 Freescale Semiconductor...
Page 511: Gci Master Mode Timing
Electrical Characteristics Figure 23-20 shows GCI master timings listed in Table 23-20. GDCL1_OUT DFSC1 DFSC2 DFSC3 DOUT1 DOUT3 DIN1 DIN3 Figure 23-20. GCI Master Mode Timing ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 23-27...
Page 512: 23.10 General-Purpose I/O Port Ac Timing Specifications
All timing references to SDCLK are given to its rising edge when bit 3 of the SDRAM control register is 0. Figure 23-21 shows GPIO timings listed in Table 23-21. SDCLK PORTx IN PORTx OUT Figure 23-21. General-Purpose I/O Port Timing ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 23-28 Freescale Semiconductor...
Page 513: Usb Interface Timing
Figure 23-22 shows USB timings listed in Table 23-22. USB_CLK (input) US4b US4a USB_RP USB_RN USB_RxD USB_TP USB_TN USB_SUSP USB_TxEN Figure 23-22. USB Interface Timing ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 23-29...
Page 514: 23.12 Ieee 1149.1 (Jtag) Ac Timing Specifications
TCK falling edge to boundary scan data high impedance — Figure 23-23 shows JTAG timings listed in Table 23-23. TDI, TMS Boundary Scan Data Inputs TRST Boundary Scan Data Outputs Figure 23-23. IEEE 1149.1 (JTAG) Timing ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 23-30 Freescale Semiconductor...
Page 515: Qspi Timing
T is defined as clock period in nS. See Table 23-6. The values in Table 23-24 correspond to Figure 23-24. QSPI_CS[3:0] QSPI_CLK QSPI_DOUT QSPI_DIN Figure 23-24. QSPI Timing ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor 23-31...
Page 516: 23.14 Pwm Electrical Specifications
All timing references to SDCLK are given to its rising edge when bit 3 of the SDRAM control register is 0. Parameter tested The values in Table 23-25 correspond to Figure 23-25. SDCLK PWM_OUT[2:0] Figure 23-25. PWM Timing ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 23-32 Freescale Semiconductor...
Page 517 UART1 Module Registers MBAR+0x0140 UART1_Base SDRAM Controller Registers MBAR+0x0180 SDRAMC_Base Timer Module Registers MBAR+0x0200 Timer_Base PLIC Module Registers MBAR+0x0300 PLIC_Base Ethernet Module Registers MBAR+0x0800 ENET_Base USB Module Registers MBAR+0x1000 USB_Base ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 518: Appendix A List Of Memory Maps
Interrupt Control Register 4 (ICR4) 0x0030 Interrupt Source Register (ISR) 0x0034 Programmable Interrupt Transition Register (PITR) 0x0038 Programmable Interrupt Wakeup Register (PIWR) 0x003F Reserved Programmable Interrupt Vector Register (PIVR) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 519: A-5 Chip Select Register Memory Map
Reserved 0x008E Reserved Port B Data Register (PBDAT) 0x0094 Port C Data Direction Register (PCDDR) Reserved 0x0096 Reserved Port C Data Register (PCDAT) 0x0098 Port D Control Register (PDCNT) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 520: A-7 Qspi Module Memory Map
Offset 0x00E0 DMA Mode Register (DCMR) 0x00E6 DMA Interrupt Register (DCIR) 0x00E8 DMA Byte Count Register (DBCR) 0x00EC DMA Source Address Register (DSAR) 0x00F0 DMA Destination Address Register (DDAR) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 521: A-10 Uart0 Module Memory Map
Divider Control Registers (UFPDn) 0x0134 UART0 CTS Unlatched Reserved Input (U0IP) 0x0138 UART0 RTS O/P Bit Set Reserved Command Register (U0OP1) 0x013C UART0 RTS O/P Bit Reset Reserved Command Register (U0OP0) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 522: A-11 Uart1 Module Memory Map
Divider Control Registers (UFPDn) 0x0174 UART1 CTS Unlatched Reserved Input (U1IP) 0x0178 UART1 RTS O/P Bit Set Reserved Command Register (U1OP1) 0x017C UART1 RTS O/P Bit Reset Reserved Command Register (U1OP0) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 523: A-12 Sdram Controller Memory Map
Timer 3 Event Register (TER3) Reserved 0x0280 Watchdog Reset Reference Register (WRRR) Reserved 0x0284 Watchdog Interrupt Reference Register (WIRR) Reserved 0x0288 Watchdog Counter Register (WCR) Reserved 0x028C Watchdog Event Register (WER) Reserved ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 524: A-14 Plic Module Memory Map
GCI C/I TX Status (PGCITSR) 0x0383 Reserved GCI D-Channel Status (PDCSR) 0x0384 Port0 Periodic Status (P0PSR) Port1 Periodic Status (P1PSR) 0x0388 Port2 Periodic Status (P2PSR) Port3 Periodic Status (P3PSR) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 525: A-15 Ethernet Module Memory Map
0x0C0C Ethernet Hash Table (Lower) (HTLR) 0x0C10 Ethernet Rx Descriptor Ring (ERDSR) 0x0C14 Ethernet Tx Descriptor Rin (ETDSR) 0x0C18 Ethernet Rx Buffer Size (EMRBR) 0x0C40– FIFO RAM (EFIFO) 0x0DFF ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 526: A-16 Usb Module Memory Map
USB Endpoint 4 Interrupt Status Register (EP4ISR) 0x10A2 Reserved USB Endpoint 5 Interrupt Status Register (EP5ISR) 0x10A6 Reserved USB Endpoint 6 Interrupt Status Register (EP6ISR) 0x10AA Reserved USB Endpoint 7 Interrupt Status Register (EP7ISR) ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 A-10 Freescale Semiconductor...
Page 527 USB Endpoint 5 Data Present Register (EP5DPR) 0x10E6 Reserved USB Endpoint 6 Data Present Register (EP6DPR) 0x10EA Reserved USB Endpoint 7 Data Present Register (EP7DPR) 0x1400 – USB Configuration RAM, 1 K Bytes 0x17FF ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor A-11...
Page 528 List of Memory Maps ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 A-12 Freescale Semiconductor...
Page 529 NEVER put buffers between the MCF5272 device and the SDRAMs. • Put termination resistors as close as possible to outputs. • Or use buffers that have integral termination resistors. ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 530 = Resistor Arrays 10-75 ohms RA1, RA2, RA3, ... R1, R2, ... = resistor 10-75 ohms B[7:0] A[7:0] D31:D0 Signals M CF5272 SDRAM Flash Device Device Device Figure B-1. Buffering and Termination ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor...
Page 531 20-24 bus, 20-2 transfer acknowledge (TA), 20-2 Debug transfer error acknowledge (TEA), 20-3 attribute trigger register, Byte strobes, 20-8 BDM command set summary, 5-19 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor Index-1...
Page 532 External bus interface overview, control register, 11-11 descriptor active register, 11-15 descriptor ring register pointer-to-receive, 11-30 Fault-on-fault halt, 5-16 pointer-to-transmit, 11-31 Features overview, error handling, 11-9 Frame reception, 11-5 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Index-2 Freescale Semiconductor...
Page 533 JTAG Organization, 1-xl BDM debug port, 21-2 Output port command registers, 16-18 boundary scan register, 21-4 IDCODE register, 6-11 instruction register, 21-7 Parallel input/output ports, overview, 21-1 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor Index-3...
Page 534 PST outputs, GCI C/I channel PULSE instruction, receive registers, 13-28 transmit registers, 13-29 control register, 18-3 transmit status register, 13-30 operation, 18-2 GCI interrupts aperiodic status, 13-10 overview, 18-1 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Index-4 Freescale Semiconductor...
Page 535 ALPR, 6-10 event, 11-12 B2 data transmit, 13-17 mask, 11-13 BI data receive, 13-15 vector status, 11-14 cache configuration, interrupt controller cache control, 4-12 pending and mask, 7-5, ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor Index-5...
Page 536 15-4 transmit, 13-25 TDR, 5-14 transmit status, 13-27 TER, 15-5 general, 13-15 timer interrupt configuration, 13-20 capture, 15-4 loopback control, 13-20 event, 15-5 memory map, 13-13 general-purpose, 15-3 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Index-6 Freescale Semiconductor...
Page 537 USB_D+ and USB_D-, 19-26 operation, wake-on-ring, 19-26 overview, programming model, overview, ROMBAR programming model, overview, register memory map, power management programming, Software watchdog timer, 6-11 SRAM ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor Index-7...
Page 538 12-17, 12-20 Timings FIFO configuration, 12-32 SDRAM refresh, 9-20 frame number match register, 12-9 Transmit signal timing, 23-18 function address register, 12-11 IN endpoints, 12-33, 12-34 initialization, 12-31 ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Index-8 Freescale Semiconductor...
Page 539 Variant address, Vector base register, 2-8, Version 2 ColdFire core overview, Wait state generation overview, Watchdog counter register, 6-13 event register, 6-13 interrupt reference register, 6-12 WDDATA execution, ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor Index-9...
Page 540 Index ® MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3 Index-10 Freescale Semiconductor...
Page 541: Physical Layer Interface Controller (Plic
Overview ColdFire Core Hardware Multiply/Accumulate (MAC) Unit Local Memory Debug Support System Integration Module (SIM) Interrupt Controller Chip-Select Module SDRAM Controller DMA Controller Module Ethernet Module Universal Serial Bus (USB) Physical Layer Interface Controller (PLIC) Queued Serial Peripheral Interface (QSPI) Module Timer Module UART Modules General-Purpose I/O Module...
Page 542: Queued Serial Peripheral Interface (Qspi) Module
Overview ColdFire Core Hardware Multiply/Accumulate (MAC) Unit Local Memory Debug Support System Integration Module (SIM) Interrupt Controller Chip-Select Module SDRAM Controller DMA Controller Module Ethernet Module Universal Serial Bus (USB) Physical Layer Interface Controller (PLIC) Queued Serial Peripheral Interface (QSPI) Module Timer Module UART Modules General-Purpose I/O Module...
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Page 544: Electrical Characteristics
How to Reach Us: Home Page: www.freescale.com RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free E-mail: counterparts. For further information, see http://www.freescale.com or contact your support@freescale.com Freescale sales representative. USA/Europe or Locations Not Listed: Freescale Semiconductor For information on Freescale’s Environmental Products program, go to Technical Information Center, CH370...
Page 545 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: MCF5272VM66 MCF5272CVM66 MCF5272CVF66 MCF5272VF66 MCF5272VF66R2 MCF5272VM66R2 MCF5272CVF66J MCF5272CVM66J MCF5272VF66J MCF5272VF66R2J MCF5272VM66J MCF5272VM66R2J...

NXP Semiconductors MCF5272 ColdFire User Manual

Paragraph Page

Number

Chapter 1

Chapter 3 Hardware Multiply/Accumulate (MAC) Unit

Chapter 4 Local Memory

Chapter 5 Debug Support

Chapter 6 System Integration Module (SIM)

Chapter 7 Interrupt Controller

Chapter 2 Coldfire Core

Chapter 8 Chip Select Module

Chapter 9 SDRAM Controller

Chapter 10 DMA Controller

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Summary of Contents for NXP Semiconductors MCF5272 ColdFire