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NXP Semiconductors MCF5253 Reference Manual

NXP Semiconductors MCF5253 Reference Manual

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MCF5253

Reference Manual

Document Number: MCF5253RM

Rev. 1

08/2008

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Summary of Contents for NXP Semiconductors MCF5253

Page 1 MCF5253 Reference Manual Document Number: MCF5253RM Rev. 1 08/2008...
Page 2 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted Home Page: hereunder to design or fabricate any integrated circuits or integrated circuits based on the information www.freescale.com in this document.
Page 3: Table Of Contents
MCF5253 Feature Introduction ........
Page 4 MCF5253 Bus Signals ........
Page 5 Audio Clock Generation ............4-6 MCF5253 Reference Manual, Rev. 1...
Page 6 7.3.1.1 DRAM Control Register (DCR) (Synchronous Mode) ......7-4 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 7 Software Watchdog Reset..........8-15 MCF5253 Reference Manual, Rev. 1...
Page 8 MCF5253 Bus Arbitration Control Registers ........
Page 9 Functional Description ............12-4 MCF5253 Reference Manual, Rev. 1...
Page 10 Destination Address Register ..........14-6 MCF5253 Reference Manual, Rev. 1...
Page 11 Local Loopback Mode ..........15-11 MCF5253 Reference Manual, Rev. 1...
Page 12 Interrupt Handling........... . 15-29 MCF5253 Reference Manual, Rev. 1...
Page 13 Control Channel Reception Register Descriptions ......17-16 17.6.1.3 Control Channel Interrupt (IEC958 “C” Channel New Frame) ....17-17 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor xiii...
Page 14 C Overview ............. . 18-2 MCF5253 Reference Manual, Rev. 1...
Page 15 UART Protocol ........... . 19-6 MCF5253 Reference Manual, Rev. 1...
Page 16 Read Control Register (RCREG) ........20-22 MCF5253 Reference Manual, Rev. 1...
Page 17 Restrictions ..............21-9 MCF5253 Reference Manual, Rev. 1...
Page 18 Register Descriptions ........... . 23-18 MCF5253 Reference Manual, Rev. 1...
Page 19 Using DMA Mode to Transmit Data to ATA Bus ......23-35 Chapter 24 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 20 Endpoint Flush Register (ENDPTFLUSH), Non-EHCI..... . . 24-40 24.6.3.19 Endpoint Status Register (ENDPTSTATUS), Non-EHCI ..... 24-41 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 21 Periodic Scheduling Threshold ........24-78 MCF5253 Reference Manual, Rev. 1...
Page 22 Interrupt on Async Advance ........24-120 MCF5253 Reference Manual, Rev. 1...
Page 23 Device Error Matrix ..........24-146 MCF5253 Reference Manual, Rev. 1...
Page 24 FlexCAN Free Running Timer Register (TIMERn)......25-11 MCF5253 Reference Manual, Rev. 1...
Page 25 Battery Removal Detection..........26-2 MCF5253 Reference Manual, Rev. 1...
Page 26: Mcf5253 Reference Manual,
MCF5253 Reference Manual, Rev. 1 xxvi Freescale Semiconductor...
Page 27 Audience The MCF5253 Reference Manual is intended to provide a design engineer with the necessary data to successfully integrate the MCF5253 into a wide variety of applications. It is assumed that the reader understands operating systems, microprocessor system design, basic principles of software and hardware, and basic details of the ColdFire architecture.
Page 28 (SIM)”:This chapter describes the operation, memory map, and register definitions of the System Integration Module (SIM) registers, including the interrupt controller and system-protection functions for the MCF5253. The SIM provides overall control of the internal and external buses and serves as the interface between the ColdFire®...
Page 29 Interface”: This chapter describes the universal serial bus (USB) interface of the MCF5253. The content includes the operation, signal descriptions, host data structures, and host operations. Also provided is the device operational model and deviations from the host mode of operation.
Page 30 4. PowerPC Virtual Environment Architecture, Book II, Version 1.00, 5/19/92 (subtitled “Work in Progress”) Register Summary Figure 1 shows the key to the register fields and Table 2 shows the register figure conventions. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 31 Self-clearing bit. Writing a one has some effect on the module, but it always reads as zero. Reset Values Resets to zero. Resets to one. — Undefined at reset. Unaffected by reset. [signal_name] Reset value is determined by polarity of indicated signal. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor xxxi...
Page 32 MCF5253 Reference Manual, Rev. 1 xxxii Freescale Semiconductor...
Page 33: Mcf5253 Introduction
MCF5253 features and modules. The MCF5253 is also an excellent general purpose system controller with over 125 Dhrystone 2.1 MIPS @ 140 MHz performance at a very competitive price. The integrated peripherals and eMAC allow the MCF5253 to replace both the microcontroller and the DSP in certain applications.
Page 34: Mcf5253 Block Diagram
1.2 V core, 3.3 V I/O • Internal 1.2 V Linear regulator to power the core (configuration is optional) • 225 pin MAPBGA package MCF5253 Block Diagram Figure 1-1 provides the block diagram of the MCF5253 device. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 35 RTC Pins Real-Time Clock FlashMedia Logic Pins USB Analog Memory Stick/SD Interface USB XTAL USB XTAL Pins Oscillator USB 2.0 OTG Controller 16 Kbyte ATA Pins SRAM Controller Figure 1-1. MCF5253 Block Diagram MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 36: Mcf5253 Feature Details
MCF5253 Introduction MCF5253 Feature Details The primary features of the MCF5253 integrated processor include the following: • ColdFire CF2 Processor Core operating at 140 MHz — Clock-doubled Version 2 microprocessor core — 32-bit internal data bus, 16 bit external data bus —...
Page 37 — Supports transfer sizes of 8 to 16 bits in 1-bit increments — Four peripheral chip-select lines for control of up to 15 devices — Supports Baud rates up to 17.5 Mbps at 140 MHz — Programmable delays before and after transfers MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 38 (Flash / ROM) then CS0 is active after reset. — Programmable interrupt controller (low interrupt latency, seven external interrupt requests, programmable autovector generator) — Up to 57 programmable general-purpose outputs — Up to 60 programmable general-purpose inputs MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 39: Mcf5253 Functional Overview
1.5.2 DMA Controller The MCF5253 provides four fully programmable DMA channels for quick data transfer. Single and dual address mode is supported with the ability to program bursting and cycle stealing. Data transfer is selectable as 8-, 16-, 32-, or 128-bits. Packing and unpacking is supported.
Page 40: Instruction Cache
USB 2.0 High-Speed On-The-Go The USB module in the MCF5253 is used for communication to a PC or communication to slave devices, e.g. to download data from a hard disc player to a flash player, to a photo printer and so on. The USB supports full Host mode functionality.
Page 41: Ata Controller
1.5.14 IEC958 Digital Audio Interfaces The MCF5253 has two digital audio input interfaces, and one digital audio output interface. There are four digital audio input pins and two digital audio output pins. An internal multiplexer selects one of the four inputs to one of the two digital audio inputs.
Page 42: Cd-Rom Encoder/Decoder
The audio bus can also be used for audio format conversion. 1.5.16 CD-ROM Encoder/Decoder The MCF5253 is capable of processing CD-ROM sectors in hardware. Processing is compliant with CD-ROM and CD-ROM XA standards. The CD-ROM decoder performs the following functions in hardware: •...
Page 43: Timer Module
1.5.20 IDE Interface The MCF5253 system bus allows connection of an IDE hard disk drive with a minimum of external hardware. The external hardware consists of bus buffers for address and data and are intended to reduce the load on the bus and prevent SDRAM and Flash accesses from propagating to the IDE bus. The control signals for the buffers are generated in the MCF5253.
Page 44: Gpio Interface
CS0 is intended to be used with an external boot ROM / Flash memory. The MCF5253 can boot from its internal boot ROM, here CS0 is used internally, CS0/CS4 pin is then is configured as CS4. CS0 and CS4 cannot be used simultaneously.
Page 45: Sleep And Wake-Up Modes
1.5.32 Internal Voltage Regulator An internal 1.2 V regulator can be used to supply the CPU and PLL sections of the MCF5253, reducing the number of external components required and allowing operation from a single supply rail, typically 3.3 volts. However, it must be noted that the internal regulator has an efficiency of less than 50%, and it is not intended for use in battery powered applications, where the use of a highly efficient external DC-DC converter would be more appropriate.
Page 46 MCF5253 Introduction MCF5253 Reference Manual, Rev. 1 1-14 Freescale Semiconductor...
Page 47: Signal Description
Chapter 2 Signal Description Overview This chapter describes the MCF5253 input and output signals. The signal descriptions as shown in Table 2-1 are grouped according to relevant functionality. Table 2-1. MCF5253 Signal Index Input/ Reset Signal Name Mnemonic Function Output...
Page 48 Signal Description Table 2-1. MCF5253 Signal Index (continued) Input/ Reset Signal Name Mnemonic Function Output State Chip Selects[2:0] CS0/CS4 Chip selects bits 2 through 0— negated CS1/QSPICS3/GPIO28 enable peripherals at programmed In/Out addresses. CS0 provides boot ROM selection. Buffer enable 1...
Page 49 Signal Description Table 2-1. MCF5253 Signal Index (continued) Input/ Reset Signal Name Mnemonic Function Output State Serial input EF/RXD2/GPIO6 Error flag serial in In/Out – Serial input CFLG/GPIO5 C-flag serial in In/Out – Subcode clock RCK/QSPIDIN/QSPIDOUT/ Audio interfaces to subcode clock In/Out –...
Page 50 Signal Description Table 2-1. MCF5253 Signal Index (continued) Input/ Reset Signal Name Mnemonic Function Output State CAN interface CAN0_TX CAN 0 transmit – CAN0_RX CAN 0 receive – CAN1_TX CAN 1 transmit – CAN1_RX CAN 1 receive – USB PHY interface...
Page 51: Gpio
• At Power-on reset all pins are set to their primary function. MCF5253 Bus Signals The signals discussed in this section provide the external bus interface to the MCF5253. 2.3.1 Address Bus The address bus provides the address of the byte or most significant byte of the word or longword being transferred.The address lines also serve as the DRAM address pins, providing multiplexed row and column...
Page 52: Read-Write Control
2.3.4 Data Bus The data bus (D[31:16]) is bi-directional and non-multiplexed. Data is registered by the MCF5253 on the rising clock edge. The data bus uses a default configuration if none of the chip-selects or DRAM bank match the address decode. All 16 bits of the data bus are driven during writes, regardless of port width or operand size.
Page 53: Chip Selects
The active low chip selects can be used to access asynchronous memories. The interface is glueless. ISA Bus The MCF5253 supports an ISA bus. Using the ISA bus protocol, reads and writes for one ISA bus peripheral is possible. IDE_DIOR/GPIO31 and IDE_DIOW/GPIO32 are the read and write strobe. The peripheral can insert wait states by pulling IDE_IORDY/GPIO33.
Page 54: Serial Module Signals
The third UART lacks flow control using RTS/CTS. Clear To Send Peripherals drive the DDATA2/CTS0/GPIO3 and DDATA0/CTS1/SDATA0_SDIO1/GPIO1 inputs to indicate to the MCF5253 serial module that it can begin data transmission. The third UART lacks flow control using RTS/CTS. 2.10 Timer Module Signals The following signal provides an external interface to Timer0.
Page 55: Digital Audio Interface Signals
I/O or as digital audio (IEC958) output. EBUOUT1 is digital audio out for consumer mode, EBUOUT2 is digital audio out for professional mode. During reset, the pin is configured as a digital audio output. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 56: Subcode Interface
Signal Description 2.13 Subcode Interface There is a 3-line subcode interface on the MCF5253. This 3-line subcode interface allows the device to format and transmit subcode in EIAJ format to a CD channel encoder device. The three signals are described in Table 2-8.
Page 57: Queued Serial Peripheral Interface (Qspi)
DMA and ultra DMA transfers. Pin descriptions are given in Table 2-1. 2.18 Two Controller Area Network (CAN) Communication Modules The two FlexCan modules are full implementation of the Bosch CAN protocol specification 2.0B. Pin descriptions are given in Table 2-1. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 2-11...
Page 58: Usb Controller
Signal Description 2.19 USB Controller The MCF5253 is fitted with an on-chip USB controller. 2.19.1 USB PHY Interface Including Oscillator There is an integrated on-chip USB PHY. Pins are described in Table 2-11. Table 2-11. USB PHY Interface Pins USB PHY Signal...
Page 59: Test Mode
Processor Status The processor status pins, PST0/GPIO50, PST1/GPIO49, PST2/INTMON/GPIO48, and PST3/INTMON/GPIO47, indicate the MCF5253 processor status. During debug mode, the timing is synchronous with the processor clock (PSTCLK) and the status is not related to the current bus transfer. Table 2-13 shows the encodings of these signals.
Page 60: Bdm/Jtag Signals
These encodings are asserted for multiple cycles. 2.24 BDM/JTAG Signals The MCF5253 complies with the IEEE 1149.1A JTAG testing standard. The JTAG test pins are multiplexed with background debug pins. See Chapter 20, “Background Debug Mode (BDM) Interface,” for details.
Page 61: On-Chip Linear Regulator
The MCF5253 includes an on-chip linear regulator. This regulator provides an 1.2 V output which is intended to be used to power the MCF5253 core. Three pins are associated with this function; LININ, LINOUT, and LINGND. Typically, LININ would be fed by the I/O (PAD) supply (3.3 V) with separate filtering recommended to provide some isolation between the I/O and the core.
Page 62 Signal Description MCF5253 Reference Manual, Rev. 1 2-16 Freescale Semiconductor...
Page 63: Coldfire Core
This chapter provides an overview of the microprocessor core of the MCF5253. The chapter describes the CF2 memory map and register description as it is implemented on the MCF5253. It also includes a full description of exception handling, data formats, an instruction set summary, and a table of instruction timings.
Page 64: Coldfire Processor Memory Map And Register Definitions
Data Registers (D0–D7) Registers D0–D7 are used as data registers for bit (1 bit), byte (8 bit), word (16 bit) and longword (32 bit) operations and can also be used as index registers. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 65: Address Registers (A0-A6)
Also used as an input operand for multiple-precision arithmetic. Negative condition code bit. Set if the msb of the result is set; otherwise cleared. Zero condition code bit. Set if the result equals zero; otherwise cleared. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 66: Enhanced Multiply Accumulate Module (Emac) User Memory Map And Register
CCR register Load MAC Mask Reg MOV.L {Ry,#imm},Rmask Writes a value to the MAC Mask Register Store MAC Mask Reg MOV.L Rmask,Rx Writes the contents of the MAC mask register to a CPU register MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 67: Supervisor Memory Map And Register Description
(CCR). The control bits indicate the following states for the processor: trace mode (T-bit), supervisor or user mode (S bit), and master or interrupt state (M). System Byte Condition Code Register (CCR) I [2–0] Figure 3-4. Status Register MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 68: Vector Base Register (Vbr)
T bit. The occurrence of an interrupt exception also forces the M bit to be cleared and the interrupt priority mask to be set to the level of the current interrupt request. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 69 $008 Fault Access error $00C Fault Address error $010 Fault Illegal instruction $014 Fault Divide by zero 6–7 $018-$01C – Reserved $020 Fault Privilege violation $024 Next Trace $028 Fault Unimplemented line-a opcode MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 70: Exception Stack Frame Definition
Table 3-6. Format Field Encoding Original A7 @ Time of A7 @ 1st Instruction Format Field Exception, Bits 1:0 of Handler Original A7 - 8 Original A7 - 9 Original A7 - 10 Original A7 - 11 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 71: Processor Exceptions
Because the actual write cycle may be decoupled from the processor’s issuing of the operation, the signaling of an access error appears to be decoupled from the instruction that generated the write. Accordingly, the PC contained in the exception stack frame merely represents the location in the program MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 72: Address Error Exception
3.5.3 Illegal Instruction Exception The MCF5253 processors decode the full 16-bit opcode and generate this exception if execution of an unsupported instruction is attempted. Additionally, attempting to execute an illegal line A or line F opcode generates unique exception types: vectors 10 and 11, respectively.
Page 73: Debug Interrupt
The interrupt exception processing, with interrupt recognition and vector fetching, includes uninitialized and spurious interrupts as well as those where the requesting device supplies the 8-bit interrupt vector. Autovectoring may optionally be supported through the System Integration module (SIM). MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 3-11...
Page 74: Fault-On-Fault Halt
1. The operand execution pipeline (OEP) is loaded with the opword and all required extension words at the beginning of each instruction execution. This implies that the OEP does not wait for the instruction fetch pipeline (IFP) to supply opwords and/or extension words. MCF5253 Reference Manual, Rev. 1 3-12 Freescale Semiconductor...
Page 75: Move Instruction Execution Times
Table 3-9. Move Byte and Word Execution Times Destination Source (Ax) (Ax)+ -(Ax) ,Ax) ,Ax,Xi) (xxx).wl 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) (An) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 3-13...
Page 76 (xxx).l 2(1/0) 2(1/1) 2(1/1) 2(1/1) – – – ,PC) 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) – – ,PC,Xi) 3(1/0) 3(1/1) 3(1/1) 3(1/1) – – – #<xxx> 1(0/0) 2(0/1) 2(0/1) 2(0/1) – – – MCF5253 Reference Manual, Rev. 1 3-14 Freescale Semiconductor...
Page 77: Standard One Operand Instruction Execution Times
3(1/1) – andi.l #imm,Dx 1(0/0) – – – – – – – asl.l <ea>,Dx 1(0/0) – – – – – – 1(0/0) asr.l <ea>,Dx 1(0/0) – – – – – – 1(0/0) MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 3-15...
Page 78 6(1/0) 6(1/0) 6(1/0) 6(1/0) 12(1/0) 11(1/0) 9(0/0) mulu.w <ea>,Dx 4(0/0) 6(1/0) 6(1/0) 6(1/0) 6(1/0) 12(1/0) 11(1/0) 9(0/0) ≤ 4(0/0) ≤ 6(1/0) ≤ 6(1/0) ≤ 6(1/0) ≤ 6(1/0) muls.l <ea>,Dx – – – MCF5253 Reference Manual, Rev. 1 3-16 Freescale Semiconductor...
Page 79: Miscellaneous Instruction Execution Times
– 3(0/0) trap #imm – – – – – – – 15(1/2) trapf – 1(0/0) – – – – – – – trapf.w – 1(0/0) – – – – – – – MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 3-17...
Page 80: Branch Instruction Execution Times
5(1/0) – – – – – Table 3-15. BRA, Bcc Instruction Execution Times Forward Forward Backward Backward Opcode Taken Not Taken Taken Not Taken 2(0/0) – 2(0/0) – 3(0/0) 1(0/0) 2(0/0) 3(0/0) MCF5253 Reference Manual, Rev. 1 3-18 Freescale Semiconductor...
Page 81: Phase-Locked Loop And Clock Dividers
PLL is locked. • The MCF5253 has a new block added to the output of the PLL / Clock Dividers to provide glitch-free Dynamic Clock Switching. This allows dynamic switching of the clock rate being fed to the CPU core and the system bus. This new block is controlled by a new 32-bit register called the ClockRate Register.
Page 82: Pll Memory Map And Register Definitions
PLL Memory Map and Register Definitions The different settings for the PLL/clock module are summarized in Table 4-2. Table 4-1. PLL Memory Map Address Access Size Bits Name Description Reset MBAR2BAS + PllConfig PLL configuration register 0x02020088 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 83 – 0 PLL normal operation – PLLPWRDWN 1 Disable PLL to power-down mode 8–4 Input frequency (Fin) is divided by (PllDiv) to determine the PLL compare frequency. PLLDIV 3–2 VCXO output divider VCXOOUT MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 84 When frequency is CRIN/2 or CRIN/4, duty cycle is 50%. When frequency is CRIN/3, duty cycle is 33%. 8. Fcpu = FVCXOOUT / CPUDIV; Fcpu is the frequency the processor is running at. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 85: Pll Operation
Due to implementation of the block, some limits apply to the PLL block. These limitations are shown in Table 4-5. Table 4-5. PLL Electrical Limits Minimum Maximum Name Reason Frequency MHz Frequency MHz Fvcxo PLL limitations Fcpu Maximum operating frequency of device Fin/PLLDIV PLL limitations MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 86: Dynamic Clock Switching
Table 4-7. Table 4-7. PLLCR Bit Fields pllCR Config PLLCR[CLSEL] PllCR CRsel Audiosel AUDIO_CLOCK MCLK2 MCLK1 (Bits 30–28) (Bit 23) (Bit 22) CRIN CRIN CRIN/2 CRIN CRIN CRIN CRIN CRIN/2 CRIN/2 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 87: Reduced Power Mode
The device can be put in a low power Sleep mode, where all internal clocks and all on-chip functions are stopped. In Sleep mode, the only block still functional is the on-chip voltage regulator. All the other analog features are put in to low-power operation and all digital functions are stopped. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 88: Enter Sleep Mode
As a result, the user may select a 11.2896 MHz X-TAL as the CRIN and use the settings shown in Table 4-9. Table 4-9. Recommended PLL Settings X-Tal Freq Vcxo Vcxo CRSel Clock MHz 11.2896 11.2896 11.2896 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 89: Instruction Cache
EXTERNAL DATA[31:0] LOCAL ADDRESS BUS 12 4 3 LINE BUFFER DATA STORAGE BUFFER LINE ADDRESS FILL HIT DATA ‘127 TAG HIT LOCAL DATA BUS Figure 5-1. Instruction Cache Block Diagram MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 90: Instruction Cache Physical Organization
In this case, data accessed from the instruction cache is simply discarded and no external memory references are generated. If the address is not mapped into the SRAM space, the instruction cache handles the request in the normal fashion. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 91: Memory Reference Attributes
With the cache enabled as defined by CACR[31], a cacheable instruction fetch that misses in both the tag memory and the line-fill buffer generates a external fetch. The size of the external fetch is determined by MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 92 5-2. For this condition, the fill buffer is loaded and subsequent references can hit in the buffer, but the data is never loaded into the memory array. Table 5-2 shows the relationship between CACR bits 31 and 10 and the type of instruction fetch. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 93: Instruction Cache Memory Map And Register Definitions
Reset Address Name Width Description Access Value MOVEC with $002 CACR Cache Control Register $0000 MOVEC with $004 ACR0 Access Control Register 0 $0000 MOVEC with $005 ACR1 Access Control Register 1 $0000 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 94: Instruction Cache Register
If a given cache location is invalid, the contents of the line-fill buffer can be written into the memory array while CFRZ is asserted. 0 Normal operation 1 Freeze valid cache lines 26–25 Reserved, should be cleared. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 95 Table 5-5. External Fetch Size Based on Miss Address and CLNF Longword Address Bits CLNF[1:0] Line Line Line Longword Line Line Longword Longword Line Line Line Line Line Line Line Line MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 96: Access Control Registers
01 Match if supervisor mode 1x Match always. Ignore user/supervisor mode 12–7 Reserved, should be cleared. The Cache Mode bit defines the cache mode: 0 is cacheable, 1 is noncacheable. 0 Caching enabled 1 Caching disabled MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 97 The Write Protect bit defines the write-protection attribute. If the effective memory attributes for a given access select the WP bit, an access error terminates any attempted write with this bit set. 0 Read and write accesses permitted 1 Only read accesses permitted 1–0 Reserved, should be cleared. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 98 Instruction Cache MCF5253 Reference Manual, Rev. 1 5-10 Freescale Semiconductor...
Page 99: Static Ram (Sram)
Accesses from the SRAM module are not cached. Only SRAM1 can be accessed by the DMA controller of the MCF5253. SRAM0 and SRAM1 are made up of two memory arrays each consisting of 2048 lines, with 16 Bytes in each line.
Page 100 – – – – – – BA15 BA14 PRI1 PRI2 Reset – – – – – – – – – – – – – – – Figure 6-2. SRAM1 Base Address Register (RAMBAR1) MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 101 The valid bit. A hardware reset clears this bit. When set, this bit enables the SRAM module; otherwise, the module is disabled. 0 Contents of RAMBAR are not valid 1 Contents of RAMBAR are valid MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 102: Sram Initialization
ASn bits associated with instruction fetches can decrease power dissipation. Additionally, if the SRAM contains only instructions, masking data accesses can reduce power dissipation. Table 6-2 shows some examples of typical RAMBAR settings. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 103 Static RAM (SRAM) Table 6-2. Typical RAMBAR Setting Examples Data Contained in SRAM RAMBAR[7:0] Code Only Data Only Both Code And Data MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 104 Static RAM (SRAM) MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 105: Synchronous Dram Controller Module
Logic SD_CS0 State Machine SDRAS SDCAS Memory Block 0 Hit Logic SDWE DRAM Address/Control Register 0 SDUDQM (DACR0) SDLDQM DRAM Control BCLKE Register (DCR) Refresh Counter Figure 7-1. Synchronous DRAM Controller Block Diagram MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 106: Synchronous Operation
By running synchronously with the system clock, the SDRAM can (after an initial latency period) be accessed on every clock; 5-1-1-1 is a typical MCF5253 burst rate to SDRAM. NOTE Because the MCF5253 cannot have more than one page open at a time, it does not support interleaving. Table 7-1 lists common SDRAM commands.
Page 107: Dram Controller Signals In Synchronous Mode
DRAM read/write. Asserted for write operations and negated for read operations. SD_CS0 Chip Select for the SDRAM memory block connected to the MCF5253. BCLKE Synchronous DRAM clock enable. Connected directly to the CKE (clock enable) signal of SDRAMs. Enables and disables the clock internal to SDRAM.
Page 108: Dram Controller Registers
Field Description Synchronous operation. Selects synchronous or asynchronous mode. When in synchronous mode, the DRAM controller can be switched to ADRAM mode only by resetting the MCF5253. 0 Asynchronous DRAM. Default at reset. Do not use. 1 Synchronous DRAM Note: bit setting SO = 0 is a legacy mode. Do not use. First action must always be to set this bit.
Page 109: Dram Address And Control (Dacr0) (Synchronous Mode)
Each BA bit is compared with the corresponding address of the current bus cycle. If all unmasked bits match, the address hits in the associated DRAM block. 17–16 Reserved, should be cleared. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 110 SDRAM address pins. Because the SDRAM does not register this information, it doesn’t matter if the IMRS access is a read or a write. The DRAM controller clears IMRS after the command finishes. 0 Take no action 1 Initiate command MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 111: Dram Controller Mask Registers (Dmr0)
Write accesses to a write-protected DRAM region are compared in the chip select module for a hit. If no hit occurs, an external bus cycle is generated. If this external bus cycle is not acknowledged, an access exception occurs. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 112: General Synchronous Operation Guidelines
Specifically for the 256Mb devices the tables change due to the fact that we need to have a A24 address line. But with the MCF5253 A24 and A20 are shared on the same pin. This means that when we program the A20/A24 pin to be A24.
Page 113 A22. Bank addresses are then A23 and above. (Bank addresses need equal address during CAS and RAS phase). The remaining 3 D-RAM ras-only address lines are connected to A9, A11 and A12. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 114: Interfacing Example
The tables in the previous section can be used to configure the interface in the following example. To interface one 1M × 16-bit × 4 bank SDRAM component (8 columns) to the MCF5253, the connections would be as shown in Table 7-11.
Page 115 The next bus RCD. cycle is initiated sooner, but cannot begin an SDRAM cycle until the precharge-to- delay completes. ACTV MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 7-11...
Page 116: Continuous
Continuous page mode is identical to burst page mode, except that it allows the processor core to handle successive bus cycles that hit the same page without having to close the page. When the current bus cycle finishes, the MCF5253 core internal pipelined bus can predict whether the upcoming cycle will hit in the same page.
Page 117 A read requires WRITE data to be returned before the bus cycle can terminate. NOTE In continuous page mode, secondary accesses output the column address only. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 7-13...
Page 118: Auto-Refresh Operation
DCR[RTIM] is inserted before the next command is generated. In this example, the next bus cycle ACTV is initiated, but does not generate an SDRAM access until T is finished. MCF5253 Reference Manual, Rev. 1 7-14 Freescale Semiconductor...
Page 119: Self-Refresh Operation
DRAM controller. Figure 7-11 shows the SELFX self-refresh operation. BCLK SDRAS SDCAS SDWE SD_CS0 BCLKE (DCR[COC] = 0) First Self- Possible PALL SELF SELFX Refresh ACTV Active Figure 7-11. Self-Refresh Operation MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 7-15...
Page 120: Initialization Sequence
Although the MCF5253 DRAM controller supports bursting operations, it does not use the bursting features of the SDRAMs. Because the MCF5253 can burst operand sizes of 1, 2, 4, or 16 bytes long, the concept of a fixed burst length in the SDRAMs mode register becomes problematic. Therefore, the MCF5253 DRAM controller generates the burst cycles rather than the SDRAM device.
Page 121: Sdram Example
Figure 7-12. Mode Register Set ( ) Command SDRAM Example This example interfaces a Samsung K4S641633 1M x 16-bit x 4 bank SDRAM component to a MCF5253 operating at 80 MHz (40 MHz bus). Table 7-12 lists design specifications for this example.
Page 122: Sdram Interface Configuration
Synchronous DRAM Controller Module 7.6.1 SDRAM Interface Configuration To interface this component to the MCF5253 DRAM controller, use the connection table that corresponds to a 16-bit port size with 8 columns (Figure 7-14). Two pins select one of four banks when the part is functional.
Page 123: Dacr Initialization
Reserved. Don’t care. 13–12 Indicates a delay of data 1 cycle after CAS is asserted. CASL – Reserved. Don’t care. 10–8 Command bit is pin 19 and bank selects are 20 and up. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 7-19...
Page 124: Dmr Initialization
Bits 22 and 21 are set because they are used as bank selects; bit 20 is set because it controls the 1-MB boundary address. 15–9 – Reserved. Don’t care. Allow reads and writes – Reserved MCF5253 Reference Manual, Rev. 1 7-20 Freescale Semiconductor...
Page 125: Mode Register Initialization
When DACR[IMRS] is set, a bus cycle initializes the mode register. If the mode register setting is read on A[9:0] of the SDRAM on the first bus cycle, the bit settings on the corresponding MCF5253 address pins must be determined while being aware of masking requirements.
Page 126: Initialization Code
– (hex) Figure 7-17. Mode Register Mapping to MCF5253 A[31:0] Although A[31:20] corresponds to the address programmed in DACR0, according to how DACR0 and DMR0 are initialized, bit 19 must be set to hit in the SDRAM. Thus, before the mode register bit is set, DMR0[19] must be set to enable masking.
Page 127 #0xFF889260, d0 //Enable DACR0[IMRS]; DACR0[RE] remains set move.l d0, DACR0 move.l #0x00000000, d0 //Access SDRAM address to initialize mode register move.l d0, 0xFF801000 move.l #0x00740075, d0 //Set up DMR again move.l d0, DMR0 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 7-23...
Page 128 Synchronous DRAM Controller Module MCF5253 Reference Manual, Rev. 1 7-24 Freescale Semiconductor...
Page 129: Bus Operation
This chapter describes bus functionality, the bus control signals, and the bus cycles provided for data-transfer operations. Bus operation is defined for transfers initiated by the MCF5253 as a bus master and for transfers initiated by an alternate bus master. This chapter includes descriptions of the error conditions, bus arbitration, and the reset operation.
Page 130: Address Bus
NOTE For SDRAM access A24 is multiplexed with A20. A0 is not available on the address bus. As a result, the MCF5253 supports only 16-bit port size. 8.2.2 Read/Write Control The read/write (RW) control line will indicate that a bus cycle in progress is read or write. RW timing is same as address timing.
Page 131: Chip Selects
However it is possible to program BUFENB2 via the CS3 registers. 8.2.6 Output Enable The OE pin on the MCF5253 will be pulled low during any read cycle from a device selected by CS0, CS1, CS2, or CS4. Clock and Reset Signals...
Page 132: Reset In
Bus Operation 8.3.1 Reset In Asserting RSTI causes the MCF5253 processor to enter reset exception processing. When RSTI is recognized, the data bus is tri-stated, and OE, CS0, and CS1 are negated. See Section 8.7, “Reset Operation.” 8.3.2 System Bus Clock Output The BCLK output signal is generated by the internal PLL, and is the system bus clock output used as the bus timing reference by the external devices.
Page 133: Bus Cycle Execution
The bus supports byte, word, and longword operand transfers and uses a 16-bit data port. With the MCF5253, the port size of all memory must be programmed to 16 bits, the internal transfer termination must be enabled, and the number of wait states must be set for the external slave being accessed by programming the Chip-Select Control Registers (CSCRs) and the DRAM Controller Control Registers (DCRs).
Page 134: Read Cycle
This data is concurrent with TA, which is also sampled at the rising edge of the clock. During a write, the MCF5253 drives data from the rising clock edge at the end of the first clock to the rising clock edge at the end of the bus cycle.
Page 135 Name STATE 0 The read cycle is initiated in state 0 (S0). On the rising edge of BCLK, the MCF5253 places a valid address on the address bus and drives RW high, if it is not already high. STATE 1 The appropriate CS and OE are asserted on the falling edge of BCLK.
Page 136: Write Cycle
STATE 5 CS and OE are negated on the falling edge of state 5 (S5). The MCF5253 stops driving the address lines and RW on the rising edge of BCLK, terminating the read cycle. The external device must have its drive from the bus. The external device must stop driving the bus.
Page 137: Back-To-Back Bus Cycles
Description STATE 0 The write cycle is initiated in state 0 (S0). On the rising edge of BCLK, the MCF5253 places a valid address on the address bus and drives RW low, if it is not already low. STATE 1 The appropriate CS is asserted on the falling edge of BCLK.
Page 138: Burst Cycles
When burst read enable or burst write enable is asserted into the relevant chip select register, the MCF5253 will initiate burst cycles any time a transfer size is larger than the port size the MCF5253 is transferring to. A line transfer to a 16-bit port would constitute a burst cycle of eight words of data.
Page 139 Figure 8-8. Line Read Burst (one wait cycle) Figure 8-9. Line Read Burst (no wait cycles) Line Write Bus Cycles MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 8-11...
Page 140 (on the rising edge of S6). Each subsequent pipelined write data burst will be a single cycle. CS remains asserted throughout the burst transfer. MCF5253 Reference Manual, Rev. 1 8-12 Freescale Semiconductor...
Page 141: Misaligned Operands
Figure 8-13. Line Write Burst-Inhibited Misaligned Operands All MCF5253 data formats can be located in memory on any byte boundary. A byte operand is properly aligned at any address; a word operand is misaligned at an odd address; and a longword is misaligned at an address that is not evenly divisible by four.
Page 142: Reset Operation
Figure 8-15. Misaligned Word Transfer Reset Operation The MCF5253 processor supports one type of reset which resets the entire MCF5253: the external master reset input (RSTI). To perform a master reset, an external device asserts the reset input pin (RSTI). When power is applied to the system, external circuitry should assert RSTI for a minimum of 16 CRIN cycles after Vcc is within tolerance.
Page 143: Software Watchdog Reset
If at power-on reset, the MCF5253 is configured to boot from external memory connected to CS0. Then CS0 is configured to address the external boot ROM / Flash. The configuration for CS0 at this time is hard-wired inside the MCF5253.
Page 144 Bus Operation MCF5253 Reference Manual, Rev. 1 8-16 Freescale Semiconductor...
Page 145: System Integration Module (Sim)
This chapter describes the operation, memory map and register descriptions of the System Integration Module (SIM) registers, including the interrupt controller and system-protection functions for the MCF5253 processor. The SIM provides overall control of the internal and external buses and serves as the ®...
Page 146: Sim Register Memory Map
Primary interrupt Pending Reg MBAR + $044 Primary Interrupt Mask Reg MBAR + $04C Primary Interrupt Control Reg ICR0 ICR1 ICR2 ICR3 MBAR + $050 Primary Interrupt Control Reg ICR4 ICR5 ICR6 ICR7 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 147: Sim Module Programming Registers
At system reset, the MBAR valid bits (MBAR[0], MBAR2[0]) are cleared to prevent incorrect reference to resources before the MBAR or MBAR2 are written. The remainder of the MBAR and MBAR2 bits are MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 148 0 Alternate master access allowed 1 Alternate master access masked Mask CPU Space and Interrupt Acknowledge Cycle. 0 IACK cycle mapped to MBAR space 1 IACK cycle not responded to by MBAR peripherals MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 149 The Base Address field defines the base address for a 1024 Mbyte address range. If V-bit in MBAR2 is set, address range Base Address to BaseAddress + $3FFF FFFF are mapped to MBAR2 space, and cannot be used for MBAR, SDRAM or Chip Select. 29–8 Reserved, should be cleared. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 150: Device Id Register
Figure 9-3. DeviceID Register (DeviceID) Interrupt Interface Registers For legacy reasons, there are two interrupt controllers on the MCF5253. This section provides the programming of the two interrupt controller registers and their register descriptions. The primary interrupt controller is centralized, and services the following: •...
Page 151: Primary Interrupt Controller Registers
ICR11 Reserved – – Primary interrupts are programmed to a level and priority. All primary interrupts have a unique Interrupt Control Register (ICR). There are 28 possible priority levels, for the primary interrupts. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 152 Higher Table 9-8 shows all possible primary source priority schemes for the MCF5253. The interrupt source in this table can be any internal interrupt source programmed to the given level and priority. For example, assume that two internal interrupt sources were programmed to IL[2:0] =110, one having a priority of IP[1:0] = 01 and one having a priority of IP[1:0] = 10.
Page 153 Internal Module Internal Module Internal Module NOTE Multiple internal modules should not be assigned to the same interrupt level and same interrupt priority when configuring the ICR registers. This can cause erratic chip behavior. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 154: Interrupt Mask Register
An interrupt can be masked by setting the corresponding bit in the IMR and enable an interrupt by clearing the corresponding bit in the IMR. 7–0 Reserved. 9.4.1.2 Interrupt Pending Register The IPR makes visible the interrupt sources that have an interrupt pending. MCF5253 Reference Manual, Rev. 1 9-10 Freescale Semiconductor...
Page 155: Secondary Interrupt Controller Registers
INTPRI4 Interrupts 24–31 priority MBAR2 + $150 INTPRI5 Interrupts 32–39 priority MBAR2 + $154 INTPRI6 Interrupts 40–47 priority MBAR2 + $158 INTPRI7 Interrupts 48–55 priority MBAR2 + $15C INTPRI8 Interrupts 56–63 priority MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 9-11...
Page 156: Interrupt Level Selection
23 is e.g. INTBASE + 23. The secondary interrupt controller will generate vector numbers INTBASE to INTBASE + 63 for its 64 interrupts. Address MBAR2 + $16B Access: User read/write BASE[7] BASE[6] BASE[5] BASE[4] BASE[3] BASE[2] BASE[1] BASE[0] Reset Figure 9-7. INTBase Register MCF5253 Reference Manual, Rev. 1 9-12 Freescale Semiconductor...
Page 157: Spurious Vector Register
– – – – – Figure 9-8. Spurvec Register 9.4.2.4 Secondary Interrupt Sources The 64 secondary interrupts used by the MCF5253 modules are provided in Table 9-14. Table 9-14. Secondary Interrupt Sources Interrupt Interrupt Name Module Description A to D convertor...
Page 158 U channel transmit register is empty UCHANTXUNDER AUDIO U channel transmit register underrun UCHANTXNEXTFIRST AUDIO U channel transmit register next byte will be first IEC958-1 U/Q BUFFER ATTENTION AUDIO IEC 958 -1 U/Q channel buffer full interrupt MCF5253 Reference Manual, Rev. 1 9-14 Freescale Semiconductor...
Page 159 Interrupt set on falling edge of shift_busy_2 intClear SHIFTBUSY2RISE Interrupt set on rising edge of shift_busy_2 intClear INTLEVEL2FALL Interrupt set on falling edge of int_level_2 intClear INTLEVEL2RISE Interrupt set on rising edge of int_level_2 intClear MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 9-15...
Page 160: Software Interrupts
9.4.3 Software Interrupts The MCF5253 supports four software interrupts. These interrupts are activated by writing a 1 to an ExtraInt register bit. When active, the interrupts can generate a normal interrupt exception to the ColdFire processor. The interrupt exception is only generated if the corresponding level register interrupt mask is higher than the current processor interrupt mask.
Page 161: System Protection And Reset Status Registers
SYPCR is set and the software watchdog timer times out, a hardware reset occurs. 9.5.2 Software Watchdog Timer The Software Watchdog Timer (SWT) prevents system lockup if the software become trapped in loops with no controlled exit. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 9-17...
Page 162 SWT IACK CYCLE 2 SWTAVAL IS SET TO ‘1’ IF SWT TA SIGNAL is ASSERTED. Figure 9-10. MCF5253 Unterminated Access Recovery When the SWT times out and SWRI register bit is programmed for a software reset, an internal reset will be asserted, and the SWTR register bit will be set in the RSR.
Page 163: System Protection Control Register
ICR0. 1 SWT causes soft reset to be asserted for all modules of the part. Software Watchdog Prescalar 0 SWT clock not prescaled. 1 SWT clock prescaled by a value of 8192. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 9-19...
Page 164: Software Watchdog Interrupt Vector Register
SWT-generated interrupt. The following register illustrates the SWIVR programming model. The SWIVR is an 8-bit supervisor write-only register. This register is set to the uninitialized vector $0F at system reset. MCF5253 Reference Manual, Rev. 1 9-20 Freescale Semiconductor...
Page 165: Software Watchdog Service Register
The MPARK register determines the default bus master arbitration applied between internal transfers. This arbitration is needed because there are two bus masters inside the MCF5253. One is the CPU, the other is the DMA unit. Both can access internal registers within the MCF5253 peripherals.
Page 166: Internal Arbitration Operation
Then when the DMA asserts its internal bus request signal, it will then have priority. MCF5253 Reference Manual, Rev. 1 9-22...
Page 167: Park Register Bit Configuration
Table 9-24. Park on Current Master Priority (PARK[1:0] = 11) Current Highest Current Lowest Next Arbitration Cycle Highest Next Arbitration Cycle Lowest Priority Master Priority Master Priority Master Priority Master Core Core Core Core MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 9-23...
Page 168: General Purpose I/Os
0 DMA BCRs function as 16-bit counters. 1 DMA BCRs function as 24-bit counters. General Purpose I/O The MCF5253 has up to 57 programmable general-purpose outputs and up to 60 programmable general-purpose inputs. Two groups of 32-bit registers control these GPIOs. Table 9-26. General Purpose I/O...
Page 169: General Purpose Inputs
GPIO-READ(13) EBUIN2/SCLKOUT/GPIO13 GPIO1-READ(45) TXD0/GPIO45 GPIO-READ(12) TA/GPIO12 GPIO1-READ(44) SDA1/RXD1/GPIO44 GPIO-READ(11) MCLK1/GPIO11 GPIO1-READ(43) LRCK3/AUDIOCLK/GPIO43 GPIO-READ(10) SCL1/TXD1/GPIO10 GPIO1-READ(42) SDA0/SDATA3/GPIO42 GPIO-READ(9) none GPIO1-READ(41) SCL0/SDATA1_BS1/GPIO41 GPIO-READ(8) SDATAI3/GPIO8 GPIO1-READ(40) BCLK/GPIO40 GPIO-READ(7) none GPIO1-READ(39) SDCAS/GPIO39 GPIO-READ(6) EF/RXD2/GPIO6 GPIO1-READ(38) SDWE/GPIO38 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 9-25...
Page 170: General Purpose Input Interrupts
GPIO-INT-EN is set, an interrupt will be made pending on the secondary interrupt controller. NOTE The registers GPIO-INT-STAT, GPIO-INT-CLEAR and GPIO-INT-EN also control some audio interrupts. Set the GPIO_FUNCTION register bit to 1 or 0 for interrupts, as applicable. MCF5253 Reference Manual, Rev. 1 9-26 Freescale Semiconductor...
Page 171: General Purpose Outputs
Figure 9-15. The primary output function of the pin is the SCLK3 function it can be configured as a general-purpose output (GPIO35) by setting its controlling bit (35) in the GPIO1-FUNCTION register. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 9-27...
Page 172 Bit Number IDE_DIOR/GPIO31 BCLKE/GPIO63 BUFENB2/GPIO30 none BUFENB1/GPIO29 none CS1/QSPICS3/GPIO28 SD_CS0/GPIO60 QSPIDOUT/SFSY/GPIO27 SDRAS/GPIO59 RCK/QSPIDIN/QSPI ADOUT/SCLK4/GPIO58 DOUT/GPIO26 QSPICLK/SUBR/GPIO25 none QSPICS2/MCLK2/GPIO24 none LRCK2/GPIO23 none SCLK2/GPIO22 A23/GPO54 WAKEUP/GPIO21 SDUDQM/GPO53 SCLK1/GPIO20 SDLDQM/GPO52 LRCK1/GPIO19 PSTCLK/GPIO51 SDATAO1/TOUT0/GPIO18 PST0/GPIO50 SDATAI1/GPIO17 PST1/GPIO49 MCF5253 Reference Manual, Rev. 1 9-28 Freescale Semiconductor...
Page 173: Multiplexed Pin Configuration
IDE_DIOW/GPIO32 Multiplexed Pin Configuration The MCF5253 has a number of pins which are multiplexed with both a primary function, a secondary function, and a GPIO function (triple functionality). Two pins have 3 major functions (a primary and two secondary functions). Two pins also have their multiplexed functions selected at power-on reset via external pull-up / pull-down resistors.
Page 174 0 SCL0 SCL0/SDATA1_BS1/GPIO41 1 SDATA1_BS1 14–13 0: 0 DDATA0 K10 13 + 14 DDATA0/CTS1/SDATA0_SDIO1/GPIO1 0: 1 SDATA0SDIO1 1: 0 CTS1 1: 1 CTS1 0 EBUIN3 EBUIN3/CMD_SDIO2/GPIO14 1 CMDSDIO2 0 EBUIN2 EBUIN2/SCLKOUT/GPIO13 1 SCLKOUT MCF5253 Reference Manual, Rev. 1 9-30 Freescale Semiconductor...
Page 175 Note: QSPIDOUT is selected when CS3 is active, otherwise QSPIDIN is enabled. 0 QSPICLK QSPICLK/SUBR/GPIO25 1 SUBR 0 QSPICS2 QSPICS2/MCLK2/GPIO24 1 MCLK2 0 QSPICS1 QSPICS1/EBUOUT2/GPIO16 1 EBUOUT2 0 QSPICS0 QSPICS0/EBUIN4/GPIO15 1 EBUIN4 0 A20 A20/A24 1 A24 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 9-31...
Page 176 System Integration Module (SIM) MCF5253 Reference Manual, Rev. 1 9-32 Freescale Semiconductor...
Page 177: Chip Select Module
10.2 Chip Select Signals The MCF5253 provides three programmable chip selects that can directly interface with SRAM, EPROM, EEPROM, and peripherals. Chip select CS2 provides separate read and write strobes for an AT-bus peripheral interface, and uses IORDY signalling to insert wait states.
Page 178: Cs1/Qspi_Cs3/Gpio28
Buffer Enable – BUFENB1 and BUFENB2 Signals The BUFENB1/GPIO29 and BUFENB2/GPIO30 signals are intended to enable bus buffers which will provide isolation / buffering between the MCF5253 high speed memory bus and additional external memory mapped devices. BUFENB1 is always active on CS0.
Page 179: Chip Select Operation
Port Sizing The MCF5253 only supports a 16-bit wide port size (PS). The size of the port controlled by a chip-select is programmable. The port size is specified by the (PS) bits in the chip select control register (CSCR). It should always be programmed as a 16-bit wide port.
Page 180: Global Chip-Select Operation
Table 10-2. Memory Map of Chip-Select Registers Address Name Width Description Reset Access MBAR + 0x80 CSAR0 Chip-Select Address Register–Bank 0 Uninitialized MBAR + 0x84 CSMR0 Chip-Select Mask Register–Bank 0 Uninitialized (except V = 0) MCF5253 Reference Manual, Rev. 1 10-4 Freescale Semiconductor...
Page 181: Chip Select Module Registers
The various chip select registers in the module are described in this section. 10.4.2.1 Chip Select Address Register The Chip Select Address registers (CSARx) determine the base address of the corresponding chip select pin. These read/write registers are 32-bit in length. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 10-5...
Page 182: Chip Select Mask Register
Each CSMR is a 32-bit read/write control register that physically resides in the chip select module. With the exception of bit 0 (V-bit), which is initialized to 0 on reset, all other bits in CSMRx are uninitialized by reset. MCF5253 Reference Manual, Rev. 1 10-6 Freescale Semiconductor...
Page 183 CSAR that has this bit set results in the appropriate chip select not being selected. No exception occurs. 0 Both read and write accesses are allowed. 1 Only read access is allowed. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 10-7...
Page 184: Chip Select Control Register
Its operation differs from the other external chip select outputs following a system reset. Address MBAR + 0x8A (CSCR0) Access: User read/write WS3 WS2 WS1 WS0 BSTR BSTW Reset – – – – – – Figure 10-3. Chip Select Control Register (CSCR0) MCF5253 Reference Manual, Rev. 1 10-8 Freescale Semiconductor...
Page 185 0 Break data larger than the specified port size into individual non-burst writes that equals the specified port size. For example, a longword write to an 16-bit port would be broken into two individual word writes. 1 Enables burst write of data larger than the specified port size. 2–0 Reserved. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 10-9...
Page 186: Code Example
#$0D80,D0;CSCR0 = 3 wait states, AA=1, PS=16-bit, BEM=0, move.w D0,CSCR0 ;BSTR=0, BSTW=0 ; Program Chip Select 0 Mask Register (validate chip selects) move.l #001F0001,D0 ;Address range from $00800000 to $009FFFFF move.l D0,CSMR0;WP,EM,C/I,SC,SD,UC,UD=0; V=1 MCF5253 Reference Manual, Rev. 1 10-10 Freescale Semiconductor...
Page 187: General Purpose Timer Modules
Chapter 11 General Purpose Timer Modules This chapter describes the configuration and operation of the two general purpose timer modules (Timer0 and Timer1) in the MCF5253. The memory map, register descriptions, and example initialization code are also provided. 11.1 Timer Module Overview The MCF5253 incorporates two independent, general-purpose 16-bit timers.
Page 188: Timer Signal Output
Users can configure the timer to count until it reaches a reference value at which time it either starts a new time count immediately or continues to run. The free run/restart (FRR) bit of the TMR selects either mode. MCF5253 Reference Manual, Rev. 1 11-2...
Page 189: Configuring The Timer For Output Mode (Timer0)
1; the value 11111111 divides the clock by 256. Prescalar value = $[PS7 – PS0] + 1 7–6 These bits have no function and should be set to 00. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 11-3...
Page 190: Timer Reference Registers (Trr0, Trr1)
TCN should be incremented again. Thus, the reference register is matched after (TRR+1) time intervals. Address MBAR+$144 Access: Supervisor or User read/write MBAR+$184 REFERENCE COMPARE VALUE (REF15–REF0) Reset Figure 11-3. Timer Reference Register (TRRn) MCF5253 Reference Manual, Rev. 1 11-4 Freescale Semiconductor...
Page 191: Timer Counters (Tcn0, Tcn1)
If a one is read from the Output Reference Event bit, the counter has reached the TRR value. The ORI bit in the TMR enables the interrupt request caused by this event. Writing a one to this bit will clear the event condition. Not applicable MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 11-5...
Page 192: Timer Initialization Example Code
Timer Initialization Example Code There are two timers on the MCF5253. With a 70 MHz clock, the maximum period is 3.83 seconds and a resolution of 14.3 ns. The timers can be free running or count to a value and reset. The following examples set up the timers: Timer0 will count to $AFAF, toggle its output, and reset back to $0000.
Page 193: Analog To Digital Converter (Adc)
The ADC block diagram and external circuit example is shown in the below figure. Figure 12-1. ADC Block Diagram and External Components 12.2 External Signal Description The ADC has six muxed inputs with the following pin names. 1. ADIN0/GPI52 2. ADIN1/GPI53 3. ADIN2/GPI54 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 12-1...
Page 194: Adc Memory Map And Register Definitions
Address MBAR2 + 0x402 (ADCONFIG) Access: User read/write INTCLR Source Select INTEN ADOUT_DRIVE ADCLK_SEL Reset – – – – – – – – – – – – – Figure 12-2. AD Configuration Register (ADconfig) MCF5253 Reference Manual, Rev. 1 12-2 Freescale Semiconductor...
Page 195: Ad Value Register (Advalue)
Address MBAR2 + 0x406 (ADVALUE) Access: User read-only ADVALUE Reset – – – – – – – – – – – – – – – – Figure 12-3. AD Value Register (ADvalue) MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 12-3...
Page 196: Functional Description
K is a constant. If K is small, the ripple on the comparator input will be quite large, and there will be some mis-measurement because the average value on both comparator pins is not equal. If K is small, MCF5253 Reference Manual, Rev. 1 12-4...
Page 197 When reading the same channel, it is not necessary to ignore every other measurement. We therefore recommend to use R = 33kΩ, C = 10nF with ADCLK = BUSCLK/256. This should produce good results for typical system clock frequencies between 30 MHz and 70 MHz. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 12-5...
Page 198 Analog to Digital Converter (ADC) MCF5253 Reference Manual, Rev. 1 12-6 Freescale Semiconductor...
Page 199: Ide And Flash Media Interface
13.1 IDE and SmartMedia Overview The MCF5253 memory bus allows connection of an IDE hard disk drive or SmartMedia flash card with a minimum of external hardware. Figure 13-1 shows the bus set-up for the MCF5253 device.
Page 200 Figure 13-1. Bus Setup with IDE and SmartMedia Interface In this example there is only one buffer between the MCF5253 memory bus and the IDE / SmartMedia interface. The SDRAM (if used) is connected directly to the memory bus along with the Flash memory (if used).
Page 201: Buffer Enables Bufenb1, Bufenb2, And Associated Logic
IDE_DIOR, IDE_DIOW—active-low IDE bus read and write strobe can also be used to implement a SmartMedia interface. • IDE_IORDY—active-high “ready” indication from IDE device to MCF5253. NOTE Either of the buffer enables can be programmed to be active on CS1 or CS2 The extra bus signals, and their configuration are detailed in the following section.
Page 202 11 3 clock post drive 0 BUFENB1 inactive on CS1 cycles bufen1cs1en 1 BUFENB1 active on CS1 cycles 0 BUFENB1 inactive on IDE_DIOR, IDE_DIOW cycles bufen1cs2en 1 BUFENB1 active on IDE_DIOR, IDE_DIOW cycles MCF5253 Reference Manual, Rev. 1 13-4 Freescale Semiconductor...
Page 203: Generation Of Ide_Dior And Ide_Diow
IDE_DIOR and IDE_DIOW are created by gating CS2 with RW. IDE_DIOR is programmable to go active on write cycles. It therefore can be used as an extra Chip Select (CS2), if required. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 13-5...
Page 204: Cycle Termination On Cs2 (Ide_Dior, Ide_Diow)
Cycle Termination on CS2 (IDE_DIOR, IDE_DIOW) Dedicated logic has been added to the MCF5253 to allow IDE compliant cycles on the bus. The logic can generate the transfer acknowledge (TA) signal for CS2 access. The manner in which the TA signal is generated is programmable using the IDE config 2 register, and is compatible with IDE/SmartMedia requirements.
Page 205: Smartmedia Interface Setup
The SmartMedia block must be connected to the bus as follows: • RE input connect to MCF5253 IDE_DIOR output • WE input connect to MCF5253 IDE_DIOW output • D0–7 connect to MCF5253 data bus wires 31–24 • CE connect to always low • ALE connect to general purpose output •...
Page 206: Smartmedia Timing
A SmartMedia interface and an IDE interface cannot be implemented simultaneously in the same hardware application as they both share the same read and write strobe signals on the MCF5253. To set up the SmartMedia interface perform the following tasks.
Page 207: Setting Up The Ide Interface
3. Program IDECONFIG2 register. Program this register as follows: — TA enable 2 = ‘1’. — IDE_IORDY enable 2 = ‘1’ if IDE_IORDY is connected from the IDE drive to the MCF5253 chip. — IDE_IORDY enable 2 = ‘0’ if IDE_IORDY wait handshake is not used.
Page 208: Ide Timing Diagram
= time difference between path from IORDY and from read data Read data in device must be valid 3 clocks after IORDY going high. CS2POST CS2POST > t9 To meet this timing, typical value for cs2post is 10 MCF5253 Reference Manual, Rev. 1 13-10 Freescale Semiconductor...
Page 209: Flash Media Interface
Flash Media Interface The MCF5253 is capable of interfacing with Sony Memory Stick and Multi-Media Card (MMC) / Secure Digital (SD) flash cards. The interface can handle one of them at any given time, but not both at the same time.
Page 210: Flash Media Interface Memory Map And Register Definitions
– – – – – – CLOCKCOUNT1 CLOCKCOUNT0 Reset – – – – – – – – – – – – – – – – Figure 13-9. Flash Media Configuration Register (FLASHMEDIACONFIG) MCF5253 Reference Manual, Rev. 1 13-12 Freescale Semiconductor...
Page 211: Flash Media Interface Operation
(to clock generator) CommandBits Interface BS (MemoryStick mode only) bitCounter Shift Register shift_busy Serial data int_level crc_is_0 TxBufferEmpty RxBufferFull RcvBufferFull loadTxShiftReg storeRcvShiftReg Figure 13-10. Shift Register MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 13-13...
Page 212 CRC_IS_0 After a read transmission is completed, this signal indicates if the packet CRC was 0 or not. • BITCOUNTER. This counter indicates the number of bits still to be exchange with the Flash Media card. MCF5253 Reference Manual, Rev. 1 13-14 Freescale Semiconductor...
Page 213: Flash Media Command Registers In Memory Stick Mode
Address MBAR2 + 0x464 Access: User read/write WIDE SEND NEXT CMDCODE SHIFT Reset – – – – – – – – – BITCOUNTER Reset Figure 13-12. Flash Media Command Register 1 (FLASHMEDIACMD) (Secure Digital Mode) MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 13-15...
Page 214: Flash Media Command Register 2 In Secure Digital Mode
0 Do not drive data line DRIVEDATA 1 Start driving data line after command transmission end 0 Do not drive command line DRIVECMD 1 Start driving command line after receiving card status response MCF5253 Reference Manual, Rev. 1 13-16 Freescale Semiconductor...
Page 215: Flash Media Data Registers
Figure 13-14. Flash Media Data Registers 1 & 2 (FLASHMEDIACMD) (Secure Digital Mode) Table 13-13. Flash Media Data Registers 1 & 2 Field Descriptions Field Description 31–0 Read receive data from this register. RCVBUFFERREG 31–0 Data written to this register will be transmitted. TXBUFFERREG MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 13-17...
Page 216: Flash Media Status Register
FLASHMEDIAINTSTAT allows the viewing of pending interrupts. Register FLASHMEDIAINTEN allows the enabling of interrupts (‘1’ = enabled, ‘0’ = disabled). Some interrupts can be cleared by writing a ‘1’ to the corresponding bit of the FLASHMEDIAINTCLEAR register. MCF5253 Reference Manual, Rev. 1 13-18 Freescale Semiconductor...
Page 217 Interrupt set on rising edge of shift_busy_2 IntClear SHIFTBUSY2RISE Interrupt set on falling edge of shift_busy_2 IntClear SHIFTBUSY2FALL Interrupt set on rising edge of int_level_1 IntClear INTLEVEL1RISE Interrupt set on falling edge of int_level_1 IntClear INTLEVEL1FALL MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 13-19...
Page 218: Flash Media Interface Operation In Memory Stick Mode
If there is a buffer full or a buffer empty on one interface, the system will freeze the outgoing SCLK signal, which causes the second interface to go into a wait-state as well. MCF5253 Reference Manual, Rev. 1 13-20 Freescale Semiconductor...
Page 219: Reading Data From The Memory Stick
In the timing diagram, the assumption is made that the processor reads the full receive buffer register before the next 32 bits are received. If this is not the case, the Flash Media interface will stop the outgoing sclk clock, which prevents data overrun. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 13-21...
Page 220: Writing Data To The Memory Stick
WRITE TO CMD REGISTER bitcounter BITCOUNTER BS_PIN bs_pin SDIO_OUT sdio_out SDIO_IN sdio_in SHIFT_BUSY shift_busy Memory Stick interface timing diagram for cmd_reg(19:16) = 0010 (Write data to stick) Figure 13-20. Writing Data to Memory Stick Timing MCF5253 Reference Manual, Rev. 1 13-22 Freescale Semiconductor...
Page 221: Interrupt From Memory Stick
All interactions to the Secure Digital (SD) card can be broken down into a number of cascaded elementary operations. There are three elementary operations in SD mode: • Send command to card MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 13-23...
Page 222: Send Command To Card
CRC must be inserted by software. A number of bits/bytes/longwords corresponding with RESPBITCOUNT must be read from FLASHMEDIADATA2 during the response phase. All words, except the first word, contain 32 bits of MCF5253 Reference Manual, Rev. 1 13-24 Freescale Semiconductor...
Page 223: Write Data To Card
Figure 13-25. Writing to Card Without Busy The write sequence sends out a packet on the DATA line, receives a CRC STATUS response from the card, and then looks for a potential busy. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 13-25...
Page 224 This is done in hardware. The CRC can be checked via bit 0 in register FLASHMEDIASTATUS after packet read. All words, except the first word read from FLASHMEDIADATA1 contain 32 bits of data. The first word contains the remainder. Data in the first word is right-justified. MCF5253 Reference Manual, Rev. 1 13-26 Freescale Semiconductor...
Page 225: Commonly Used Commands In Sd Mode
((FLASHMEDIASTATUS & 8)!= 0) RESPBITCOUNT = 46 or 134 /* depends on command */ FLASHMEDIACMD2 = RESPBITCOUNT; while(RESPBITCOUNT > 0) if(FLASHMEDIADATA2 full) read data from FLASHMEDIADATA2 RESPBITCOUNT:= RESPBITCOUNT - 32; MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 13-27...
Page 226: Send Command To Card (Receive Multiple Data Blocks And Status)
FLASHMEDIACMD1 = 0x040000 + dataBitCount + wide_shift_mask; if(FLASHMEDIADATA2 full) read FLASHMEDIADATA2 RESPBITCOUNT = RESPBITCOUNT - 32; if(FLASHMEDIADATA1 full) read FLASHMEDIADATA1 dataBitCount = dataBitCount - 32; if((FLASHMEDIASTATUS & 1) == 1) CRC OK!. BLOCKCOUNT = BLOCKCOUNT - 1; MCF5253 Reference Manual, Rev. 1 13-28 Freescale Semiconductor...
Page 227: Send Command To Card (Write Multiple Data Blocks)
BLOCKCOUNT:= <N> while(BLOCKCOUNT > 0) -- start transmission of new block DATABITCOUNT = <blockLen> + crcLen; FLASHMEDIACMD1 = 0x260000 + dataBitCount + wide_shift_mask; while(DATABITCOUNT > 0) if(FLASHMEDIADATA1 empty) write data to FLASHMEDIADATA1 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 13-29...
Page 228 On falling edge of busy, INTLEVEL1FALL event will occur. During busy, (FLASHMEDIASTATUS & 4) == 4 wait until ((FLASHMEDIASTATUS & 4) == 0) /* busy end */ FLASHMEDIACMD1 = 0; BLOCKCOUNT:= BLOCKCOUNT - 1; FLASHMEDIACMD2 = 0; MCF5253 Reference Manual, Rev. 1 13-30 Freescale Semiconductor...
Page 229: Dma Controller
Chapter 14 DMA Controller The direct memory access controller (DMAC) of the MCF5253 quickly and efficiently moves blocks of data with minimal processor overhead. The DMA module, shown in Figure 14-1, provides four channels that allow byte, word, or longword data transfers. These transfers are dual address to on-chip devices; such as the ATA, UART, SDRAM controller, and audio module.
Page 230: Dma Request
DMAROUTE register. Each DMA channel is programmable individually. The internal signals are asserted by a peripheral device to request an operand transfer between that peripheral and memory. MCF5253 Reference Manual, Rev. 1 14-2 Freescale Semiconductor...
Page 231: Dma Module Overview
3. Channel termination step—This occurs after operation is complete. The channel indicates the status of the operation in the channel status register. MEMORY MEMORY- MAPPED PERIPHERAL MEMORY MEMORY- MAPPED PERIPHERAL Figure 14-2. Dual Address Transfer MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 14-3...
Page 232: Dma Memory Map And Register Definitions
Figure 14-3. DMAroute Register Table 14-3. DMAroute Register Field Descriptions DMAroute Bits Field Name DMA Channel 31–24 DMA3REQ (7:0) DMA3 23–16 DMA2REQ (7:0) DMA2 15–8 DMA1REQ (7:0) DMA1 7–0 DMA0REQ (7:0) DMA0 MCF5253 Reference Manual, Rev. 1 14-4 Freescale Semiconductor...
Page 233: Source Address Register
DMA0: audio source 2 audio 14.4.2 Source Address Register The source address register (SAR) is a 32-bit register containing the address from which the DMA controller module requests data during a transfer. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 14-5...
Page 234: Destination Address Register
DAR31 DAR30 DAR29 DAR28 DAR27 DAR26 DAR25 DAR24 DAR23 DAR22 DAR21 DAR20 DAR19 DAR18 DAR17 DAR16 Reset DAR15 DAR14 DAR13 DAR12 DAR11 DAR10 DAR9 DAR8 DAR7 DAR6 DAR5 DAR4 DAR3 DAR2 DAR1 DAR0 Reset Figure 14-5. Destination Address Register (DAR) MCF5253 Reference Manual, Rev. 1 14-6 Freescale Semiconductor...
Page 235: Byte Count Register
DMA Controller NOTE The MCF5253 on-chip DMAs must be careful when transferring data to cacheable memory since the on-chip DMAs do not maintain cache coherency with the MCF5253 instruction cache. 14.4.4 Byte Count Register The byte count register (BCR) is a 24-bit register containing the number of bytes remaining to be transferred for a given block.
Page 236: Dma Control Register
BCR24BIT in the MPARK register in the SIM module, the DMA control register looks slightly different. Specifically, the AT bit (DCR[15]) is included when BCR24BIT = 1, providing greater flexibility in DMA transfer acknowledge. MCF5253 Reference Manual, Rev. 1 14-8 Freescale Semiconductor...
Page 237 If the DSIZE bits indicate a larger transfer size than SSIZE, then the destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto- alignment is enabled, the appropriate address register increments, regardless of the state of DINC or SINC. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 14-9...
Page 238 The destination increment bit determines whether the destination address increments after each successful transfer. DINC 0 No change to the DAR after a successful transfer. 1 The DAR increments by 1, 2, 4, or 16; depending upon the size of the transfer. MCF5253 Reference Manual, Rev. 1 14-10 Freescale Semiconductor...
Page 239: Dma Status Register
DMA status register. Address MBAR + $310 Access: User read/write MBAR + $350 MBAR + $390 MBAR + $3D0 DONE Reset – – Figure 14-9. DMA Status Register (DSR) MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 14-11...
Page 240: Dma Interrupt Vector Register
Address MBAR + $314 Access: User read/write MBAR + $354 MBAR + $394 MBAR + $3D4 INTERRUPT VECTOR BITS Reset Figure 14-10. DMA Interrupt Vector Register (DIVR) MCF5253 Reference Manual, Rev. 1 14-12 Freescale Semiconductor...
Page 241: Transfer Request Generation
If the SINC bit (DCR[22]) is set, then the SAR increments by the appropriate number of bytes upon a successful read cycle. When the appropriate number of read cycles completes successfully, the DMA initiates the write portion of the transfer. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 14-13...
Page 242: Dual-Address Write
Before starting a block transfer operation, the channel registers must be initialized with information describing the channel configuration, request-generation method, and data block. This initialization is accomplished by programming the appropriate information into the channel registers. MCF5253 Reference Manual, Rev. 1 14-14 Freescale Semiconductor...
Page 243: Channel Prioritization
If any fields in the DCR are modified while the channel is active, that change is effective immediately. To avoid any problems with changing the setup for the DMA channel, a 1 should be written to the DONE bit in the DSR to stop the DMA channel. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 14-15...
Page 244: Data Transfer
BWC, the DMA bus request negates until termination of the bus cycle. Should a request be pending, the arbiter may then choose to switch the bus to another master. If auto-alignment is enabled (DCR[AA] = 1), MCF5253 Reference Manual, Rev. 1 14-16...
Page 245: Channel Termination
DSR to determine if the transfer terminated successfully or with an error. The DONE bit of the DSR is then written with a 1 to clear the interrupt, along with clearing the DONE and error bits. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 14-17...
Page 246 DMA Controller MCF5253 Reference Manual, Rev. 1 14-18 Freescale Semiconductor...
Page 247: Uart Modules
INTERRUPT CONTROL LOGIC Figure 15-1. UART Block Diagram 15.1 UART Module Features The MCF5253 contains three independent UART modules. Features of each UART module include the following: • UART clocked by the system clock • Full duplex asynchronous receiver/transmitter channel •...
Page 248: Serial Communication Channel
15.1.3 Interrupt Control Logic An internal interrupt request signal (IRQ) notifies the MCF5253 interrupt controller of an interrupt condition. The output is the logical NOR of all (as many as four) unmasked interrupt status bits in the UART Interrupt Status Register (UISR). The UART Interrupt Mask Register (UIMR) can be programmed to determine which interrupts will be valid in the UISR.
Page 249: Uart Module Signal Definitions
UART Modules The UART module interrupt level in the MCF5253 interrupt controller is programmed external to the UART module. The UART can be configured to supply the vector from the UART Interrupt Vector Register (UIVR) or the SIM can be programmed to provide an autovector when a UART interrupt is acknowledged.
Page 250: Request-To-Send
UART2 has no CTS signal capability. 15.3 Operation The following sections describe the operation of the baud-rate generator, transmitter and receiver, and other operating modes of the UART module. MCF5253 Reference Manual, Rev. 1 15-4 Freescale Semiconductor...
Page 251: Baud-Rate Generator/Timer
15.3.1 Baud-Rate Generator/Timer The timer references made here relative to clocking the UART are different than the MCF5253 timer module that is integrated on the bus of the ColdFire core. The UART has a baud generator based on an internal baud-rate timer that is dedicated to the UART. The Clock Select Register (UCSR) needs to be programmed to enable the baud-rate timer.
Page 252: Transmitter
UART transmitter buffer (UTB). If the transmitter receives a disable command, it continues operating until the character (if one is present) in the transmit-shift register is completely shifted out of transmitter MCF5253 Reference Manual, Rev. 1 15-6 Freescale Semiconductor...
Page 253 Users must manually enable the transmitter by setting the enable-transmitter bit in the UART Command Register (UCR). 1. CTS and RTS are not available on UART2. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 15-7...
Page 254: Receiver
(framing error) and RxD remains low for one-half of the bit period after the stop bit is sampled, the receiver operates as if a new start bit is detected. The parity error (PE), MCF5253 Reference Manual, Rev. 1 15-8...
Page 255: Receiver Fifo
If an error occurs within the message, the error is not recognized until the final check is performed, and no indication exists as to which message character is at fault. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 15-9...
Page 256: Looping Modes
A received break is echoed as received until the next valid start bit is detected. 1. CTS and RTS are not available on UART2. MCF5253 Reference Manual, Rev. 1 15-10 Freescale Semiconductor...
Page 257: Local Loopback Mode
RxD Input Disabled Output (a) Automatic Echo Disabled RxD Input Disabled Output (b) Local Loopback Disabled RxD Input Disabled Output (c) Remote Loopback Figure 15-7. Looping Modes Functional Diagram MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 15-11...
Page 258: Multidrop Mode
The character is interpreted as an address character if the A/D bit is set or as a data character if the A/D bit is cleared. The polarity of the A/D bit is selected by MCF5253 Reference Manual, Rev. 1 15-12...
Page 259: Bus Operation
SIM Interrupt Control Register (ICR). If the UIVR is not initialized and the ICR is not programmed for autovector, a spurious interrupt exception is taken if interrupts are generated. This works in conjunction with the MCF5253 interrupt controller, which allows a programmable Interrupt Priority Level (IPL) for the interrupt.
Page 260: Mode Register 1 (Umr1N)
UMR1. The pointer is set to UMR1 by RESET or by a set pointer command using the control register. After reading or writing UMR1, the pointer points to UMR2. MCF5253 Reference Manual, Rev. 1 15-14 Freescale Semiconductor...
Page 261 The Parity Mode bits encode the type of parity used for the channel (see Table 15-3). The parity bit is added to the transmitted character and the receiver performs a parity check on incoming data. These bits can alternatively select multidrop mode for the channel. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 15-15...
Page 262: Mode Register 2 (Umr2N)
UMR2n do not update the pointer. Address MBAR + $1C0 (UMR20) Access: Supervisor or User read/write MBAR + $200 (UMR21) MBAR2 + $C00 (UMR22) TxRTS TxCTS Reset Table 15-5. Mode Register 2 (UMR2) MCF5253 Reference Manual, Rev. 1 15-16 Freescale Semiconductor...
Page 263: Status Registers (Usrn)
The RB, FE, and PE bits are cleared by the Reset Error Status command in the UCR registers if the RB bit has not been read. Also, RB, FE, PE and OE can also be cleared by reading the Receive buffer (URB). MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 15-17...
Page 264 This bit is also set when the transmitter is first enabled. Characters loaded into the transmitter holding register while the transmitter is disabled are not transmitted. 0 The CPU has loaded the transmitter-holding register or the transmitter is disabled. MCF5253 Reference Manual, Rev. 1 15-18 Freescale Semiconductor...
Page 265: Clock-Select Registers (Uscrn)
RCS2 RCS1 RCS0 Mode TIMER reserved reserved 3–0 The Transmitter Clock Select bits determine the clock source of the UART transmitter channel. TCS3–TCS0 TCS3 TCS2 TCS1 TCS0 SET 1 TIMER reserved reserved MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 15-19...
Page 266: Command Registers (Ucrn)
RxRDY bits in the USR are cleared, and the receiver FIFO pointer is reinitialized. All other registers are unaltered. Use this command instead of the receiver-disable command whenever the receiver configuration is changed (it places the receiver in a known state). MCF5253 Reference Manual, Rev. 1 15-20 Freescale Semiconductor...
Page 267: Reset Transmitter
Do Not Use 15.4.5.2.1 No Action Taken The “no action taken” command causes the transmitter to stay in its current mode. If the transmitter is enabled, it remains enabled; if disabled, it remains disabled. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 15-21...
Page 268: Transmitter Enable
If the receiver is already disabled, this command has no effect. 15.4.5.3.4 Do Not Use Do not use this bit combination because the result is indeterminate. MCF5253 Reference Manual, Rev. 1 15-22 Freescale Semiconductor...
Page 269: Receiver Buffer Registers (Ubrn)
UART Status Register (USR) TxRDY bit is clear and when the transmitter is disabled have no effect on the transmitter buffer. Address MBAR + $1CC (UTB0) Access: User write only MBAR + $20C (UTB1) MBAR2 + $C0C (UTB2) Reset Figure 15-14. Transmitter Buffer (UTBn) Register MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 15-23...
Page 270: Input Port Change Registers (Uipcrn)
1 The current state of the CTS input is logic one. 0 The current state of the CTS input is logic zero. Note: Not available on UART2 15.4.9 Auxiliary Control Registers (UACRn) The UART auxiliary control registers control the input enable. MCF5253 Reference Manual, Rev. 1 15-24 Freescale Semiconductor...
Page 271: Interrupt Status Registers (Uisrn)
UIMR. A UART module reset clears the contents of UISR. Address MBAR + $1D4 (UISR0) Access: User read only MBAR + $214 (UISR1) MBAR2 + $C14 (UISR2) RXRDY TXRDY Reset Figure 15-17. Interrupt Status Register (UISRn) MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 15-25...
Page 272: Interrupt Mask Registers (Uimrn)
Figure 15-18. Interrupt Mask Register (UIMRn) Table 15-17. Interrupt Mask Register (UIMRn) Field Descriptions Field Description Change-of-State 1 Enable interrupt 0 Disable interrupt 6–3 Reserved Delta Break 1 Enable interrupt 0 Disable interrupt MCF5253 Reference Manual, Rev. 1 15-26 Freescale Semiconductor...
Page 273: Baud Rate Generator (Msb) Register (Ubg1N)
The UIVR is reset to $0F, which indicates an uninitialized interrupt condition. 15.4.15 Input Port Registers (UIPn) The UIP registers show the current state of the CTS input. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 15-27...
Page 274: Output Port Data Registers (Uop1N)
0 This bit is not affected by writing a zero to this address. The output port bits are inverted at the pins so the RTS set bit provides an asserted RTS pin. Note: Not available on UART2. MCF5253 Reference Manual, Rev. 1 15-28 Freescale Semiconductor...
Page 275: 15.4.17 Programming
(beginning of a break). SIRQ then clears the interrupt source, waits for the next change-in-break interrupt (end of break), clears the interrupt source again, then returns from exception processing to the system monitor. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 15-29...
Page 276: Uart Module Initialization Sequence
2. If required, program operation of Transmitter Ready-to-Send (TxRTS Bit). 3. If required, program operation of Clear-to-Send (TxCTS Bit). 4. Select stop-bit length (SBx Bits). Command Register (UCR) Enable the receiver and transmitter. MCF5253 Reference Manual, Rev. 1 15-30 Freescale Semiconductor...
Page 277 UART Modules SERIAL MODULE INITIATE: CHANNEL INTERRUPTS CHK1 CALL CHCHK SAVE CHANNEL STATUS ENABLE ERRORS ENABLE RECEIVER ASSERT REQUEST TO SEND SINTR RETURN Figure 15-23. UART Software Flowchart (1 of 5) MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 15-31...
Page 278 TxCHK WAITED SET TRANSMITTER- TRANSMITTER TOO LONG NEVER-READY FLAG READY SEND CHARACTER TO TRANXMITTER WAITED CHARACTER SET RECEIVER- TOO LONG BEEN NEVER-READY FLAG RECEIVED Figure 15-24. UART Software Flowchart (2 of 5) MCF5253 Reference Manual, Rev. 1 15-32 Freescale Semiconductor...
Page 279 ERROR FLAG RETURN PRCHK HAVE PARITY ERROR SET PARITY ERROR FLAG CHRCHK GET CHARACTER FROM RECEIVER SAME AS TRANSMITTED CHARACTER SET INCORRECT CHARACTER FLAG Figure 15-25. UART Software Flowchart (3 of 5) MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 15-33...
Page 280 IRQ ARRIVED YET RETURN CLEAR CHANGE-IN-BREAK STATUS BIT REMOVE BREAK CHARACTER FROM RECEIVE FIFO REPLACE RETURN ADDRESS ON SYSTEM STACK AND MONITOR WARM START ADDRESS Figure 15-26. UART Software Flowchart (4 of 5) MCF5253 Reference Manual, Rev. 1 15-34 Freescale Semiconductor...
Page 281 UART Modules OUTCH TRANSMITTER READY SEND CHARACTER TO TRANSMITTER RETURN Figure 15-27. UART Software Flowchart (5 of 5) MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 15-35...
Page 282 UART Modules MCF5253 Reference Manual, Rev. 1 15-36 Freescale Semiconductor...
Page 283: Queued Serial Peripheral Interface (Qspi) Module
Chapter 16 Queued Serial Peripheral Interface (QSPI) Module This chapter describes the operation of the Queued Serial Peripheral interface module of the MCF5253 and provides its memory map and register descriptions. 16.1 Features The QSPI module provides a serial peripheral interface with queued transfer capability. It allows users to queue up to 16 transfers at once, eliminating CPU intervention between transfers.
Page 284: Internal Bus Interface
The QSPI uses a dedicated 80-byte block of static RAM accessible both to the module and the CPU to perform queued operations. The RAM is divided into three segments as follows: • 16 command control bytes (command RAM) MCF5253 Reference Manual, Rev. 1 16-2 Freescale Semiconductor...
Page 285: Qspi Ram
The QSPI contains an 80-byte block of static RAM that can be accessed by both the user and the QSPI. This RAM does not appear in the MCF5253 memory map because it can only be accessed by the user indirectly through the QSPI address register (QAR) and the QSPI data register (QDR).
Page 286 16 bits wide 0x0F QTR15 0x10 QRR0 Receive RAM 0x11 QRR1 16 bits wide 0x1F QRR15 0x20 QCR0 Command RAM 0x21 QCR1 8 bits wide 0x2F QCR15 Figure 16-2. QSPI RAM Model MCF5253 Reference Manual, Rev. 1 16-4 Freescale Semiconductor...
Page 287: Transmit Ram
Before any data transfers begin, control data must be written to the command RAM, and any out-bound data must be written to transmit RAM. Also, the queue pointers must be initialized to the first and last entries in the command queue. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 16-5...
Page 288: Baud Rate Selection
A delay can also be inserted between consecutive transfers to allow serial A/D converters to complete conversion. There are two transfer delay options: the user can MCF5253 Reference Manual, Rev. 1 16-6 Freescale Semiconductor...
Page 289: Transfer Length
Wraparound mode is enabled by setting QWR[WREN]. The queue can wrap to pointer address 0x0, or to the address specified by QWR[NEWQP], depending on the state of QWR[WRTO]. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 16-7...
Page 290: Qspi Memory Map And Register Definitions
QMR[MSTR], must be set for the QSPI module to operate correctly. Address MBAR + 0x400 Access: User read/write MSTR DOHIE BITS CPOL CPHA BAUD Reset Figure 16-3. QSPI Mode Register (QMR) MCF5253 Reference Manual, Rev. 1 16-8 Freescale Semiconductor...
Page 291 QSPI_CLK QSPI_Dout QSPI_Din QSPI_CS QMR[CPOL] = 0 Chip selects are active low QMR[CPHA] = 1 A = QDLYR[QCD] QCR[CONT] = 0 B = QDLYR[DTL] Figure 16-4. QSPI Clocking and Data Transfer Example MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 16-9...
Page 292: Qspi Delay Register (Qdlyr)
1 After executing command pointed to by QWR[ENDQP], wrap back to entry zero, or the entry pointed to by QWR[NEWQP] and continue execution. Wraparound location. Determines where the QSPI wraps to in wraparound mode. WRTO 0 Wrap to RAM entry zero. 1 Wrap to RAM entry pointed to by QWR[NEWQP]. MCF5253 Reference Manual, Rev. 1 16-10 Freescale Semiconductor...
Page 293: Qspi Interrupt Register (Qir)
Reserved, should be cleared. QSPI finished interrupt enable. Interrupt enable for SPIF. Setting this bit enables the interrupt, and clearing it disables SPIFE the interrupt. 7–4 Reserved, should be cleared. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 16-11...
Page 294: Qspi Address Register (Qar)
QSPI Data Register (QDR) The QDR, shown in Figure 16-9, is used to access QSPI RAM indirectly. The CPU reads and writes all data from and to the QSPI RAM through this register. MCF5253 Reference Manual, Rev. 1 16-12 Freescale Semiconductor...
Page 295: Command Ram Registers (Qcr0-Qcr15)
The delay between transfers is determined by QDLYR[DTL]. Chip select to QSPI_CLK delay enable. DSCK 0 Chip select valid to QSPI_CLK transition is one-half QSPI_CLK period. 1 QDLYR[QCD] specifies the delay from QSPI_CS valid to QSPI_CLK. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 16-13...
Page 296: Programming Example
The QSPI RAM is set up for a queue of 16 transfers. All four QSPI_CS signals are used in this example. 1. Set QSPI pin functionality by the programming the PIN_CONFIG register as appropriate. MCF5253 Reference Manual, Rev. 1 16-14...
Page 297 12. Write QAR with 0x0010 to select the first receive RAM entry. 13. Read QDR to get the received data for each transfer. 14. Repeat steps 5 through 13 to do another transfer. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 16-15...
Page 298 Queued Serial Peripheral Interface (QSPI) Module MCF5253 Reference Manual, Rev. 1 16-16 Freescale Semiconductor...
Page 299: Audio Interface Module (Aim)
The audio interface module provides the necessary input and output features to receive and transmit digital audio signals over serial audio interfaces (IIS/EIAJ) and over digital audio interfaces (IEC958). The MCF5253 is equipped with three serial audio interfaces compliant with Philips I S and Sony EIAJ format.
Page 300: Audio Interface Block Diagram
(write only) Receive ebuRcvData1 Block EbuIn2 ebuOut2 EbuIn3 EBUOUT2 ebuOut1 Block Receive ebuRcvData2 EbuIn4 Block ebuOut1 ebuOut2 EBUOUT1 clock gen ebuOff Bypass select ebuExtractedClock (To FreqMeas block) Figure 17-1. Audio Interface Block Diagram MCF5253 Reference Manual, Rev. 1 17-2 Freescale Semiconductor...
Page 301: Audio Interface Structure
Besides the mechanism to let the processor access the audio data, there are several interrupts and control registers to allow the processor to determine when it should read or write data to the appropriate Processor Data Interface Register. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 17-3...
Page 302: Audio Interface Memory Map And Register Definitions
Processor data in 3 Left (PDIR3-L) MBAR2 + 0x48 MBAR2 + 0x4C MBAR2 + 0x50 MBAR2 + 0x54 Processor data in 1 Right (PDIR1-R) MBAR2 + 0x58 MBAR2 + 0x5C MBAR2 + 0x60 MCF5253 Reference Manual, Rev. 1 17-4 Freescale Semiconductor...
Page 303 CD Text Control MBAR2 + 0x9F DMA Configure MBAR2 + 0xA2 Phase Configure MBAR2 + 0xA6 XTRIM MBAR2 + 0xA8 Frequency measurement MBAR2 + 0xC8 Block decoder/encoder control MBAR2 + 0xCE audioGlob MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 17-5...
Page 304: Audio Interrupt Mask And Status Register Descriptions
UCHANTXUNDER U Channel transmit register underrun reg. IntClear UCHANTX NEXTFIRST U Channel transmit register next byte will be first write to Tx reg U1CHANRCVFULL U1Channel receive register full read Rcv reg MCF5253 Reference Manual, Rev. 1 17-6 Freescale Semiconductor...
Page 305 IntClear3 QCHANRVFULL Q2 Channel receive register full read rcv reg QCHANOVERRUN Q2 Channel receive register overrun reg. IntClear3 UQCHANSYNC U/Q2 Channel sync found reg. IntClear3 UQCHANERR U/Q2 Channel framing error reg IntClear3 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 17-7...
Page 306: Serial Audio Interface (I S/Eiaj) Register Descriptions
SELECT FREQUENCY INVERT Reset 0 Figure 17-2. IIS1 Configuration Registers (0x10) Figure 17-3 illustrates the valid bits in the IIS2 Configuration Registers and Table 17-5 provides the description of the bit fields. MCF5253 Reference Manual, Rev. 1 17-8 Freescale Semiconductor...
Page 307 0 Not active 1 Active CFLG CFLG sample position. See note 16 0 Sample CFLG input 1 SCLK clock after incoming LRCK edge 1 Sample CFLG input 6 SCLK clocks before incoming LRCK edge MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 17-9...
Page 308 010 48 bit clocks / word clock 000 32 bit clocks / word clock Other settings: reserved, undefined LRCK INVERT See note 5 following bit these descriptions. 1 Invert on word clock 0 No invert on word clock MCF5253 Reference Manual, Rev. 1 17-10 Freescale Semiconductor...
Page 309: Iis/Eiaj Transmitter Descriptions
IIS/EIAJ Transmitter Descriptions The two I S/EIAJ transmitters operate independently. Each of the transmitters has the capability of transmitting data from one of several sources: • One of the three processor data out registers. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 17-11...
Page 310: Iis/Eiaj Transmitter Interrupts
SCLK/LRCK. Data is always clocked on the rising edge of the SCLK bit clock (non-inverted). SCLK (inverted clock) SCLK (noninverted) Left (if noninverted) LRCK(IIS) LRCK(Sony-16 bit) Left (if noninverted) Data out D19 D18 D17 Data In Figure 17-5. IIS/EIAJ Timing Diagram (16 SCLK edges per word) MCF5253 Reference Manual, Rev. 1 17-12 Freescale Semiconductor...
Page 311: Digital Audio Interface (Ebu/Spdif) Register Descriptions
Address MBAR2 + 0x20 (Reset 0x3F00) Access: User read/write TXSOURCE SELECT Reset IEC958 TX FIFO TXSOURCE IEC958 OUT U SOURCE CLOCKSEL RXSOURCE CONTROL SELECT CONTROL SELECT SELECT SELECT Reset Figure 17-7. EBU1Config Register MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 17-13...
Page 312 0 Outgoing V flag always 1 VALCONTROL 1 Outgoing V flag always 0 4–2 000 Off. Output 0 IEC958 OUT SELECT 001 Feed-through EBUIn1 010 Feed-through EBUIn2 011 Feed-through EBUIn3 100 Feed-through EBUIn4 101 Normal operation MCF5253 Reference Manual, Rev. 1 17-14 Freescale Semiconductor...
Page 313 EBU2Config Register and Table 17-7 provides the description of the bit fields. Address MBAR2 + 0xD0 (Reset 0x3f00) Access: User read/write Reset IEC958 RECEIVE SOUCE SELECT Reset Figure 17-8. EBU2Config Register MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 17-15...
Page 314: Iec958 Receive Interface
For a description of the control (or “C”) channel in EBU data formatting, refer to the IEC958-3 specification’s description of control channel. Figure 17-9 illustrates the valid bits in the EBURcvCChannel. MCF5253 Reference Manual, Rev. 1 17-16 Freescale Semiconductor...
Page 315: Control Channel Interrupt (Iec958 "C" Channel New Frame)
EBU signal. If the receiver finds such an illegal sequence, the illegal symbol interrupt is set. No corrective action is undertaken. When the interrupt occurs, this means: a) The EBU signal is has been affected by noise MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 17-17...
Page 316: Ebu Extracted Clock
U Channel Receive and Q Channel Receive Register Descriptions Figure 17-10 illustrates the valid bits in the U Channel Receive and Q Channel Receive Registers and Table 17-8 provides the description of the bit fields. MCF5253 Reference Manual, Rev. 1 17-18 Freescale Semiconductor...
Page 317 Table 17-9. CDTEXTCONTROL Register Field Descriptions Field Description Notes 0 No action on free-running sync position counter 2, 3 PRESETEN 1 Preset free-running sync position counter 14–8 Sync presetting count 1, 3 PRESETCOUNT MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 17-19...
Page 318: U And Q Receive Register Interrupts
This section details the behavior of the user channel receive interface on incoming CD user channel subcode in the IEC958 receiver. This mode is selected if UsyncMode (bit 1) in register CD-Subcode control, is set. MCF5253 Reference Manual, Rev. 1 17-20 Freescale Semiconductor...
Page 319 QChannelRcvFull occurs, it is coincident with UChannelRcvFull. There is only one QChannelRcvFull for every 8 UChannelRcvFull. The convention is that the most significant data is transmitted first, and is left-aligned in the registers. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 17-21...
Page 320: Behavior Of User Channel Receive Interface (Non-Cd Data)
‘0’. In addition to data, the interface allows for transmission of the C- and U-channels and control over the Valid flag. Note: For the U-channel, only the CD User Data format is supported. MCF5253 Reference Manual, Rev. 1 17-22...
Page 321: Transmit "C" Channel
CD standard specification. The generation of the data needs to be done in software and loaded into hardware registers. The Audio peripheral has provisions to insert this CD subcode stream into the outgoing MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 322: Cd Subcode Interrupts
EBU1 Reset Figure 17-13. CD-Subcode Register 17.6.3 CD Subcode Interrupts The following interrupts are associated with the CD Subcode data: • UChannelTxEmpty—Register is empty, needs re-loaded. • UChannelTxUnderrun—Under run error on register. MCF5253 Reference Manual, Rev. 1 17-24 Freescale Semiconductor...
Page 323 ; load UChannelTransmit with data from pointer update pointer reset interrupt end if ; MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 17-25...
Page 324: Free Running Counter Synchronization
RCK clock is kept silent. At a certain point in time, the CDR60 will start clocking the RCK, and then it will require that the first symbol transmitted from the MCF5253 to the CDR60 is a sync symbol. If this is not the case, the CDR60 fails to synchronize.
Page 325: Data Exchange Register Descriptions
Multiple address to read this register allows MOVEM instruction to read FIFO. 0x5C 0x60 0x64 PDIR3-R Processor data in Right – 0x68 Multiple address to read this register allows MOVEM instruction to read FIFO. 0x6C 0x70 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 17-27...
Page 326: Data Exchange Register Overview
Data written to it will end in one of the FIFO ‘s. (fig 17-1) 12,14, 17a, 17b or 25. • PDIR1-L, PDIR1-R (Processor data in). Used to transfer data to the processor. These 32-bit registers, each occupy 4 consecutive longword addresses are used to read data from the audio bus. MCF5253 Reference Manual, Rev. 1 17-28 Freescale Semiconductor...
Page 327: Data In Selection
Table 17-15. DataInControl Register Field Descriptions Field Description Reset 31–24 Reserved. 0 Normal operation PDIR3 ZERO 1 Always read zero from PDIR3 CONTROL 0 Normal operation PDIR3 RESET 1 Reset PDIR3 to one sample remaining MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 17-29...
Page 328 01 Full interrupt if at least 2 samples in FIFO INTERRUPT 10 Full interrupt if at least 3 samples in FIFO SELECT 11 Full interrupt if at least 6 samples in FIFO MCF5253 Reference Manual, Rev. 1 17-30 Freescale Semiconductor...
Page 329: Pdir And Pdor Field Formatting
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 17-31...
Page 330: Overrun And Underrun With Pdir And Pdor Registers
Automatic Resynchronization of FIFOs An automatic FIFO resynchronization feature is available on the MCF5253. It can be enabled or disabled separately for every FIFO. If enabled, the hardware will check if the left and right FIFOs are in sync, and if not, it will set the filling pointer of the right FIFO to be equal to the filling pointer of the left FIFO.
Page 331: Audioglob Register Descriptions
0 Auto synchronization off 1 Auto synchronization on IIS1 FIFO AUTO SYNC 0 Auto synchronization off 1 Auto synchronization on PDIR2 FIFO AUTO SYNC 0 Auto synchronization off 1 Auto synchronization on MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 17-33...
Page 332: Audio Interrupts
IIS1 Tx FIFO. Even if the FIFO is in reset state, the interrupt will continue running. 17.7.7.2 PDIR1, PDIR2, and PDIR3, Interrupts With FIFO’s feeding data to the PDIR registers, three interrupts are associated. 1. Full 2. Under/over 3. Resync MCF5253 Reference Manual, Rev. 1 17-34 Freescale Semiconductor...
Page 333: Pdor1, Pdor2, And Pdor3 Interrupts
Table 17-20. Interrupt Register Field Description (0x94, 0x98) Interrupt Name Description How to Clear FIFO IIS1TxUnOv IIS1 transmit under/overrun reg. IntClear FIFO IIS1TxResyn IIS1 transmit resync reg. IntClear FIFO IIS2TxUnOv IIS2 transmit under/overrun reg. IntClear MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 17-35...
Page 334 IIS 2 transmit FIFO empty write to FIFO ebuTxEmpty IEC958 transmit FIFO empty write to FIFO PDIR2 full Processor data input full read from PDIR2 PDIR1 full Processor data input full read from PDIR1 MCF5253 Reference Manual, Rev. 1 17-36 Freescale Semiconductor...
Page 335: Audio Interrupt Routines And Timing
While this is a situation that should be taken seriously, it will rarely occur, if at all. However, should this happen, the system will continue to repeat the last sample until the FIFO buffer has new data. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 17-37...
Page 336: Cd-Rom Block Encoder And Decoder Register Descriptions
See note 3. ENABLE 1 Descramble enabled. 0 Escramble disabled 9, 10 DECODE See note 4. MODE 00 No CRC check 01 Mode 1 10 Mode 2, form 1 11 Mode 2, form 2 MCF5253 Reference Manual, Rev. 1 17-38 Freescale Semiconductor...
Page 337 Notation used is 32-bit words. Bits31-16 are part of the LEFT sample, bits 15-0 are part of the RIGHT sample. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 17-39...
Page 338: Cd-Rom Decoder Interrupts
2352 bytes (the nominal block length). • crcError interrupt—Set when the next longword to be read is the first word of a new block, and CRC check on the previous block failed. MCF5253 Reference Manual, Rev. 1 17-40 Freescale Semiconductor...
Page 339: Cd-Rom Encoder Interrupts
PDIR2 and PDOR3 registers support DMA transfer, as the others need more than 1 long-word to transfer data to/from the FIFO and cannot be used with DMA operation. Operation is as follows: • If PDIR2 is full and DMAConfig(1) is set to ‘0’, DMA1REQ is activated. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 17-41...
Page 340: Phase/Frequency Determination And Xtrim Function
CRIN (either external generated clock or crystal) to the recovered SPDIF audio clock - if so desired. Some external hardware is required for this including a set of varicap diodes. MCF5253 Reference Manual, Rev. 1 17-42...
Page 341 For measurement of the EBU input: FreqMeas = (EBU Freq) / Faudio × (2 ** 15) × Gain • Table 17-24. PhaseConfig and Frequency Measure Register Addresses Address Name Width Description Access MBAR2 + 0xA3 PhaseConfig Phase Configuration (gain and source select) MBAR2 + 0xA8 FreqMeas Frequency measurement MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 17-43...
Page 342: Filtering For The Discrete Time Oscillator
The XTRIM output allows use of varicap-controlled crystal. (See Figure 17-26). To do this, the XTRIM must output a PWM/PDM modulated phase-error signal. One 16-bit config register is associated with this functionality. MCF5253 Reference Manual, Rev. 1 17-44 Freescale Semiconductor...
Page 343: Xtrim Internal Logic
17-27. It is a first-order pulse density modulator, working from the system clock divided by 16. XTRIM Output 16-bit adder PdmOut[15:0] Memory-mapped Register sysclock/16 Figure 17-27. PDM Modulator Used on XTRIM Output MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 17-45...
Page 344 Audio Interface Module (AIM) MCF5253 Reference Manual, Rev. 1 17-46 Freescale Semiconductor...
Page 345: I 2 C Modules
Chapter 18 C Modules This chapter provides the system configuration and protocol of the Inter IC Communications (I modules of the MCF5253, the memory map and register descriptions, and a programming example. 18.1 C Interface Features • Compatibility with I C Bus standard •...
Page 346: I 2 C Overview
CONTROL COMPARE Figure 18-1. I C Module Block Diagram 18.2 C Overview The MCF5253 provides dual I C interface capability. The I C interface described in this chapter is fully compatible with the I C Bus Standard. The I C is a two-wire, bidirectional serial bus that provides a simple and efficient method of data exchange between devices.
Page 347: I 2 C System Configuration
A standard communication is composed of four parts: 1. START signal 2. Slave address transmission 3. Data transfer 4. STOP signal They are described briefly in the following sections and shown in Figure 18-2. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 18-3...
Page 348: Start Signal
18-2). 18.4.3 Data Transfer Once successful slave addressing is achieved, the data transfer can proceed on a byte-by-byte basis in the direction specified by the R/W bit sent by the calling master. MCF5253 Reference Manual, Rev. 1 18-4 Freescale Semiconductor...
Page 349: Repeated Start Signal
Once a device clock has gone low, it holds the SCL line low until the clock high state is reached. However, the change of low to high in the MCF5253 clock may not change the state of the SCL line if MCF5253 Reference Manual, Rev.
Page 350: Handshaking
Table 18-1 shows the register summary of the I C interface. Table 18-1. I C Interfaces Register Summary Address C Module Registers MBAR+$280 C Address Register (MADR) MBAR+$284 C Frequency Divider Register (MFDR) MCF5253 Reference Manual, Rev. 1 18-6 Freescale Semiconductor...
Page 351: I 2 C Control Registers (Mbcr)
C Status Register (MBSR2) MBAR2 + $450 MBAR2 I C Data I/O Register (MBDR2) NOTE External masters cannot access the MCF5253 on-chip memories or MBAR, but can access any I C module register. 18.5.1 C Address Registers (MADR) This register contains the address that the I C will respond to when addressed as a slave.
Page 352 Table 18-4 The MFDR frequency value can be changed at any point in a program. Table 18-4. I C Prescaler Values MBC5-0 (hex) Divider (dec) MBC5-0 (hex) Divider (dec) MCF5253 Reference Manual, Rev. 1 18-8 Freescale Semiconductor...
Page 353 C interrupts. It also contains the bits that govern operation as Master or Slave. Address MBAR+ $288 (MBCR) Access: Supervisor or User read/write MBAR2+ $448 (MBCR2) IIEN MSTA TXAK RSTA Reset Figure 18-6. MBCR Register MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 18-9...
Page 354: I 2 C Status Registers (Mbsr)
This status register is read-only with the exception of bit 1 (IIF) and bit 4 (IAL), which can be cleared by software. All bits are cleared on reset except bit 7 (ICF) and bit 0 (RXAK), which are set (=1) at reset. MCF5253 Reference Manual, Rev. 1 18-10...
Page 355 C is a slave and has an address match. Checking this bit, the CPU can select slave transmit/receive mode according to the command of the master. 1 Slave transmit, master reading from slave 0 Slave receive, master writing to slave MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 18-11...
Page 356: I 2 C Data I/O Registers (Mbdr)
3. Set the IEN bit of the I C Control Register (MBCR) to enable the I C bus interface system. 4. Modify the MBCR to select master/slave mode, transmit/receive mode, and interrupt-enable or not. MCF5253 Reference Manual, Rev. 1 18-12 Freescale Semiconductor...
Page 357: Generation Of Start
Generation of START After completion of the initialization procedure, users can transmit serial data by selecting the “master transmitter'’ mode. If the MCF5253 is connected to a multimaster bus system, users must test the state of the I C Busy Bit (IBB) to check whether the serial bus is free.
Page 358: Post-Transfer Software Response
MOVE.B TXCNT,D0 ;Get value from the transmitting counter BEQ.S ;If no more data, branch to end MOVE.B DATABUF,-(A7) ;Transmit next byte of data MOVE.B (A7)+,MBDR MOVE.B TXCNT,D0 ;Decrease the TXCNT SUBQ.L #1,D0 MCF5253 Reference Manual, Rev. 1 18-14 Freescale Semiconductor...
Page 359: Generation Of Repeated Start
Setting RXAK means an “end-of-data’' signal from the master receiver, after which it must be switched from transmitter mode to receiver mode by software. A read from MBDR then releases the SCL line so that the master can generate a STOP signal. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 18-15...
Page 360: Arbitration Lost
4. Sets the IAL to indicate the failed attempt to engage the bus When considering these cases, the slave service routine should test the IAL first and the software should clear the IAL bit if it is set. MCF5253 Reference Manual, Rev. 1 18-16 Freescale Semiconductor...
Page 361 Rx Mode Read Data Dummy Read Generate Dummy Read Dummy Read From MBDR From MBDR Stop Signal From MBDR From MBDR And Store Figure 18-9. Flow-Chart of Typical I C Interrupt Routine MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 18-17...
Page 362 C Modules MCF5253 Reference Manual, Rev. 1 18-18 Freescale Semiconductor...
Page 363: Boot Rom
19.1 Overview The boot ROM on the MCF5253 serves to boot the CPU in designs which do not have external Flash memory or ROM. Typically these systems use a separate MCU for control, and/or the MCF5253 is used as a stand-alone decoder.
Page 364: Boot Rom Operation
• Hard Disk Drive (IDE) In slave mode, the MCF5253 will wait for communication from a controlling MCU and store the code it receives in RAM. It executes this code after receiving an execute command. The controlling MCU must control the data transfer and handle error recovery if required.
Page 365: Boot Type Detection
Table 19-1. Table 19-1. Boot Detection GPIO Boot Mode GPIO50 GPIO49 GPIO48 C master SPI (master) IDE (master) C slave UART (5.6448/11.2896 MHz Xtal) UART (8.4672/16.9344/33.8688 MHz Xtal) UART (5/10/20 MHz Xtal) MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 19-3...
Page 366: Serial Boot Data Format
The command is coded in the upper nibble; the size is coded in the lower nibble. The size specification defines the word length to be used to store the data in the MCF5253 memory space. This allows writing to registers through the boot loader.
Page 367: Supported Commands
– Data/Code section The load address provides the start location where the boot record will be stored within the MCF5253’s memory map, the execution address provides the entry point code execution will begin from after the boot record has been loaded into memory. The CRC allows the boot record to be validated before attempting to begin code execution.
Page 368: Boot From I 2 C - Slave Mode
19.2.5.3 Boot from UART In UART mode, the MCF5253 acts as a slave device and receives data over UART1 (TXD1 and RXD1). UART configuration: Baud rate:19200 / 9600 / 4800 baud @ Xtal = 33.8688 / 16.9344 / 8.4672 MHz (see config GPIO’s) 19200 / 9600 baud @ Xtal = 11.2896 / 5.6448 MHz (see config GPIO’s)
Page 369: Creating Appropriate Boot Record Files
Multiple ‘Store Immediate’ headers can be used if several separate blocks of data need to be loaded before code execution can begin. Example utilities are available from Freescale to generate appropriate boot record files if required, contact your local Freescale representative for further details. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 19-7...
Page 370 Boot ROM MCF5253 Reference Manual, Rev. 1 19-8 Freescale Semiconductor...
Page 371: Background Debug Mode (Bdm) Interface
Chapter 20 Background Debug Mode (BDM) Interface This chapter details the MCF5253 hardware debug support. The topics discussed are real-time trace support, background debug mode (BDM), and real-time debug support. The memory map, register descriptions and debug support operation are provided.
Page 372: Breakpoint (Bkpt)
These outputs indicate the current status of the processor pipeline and are not related to the current bus transfer. The PST value is updated each processor cycle. MCF5253 Reference Manual, Rev. 1 20-2 Freescale Semiconductor...
Page 373: Processor Status Clock (Pstclk)
(4 bits): one nibble allows the processor to transmit information concerning the execution status of the core (processor status: PST), while the other nibble allows operand data to be MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 374: Processor Status Signal Encoding
$4, when executed. This instruction can define logic analyzer triggers for debug and/or performance analysis. Additionally, a WDDATA instruction is supported that allows the processor core to write any operand (byte, word, longword) directly to the DDATA port, independent of any debug module MCF5253 Reference Manual, Rev. 1 20-4 Freescale Semiconductor...
Page 375: Begin Execution Of Taken Branch (Pst = $5)
The PST can continue with the next instruction before the address has completely displayed on the DDATA because of the DDATA FIFO. If the FIFO is full and the MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 376: Begin Execution Of Rte Instruction (Pst = $7)
ColdFire implements the BDM controller in a dedicated hardware module. Although some BDM operations do require the CPU to be halted (For example, CPU register accesses), other BDM commands such as memory accesses can be executed while the processor is running. MCF5253 Reference Manual, Rev. 1 20-6 Freescale Semiconductor...
Page 377: Cpu Halt
ColdFire processor into emulation mode using the EMU bit in the configuration/status register (CSR). Once the system initialization is complete, the processor response to a BDM GO command is dependent on the set of BDM commands performed while breakpointed. Specifically, if the processor’s PC register MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 20-7...
Page 378: Bdm Serial Interface
CPUCLK as well as the DSI. The DSO output is delayed from the DSCLK-enabled CPUCLK rising edge. All events in the debug module’s serial state machine are based on the rising edge of the microprocessor clock. MCF5253 Reference Manual, Rev. 1 20-8 Freescale Semiconductor...
Page 379: Receive Packet Format
The Control Bit (Bit 16) is reserved. Command and data transfers initiated by the development system should C-Control clear bit 16. 15–0 The data field contains the message data to be communicated from the development system to the debug Data Field module. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 20-9...
Page 380: Bdm Command Set
Read the debug module register. Parallel $2D {$4† 20.3.4.1. MODULE REGISTER DRc[4:0]} 11/20-24 WRITE DEBUG WDMREG Write the operand data to the debug module Parallel $2C {$4† 20.3.4.1. MODULE REGISTER register. Drc[4:0]} 12/20-24 MCF5253 Reference Manual, Rev. 1 20-10 Freescale Semiconductor...
Page 381 BDM command set, the optional set of extension words is defined as “Address,” “Data,” or “Operand Data.” Table 20-7. BDM Size Field Encoding Encoding Operand Size Bit Values Byte 8 bits Word 16 bits Longword 32 bits Reserved MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 20-11...
Page 382: Command Sequence Diagram
In the third cycle, the development system supplies the low-order 16 bits of a memory address. The debug module always returns the “not ready” response in this cycle. At the completion of the third cycle, the MCF5253 Reference Manual, Rev. 1 20-12...
Page 383: Command Set Descriptions
CPU core is not halted. Figure 20-8. Command/Result Formats Command Sequence: Next CMD RAREG/RDREG LS Result MS Result Next CMD “Not Ready” BERR Figure 20-9. Read A/D Register Command Sequence Operand Data: None MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 20-13...
Page 384: Write Address/Data Register (Wareg And Wdreg)
Attribute Register (BAAR). The hardware forces the low-order bits of the address to zeros for word and longword accesses to ensure that operands are always accessed on natural boundaries: words on 0-modulo-2 addresses, longwords on 0-modulo-4 addresses. MCF5253 Reference Manual, Rev. 1 20-14 Freescale Semiconductor...
Page 385 Background Debug Mode (BDM) Interface Figure 20-11. WAREG/WDREG Command Format Figure 20-12. READ Command/Result Format MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 20-15...
Page 386: Write Memory Location (Write)
Attribute Register (BAAR). The hardware forces the low-order bits of the address to zeros for word and longword accesses to ensure that operands are always accessed on natural boundaries: words on 0-modulo-2 addresses, longwords on 0-modulo-4 addresses. MCF5253 Reference Manual, Rev. 1 20-16 Freescale Semiconductor...
Page 387: Dump Memory Block (Dump)
READ is executed to set up the starting address of the block and to retrieve the first result. The DUMP command retrieves subsequent operands. The initial address is incremented by the operand size (1, 2, or MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 388 The size field is examined each time a DUMP command is processed, allowing the operand size to be dynamically altered. Figure 20-15. DUMP Command/Result Format MCF5253 Reference Manual, Rev. 1 20-18 Freescale Semiconductor...
Page 389: Fill Memory Block (Fill)
FILL, NOP or by a WRITE command. Otherwise, an illegal command response is returned. The NOP command can be used for intercommand padding without corrupting the address pointer. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 20-19...
Page 390 BERR Write Data Fill (B/W) Memory “Not Ready” Location “Not Ready” Next Cmd Next Cmd “Illegal” “Not Ready” “Cmd Complete” Next Cmd “Not Ready” BERR Figure 20-17. Fill Memory Block Command Sequence MCF5253 Reference Manual, Rev. 1 20-20 Freescale Semiconductor...
Page 391: Resume Execution (Go)
NOP performs no operation and may be used as a null command where required. Command Formats: Table 20-13. NOP Command Command Sequence: NEXT CMD SYNC_PC “CMD COMPLETE” Figure 20-19. No Operation Command Sequence MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 20-21...
Page 392: Read Control Register (Rcreg)
$807 MAC Accumulator (ACC1) $808 MAC Accumulator (ACC2) $80B MAC Accumulator (ACC3) $80E Status Register (SR) $80F Program Register (PC) $C04 RAM Base Address Register (RAMBAR0) $C05 RAM Base Address Register (RAMBAR1) MCF5253 Reference Manual, Rev. 1 20-22 Freescale Semiconductor...
Page 393: Write Control Register (Wcreg)
Result Data: Successful write operations return a $FFFF. Bus errors on the write cycle are indicated by the assertion of bit 16 in the status message and by a data pattern of $0001. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 20-23...
Page 394: Read Debug Module Register (Rdmreg)
The DSCLK signal must be inactive while debug module register writes from the CPU accesses are performed using the WDEBUG instruction. Figure 20-25. WDMREG BDM Command Register MCF5253 Reference Manual, Rev. 1 20-24 Freescale Semiconductor...
Page 395: 20.3.4.1.13 Unassigned Opcodes
The presence of rounding logic in the output data path of the eMAC requires special care for BDM-initiated reads and writes of its programming model. In particular, any result rounding modes must MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 20-25...
Page 396: Real-Time Debug Support
The debug module provides a number of hardware resources to support various hardware breakpoint functions. Specifically, three types of breakpoints are supported: PC with mask, operand address range, and data with mask. These three basic breakpoints can be configured into one- or two-level triggers with MCF5253 Reference Manual, Rev. 1 20-26 Freescale Semiconductor...
Page 397: Theory Of Operation
Once the debug interrupt is recognized, the processor aborts execution and initiates exception processing. At the initiation of the exception processing, the core enters emulator mode. After the standard 8-byte MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 20-27...
Page 398: Emulator Mode
SRAM module is disabled while in this mode. The return-from-exception (RTE) instruction exits emulation mode. The processor status output port provides a unique encoding for emulator mode entry ($D) and exit ($7). MCF5253 Reference Manual, Rev. 1 20-28 Freescale Semiconductor...
Page 399: Debug Module Hardware
(setting IPW = 1). The BDM commands must not be issued if the ColdFire processor is accessing the debug module registers using the WDEBUG instruction. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 20-29...
Page 400: Address Breakpoint Registers
This field contains the 32-bit address which marks the lower bound of the address breakpoint range. Additionally, if a breakpoint on a specific address is required, the value is programmed into the ABLR. MCF5253 Reference Manual, Rev. 1 20-30 Freescale Semiconductor...
Page 401: Address Attribute Trigger Register
The Transfer Modifier Mask field corresponds to the TM field. Setting a bit in this field causes the corresponding bit in TM to be ignored in address comparisons. The Read/Write field is compared with the R/W signal of the processor’s local bus. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 20-31...
Page 402: Program Counter Breakpoint Register (Pbr, Pbmr)
TDR. The PBR is accessible in supervisor mode as debug control register $8 using the WDEBUG instruction and through the BDM port using the RDMREG and WDMREG MCF5253 Reference Manual, Rev. 1 20-32 Freescale Semiconductor...
Page 403: Data Breakpoint Registers (Dbr, Dbmr)
The DBMR is accessible in supervisor mode as debug control register $F using the WDEBUG instruction and through the BDM port using the WDMREG command. The DBR is overwritten by the BDM hardware when accessing memory as described in Section 20.4.1.2, “Debug Module Hardware.” MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 20-33...
Page 404 The data breakpoint register supports both aligned and misaligned references. The relationship between the processor address, the access size, and the corresponding location within the 32-bit data bus is shown Table 20-20. MCF5253 Reference Manual, Rev. 1 20-34 Freescale Semiconductor...
Page 405: Trigger Definition Register (Tdr)
0 Level-2 trigger = PC_condition & Address_range & Data_condition 1 Level-2 trigger = PC_condition | (Address_range & Data_condition) 0 Level-1 trigger = PC_condition & Address_range & Data_condition 1 Level-1 trigger = PC_condition | (Address_range & Data_condition) MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 20-35...
Page 406: Configuration/Status Register (Csr)
The CSR is accessible in supervisor mode as debug control register $0 using the WDEBUG instruction and through the BDM port using the RDMREG and WDMREG commands. MCF5253 Reference Manual, Rev. 1 20-36 Freescale Semiconductor...
Page 407 There is no support for any type of “nesting” of debug interrupts. If set, the PSTCLK Disable bit disables the generation of the PSTCLK output signal, and forces this signal to remain quiescent. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 20-37...
Page 408 In this mode, the trigger reporting can be considered to be precise. As previously detailed, the occurrence of an address and/or data breakpoint should always happen before the next instruction begins execution. Therefore the occurrence of the address/data breakpoints should be guaranteed. MCF5253 Reference Manual, Rev. 1 20-38 Freescale Semiconductor...
Page 409: Bdm Address Attribute Register (Baar)
The debug module supports concurrent operation of both the processor and most BDM commands. BDM commands may be executed while the processor is running, except for the operations that access processor/memory registers as follows: MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 20-39...
Page 410: Freescale-Recommended Bdm Pinout
RESET +3.3V PST3 PST2 PST1 PST0 DDATA3 DDATA2 DDATA1 DDATA0 Freescale Reserved Freescale Reserved PSTCLK Vdd_CPU Supplied by target Pins reserved for BDM developer use. Contact developer. Figure 20-39. Recommended BDM Connector MCF5253 Reference Manual, Rev. 1 20-40 Freescale Semiconductor...
Page 411: Ieee 1149.1 Test Access Port (Jtag)
• Sample the MCF5253 system pins during operation and transparently shift out the result • Set the MCF5253 output drive pins to fixed logic values while reducing the shift register path to a single cell • Protect the MCF5253 system output and input pins from backdriving and random toggling (such...
Page 412: Jtag Signal Descriptions
TRST Figure 21-1. JTAG Test Logic Block Diagram 21.3 JTAG Signal Descriptions The JTAG operation on the MCF5253 is enabled when TEST[2:0]= 000, in which case the external pin descriptions in Table 21-1 apply.Otherwise, the JTAG Test Access Port signals (TCK/TMS/TDI/TDO/TRST) are interpreted as the debug port pins.
Page 413: Test Clock (Tck)
21.3.1 Test Clock (TCK) TCK is the dedicated JTAG test logic clock that is independent of the MCF5253 processor clock. Various JTAG operations occur on the rising or falling edge of TCK. The internal JTAG controller logic is designed such that holding TCK high or low for an indefinite period of time will not cause the JTAG test logic to lose state information.
Page 414: Test Data Input/Development Serial Input (Tdi/Dsi)
21-2. For more detail on each state, refer to the IEEE 1149.1A Standard JTAG document. NOTE From any state that the TAP controller is in, Test-Logic-Reset can be entered if TMS is held high for at least five rising edges of TCK. MCF5253 Reference Manual, Rev. 1 21-4 Freescale Semiconductor...
Page 415 E1IR PAUSE - DR PAUSE - IR PaDR PaIR EXIT2 - DR EXIT2 - IR E2DR E2IR UPDATE - IR UPDATE - DR UpIR UpDR Figure 21-2. JTAG TAP Controller State Machine MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 21-5...
Page 416: Idcode
IDCODE The IDCODE instruction selects the 32-bit IDcode register for connection as a shift path between the TDI pin and the TDO pin. This instruction lets users interrogate the MCF5253 to determine its version number MCF5253 Reference Manual, Rev. 1...
Page 417: Sample/Preload Instruction
The SAMPLE/PRELOAD instruction provides two separate functions. First, it obtains a sample of the system data and control signals present at the MCF5253 input pins and just prior to the boundary scan cell at the output pins. This sampling occurs on the rising edge of TCK in the capture-DR state when an instruction encoding of 2 is resident in the instruction register.
Page 418: Bypass Instruction
TDI pin to the bypass register to the TDO pin. This instruction enhances test efficiency by reducing the overall shift path when a device other than the MCF5253 processor becomes the device under test on a board design with multiple chips on the overall IEEE1149.1A defined boundary-scan chain. The bypass register has been implemented in accordance with IEEE1149.1A so that the shift register stage is set to...
Page 419: Jtag Boundary Scan Register
21.7 Disabling IEEE 1149.1A Standard Operation There are two ways to use the MCF5253 without the IEEE 1149.1A test logic being active: 1. Non-use of the JTAG test logic by either non-termination (disconnection) or intentional fixing of TAP logic values.
Page 420: Obtaining The Ieee 1149.1A Standard
Figure 21-4. Disabling JTAG in JTAG Mode A second method of using the MCF5253 without the IEEE 1149.1A logic being active is to select Debug mode by setting TEST[2:0]= 001. The IEEE 1149.1A test controller is now placed in the test-logic-reset state by the internal assertion of the TRST signal to the controller and the TAP pins function as debug mode pins.
Page 421: Usb, Ata Dma, And Clock Integration Module
22.1 Introduction This chapter includes registers that are used to configure the various modules that are new to the MCF5253 family. It also includes a shared 16 kB local memory for the ATA and USB modules. 22.2 Memory Map and Register Definitions Table 22-1 provides the memory map and register definitions for the ATA DMA integration module.
Page 422 1 ATA to RAM ATA DMA transfer active. ADTA 1 ATA DMA armed. Will transfer data when needed as long as atadma_count > 0. 0 ATA DMA blocked. WIll not transfer data. MCF5253 Reference Manual, Rev. 1 22-2 Freescale Semiconductor...
Page 423: Ata Dma Address Register (Ata_Daddr)
ATA DMA word count. Indicates amount of words to transfer on the ATA DMA bus. COUNT 22.2.4 RTC Time Register (RTC_TIME) Chapter 26, “Real-Time Clock” for a detailed description of this register. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 22-3...
Page 424: Usb/Flexcan Clock Register (Usbcanclk)
A block diagram of how the devices are tied to this local bus is given in Figure 22-5. 16 kB RAM Arbiter USB Controller ATA DMA Controller ATA Controller Figure 22-5. ATA/USB Shared RAM Block Diagram MCF5253 Reference Manual, Rev. 1 22-4 Freescale Semiconductor...
Page 425: Endianness Issues
During the transfer, this address is autoincremented. The address is offset-0, so the value that needs to be programmed here is the result of the following equation: [(ColdFire cache RAM address) - (MBAR2 + 0x20000)]. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 22-5...
Page 426 ATA. 10. The DMA will end the transfer when the ATA_DCOUNT reaches zero. On DMA complete, a DMA interrupt is requested. MCF5253 Reference Manual, Rev. 1 22-6 Freescale Semiconductor...
Page 427: Advanced Technology Attachment Controller (Ata)
ATA interface. The ATA interface of the MCF5253 is an AT attachment host interface. Its main use is to interface with hard disc drives and optical disc drives. It interfaces with the ATA device over a number of ATA signals.
Page 428: Overview
ATA bus cycle by the ATA protocol engine. The IP bus cycle is stalled until completion of the ATA bus cycle on read, or until putting the write data on the ATA bus on write. MCF5253 Reference Manual, Rev. 1 23-2...
Page 429: Modes Of Operation
ATA bus pulls its DMARQ line high. During an ATA bus DMA transfer, data is transferred between the ATA bus and the FIFO. The transfer will pause to avoid FIFO overflow and FIFO underflow. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 23-3...
Page 430: External Signal Description
This signal is the ATA reset signal. When low, the ATA bus is in reset state. When high, no reset. The ATA bus is in reset whenever the appropriate bit in the control register is cleared. After system reset, the ATA bus is in reset. MCF5253 Reference Manual, Rev. 1 23-4 Freescale Semiconductor...
Page 431 This is the ATA data bus. 23.4.2 Electrical Spec on the ATA Bus, Bus Buffers To meet electrical spec on the ATA bus, several requirements must be met. For a detailed description, refer to the ATA specification. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 23-5...
Page 432: Timing Parameters
Max difference in buffer propagation delay for any of following signals: transceiver ATA_IORDY, ATA_Dx (read) tbuf Max buffer propagation delay transceiver tcable1 Cable propagation delay for ATA_Dx cable tcable2 Cable propagation delay for control signals: cable ATA_DIOR, ATA_DIOW, ATA_IORDY, ATA_DMACK MCF5253 Reference Manual, Rev. 1 23-6 Freescale Semiconductor...
Page 433: Pio Mode Timing
– t0(min) = (time_1 + time_2 + time_9) * T time_1, time_2r, time_9 Figure 23-2. In PIO write mode, timing waveforms are somewhat different. A timing diagram is given in Figure 23-3. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 23-7...
Page 434: Timing In Multiword Dma Mode
Avoid bus contention when switching buffer off by making toff long – enough Figure 23-3. 23.4.3.3 Timing in Multiword DMA Mode In multi-word DMA mode, see Figure 23-4 for read timing diagram and Figure 23-5 for write timing diagram. MCF5253 Reference Manual, Rev. 1 23-8 Freescale Semiconductor...
Page 435 = tco + tsu + tbuf + tbuf + tcable1 + tcable2 time_d tgr(min-drive) = td - te(drive) tf(read) tfr(min-drive) =0k – tg(write) – tg(min-write) = time_d * T -(tskew1 + tskew2 + tskew5) time_d MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 23-9...
Page 436: Udma In Timing Diagrams
UDMA in are provided. Figure 23-6 shows timing for UDMA in transfer start. Figure 23-6. UDMA in Transfer Start Timing Diagram Figure 23-7 shows timing for host terminating UDMA in transfer. MCF5253 Reference Manual, Rev. 1 23-10 Freescale Semiconductor...
Page 437 Figure 23-7. UDMA in Host Terminates Transfer Figure 23-8 shows timing for device terminating UDMA in transfer. Figure 23-8. UDMA in Device Terminates Transfer Timing parameters for UDMA in burst are listed in Table 23-6. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 23-11...
Page 438: Udma Out Timing Diagrams
UDMA Out Timing Diagrams UDMA mode timing is more complicated than PIO mode or MDMA mode. In this section, timing diagrams for UDMA out are provided. Figure 23-9 shows timing for UDMA out transfer start. MCF5253 Reference Manual, Rev. 1 23-12 Freescale Semiconductor...
Page 439 Figure 23-9. UDMA Out Transfer Start Timing Diagram Figure 23-10 shows timing for host terminating UDMA out transfer. Figure 23-10. UDMA Out Host Terminates Transfer Figure 23-11 shows timing for device terminating UDMA out transfer. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 23-13...
Page 440: Memory Map And Register Definitions
– toff toff = time_off * T - tskew1 23.5 Memory Map and Register Definitions Section 23.5.2, “Register Descriptions” on page 23-18 provides the detailed descriptions for all of the ATA registers. MCF5253 Reference Manual, Rev. 1 23-14 Freescale Semiconductor...
Page 441: Memory Map
0x01 23.5.2.2.19/23-24 (TIME_DVH) Controls tdvh Address TIME_DZFS UDMA timing parameter. 0x01 23.5.2.2.20/23-25 Controls tdzfs Address TIME_DVS UDMA timing parameter. 0x01 23.5.2.2.21/23-25 Controls tdvs Address TIME_CVH UDMA timing parameter. 0x01 23.5.2.2.22/23-25 Controls tcvh MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 23-15...
Page 442 MBAR2 + 0x8C8 DRIVE_CONTROL Drive control register Write-only 23.5.2.7/23-32 (DRIVE_CONTROL) Table 23-9 shows the ATA register summary. Table 23-9. ATA Register Summary Name TIME_OFF[7:0] MBAR2 + 0x800 (TIME_OFF) TIME_ON[7:0] MBAR2 + 0x801 (TIME_ON) MCF5253 Reference Manual, Rev. 1 23-16 Freescale Semiconductor...
Page 443 TIME_D[7:0] Address TIME_K[7:0] MBAR2 + 0x80D (TIME_ACK) TIME_ACK[7:0] Address TIME_ENV[7:0] Address TIME_RPX[7:0] Address TIME_ZAH[7:0] MBAR2 + 0x811 (TIME_MLIX) TIME_MLIX[7:0] MBAR2 + 0x812 (TIME_DVH) TIME_DVH[7:0] Address TIME_DZFS[7:0] Address TIME_DVS[7:0] Address TIME_CVH[7:0] Address TIME_SS[7:0] MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 23-17...
Page 444: Register Descriptions
(they remain same.) The few 16-bit and 32-bit registers represent strings of 2 or 4 bytes. The byte order in the 16-bit or 32-bit register is dependent on endianess selection. MCF5253 Reference Manual, Rev. 1 23-18...
Page 445: Timing Registers
Access: User read/write TIME_OFF[7:0] Reset Figure 23-12. TIME_OFF Register 23.5.2.2.2 TIME_ON Register Figure 23-13 for illustration of valid bits in the TIME_ON Register and Table 23-8 for description of the bit fields. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 23-19...
Page 446: Time_1 Register
TIME_2R Register and Table 23-8 for description of the bit fields. Address MBAR2 + 0x804 (TIME_2R) Access: User read/write TIME_2R[7:0] Reset Figure 23-16. TIME_2R Register MCF5253 Reference Manual, Rev. 1 23-20 Freescale Semiconductor...
Page 447: Time_Ax Register
Access: User read/write TIME_4[7:0] Reset Figure 23-19. TIME_4 Register 23.5.2.2.9 TIME_9 Register Figure 23-20 for illustration of valid bits in the TIME_9 Register and Table 23-8 for description of the bit fields. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 23-21...
Page 448: Time_M Register
TIME_D Register and Table 23-8 for description of the bit fields. Address MBAR2 + 0x80B (TIME_D) Access: User read/write TIME_D[7:0] Reset Figure 23-23. TIME_D Register MCF5253 Reference Manual, Rev. 1 23-22 Freescale Semiconductor...
Page 449: Time_K Register
Access: User read/write TIME_ENV[7:0] Reset Figure 23-26. TIME_ENV Register 23.5.2.2.16 TIME_RPX Register Figure 23-27 for illustration of valid bits in the TIME_RPX Register and Table 23-8 for description of the bit fields. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 23-23...
Page 450: 23.5.2.2.17 Time_Zah Register
TIME_DVH Register and Table 23-8 for description of the bit fields. Address MBAR2 + 0x812 (TIME_DVH) Access: User read/write TIME_DVH[7:0] Reset Figure 23-30. TIME_DVH Register MCF5253 Reference Manual, Rev. 1 23-24 Freescale Semiconductor...
Page 451: Time_Dzfs Register
Access: User read/write TIME_CVH[7:0] Reset Figure 23-33. TIME_CVH Register 23.5.2.2.23 TIME_SS Register Figure 23-34 for illustration of valid bits in the TIME_SS Register and Table 23-8 for description of the bit fields. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 23-25...
Page 452: 23.5.2.2.24 Time_Cyc Register
Figure 23-36. FIFO_Data Register In 16-bit Mode 23.5.2.3.2 FIFO_Data Register in 32-Bit Mode Figure 23-37 for illustration of valid bits in the FIFO_Data Register in 32-bit Mode and Table 23-8 description of the bit fields. MCF5253 Reference Manual, Rev. 1 23-26 Freescale Semiconductor...
Page 453: Fifo_Fill Register
FIFO_FILL is a read-only register. Any read to it returns the current number of halfwords present in the FIFO. 23.5.2.4 ATA_CONTROL Register Figure 23-39 for illustration of valid bits in the ATA Control Register and Table 23-10 for description of the bit fields. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 23-27...
Page 454: Interrupt Registers
1 IORDY handshake will be used 23.5.2.5 Interrupt Registers A group of three registers control the interrupt interface from the ATA module and going to the CPU and DMA. There are two interrupts controlled by these registers: MCF5253 Reference Manual, Rev. 1 23-28 Freescale Semiconductor...
Page 455 ATA bus. It is cleared when there is activity on the ATA bus. When the bit is set in the interrupt pending register, and the same bit is set in the interrupt enable register, ipbus_int will be active, signalling interrupt to the cpu. The interrupt clear register has no influence on this bit. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 23-29...
Page 456: Interrupt_Enable Register
ATA bus. It is cleared when there is activity on the ATA bus. When the bit is set in the interrupt pending register, and the same bit is set in the interrupt enable register, ipbus_int will be active, signalling interrupt to the cpu. The interrupt clear register has no influence on this bit. MCF5253 Reference Manual, Rev. 1 23-30 Freescale Semiconductor...
Page 457: Interrupt_Clear Register
4–0 Uncommitted 23.5.2.6 FIFO Alarm Register Figure 23-43 for illustration of valid bits in the FIFO_Alarm Register. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 23-31...
Page 458: Functional Description
ATA bus are swapped. No swaps occur in little endian mode, nor for any other register. 23.6 Functional Description The ATA interface provides two ways to communicate with the ATA peripherals connected to the ATA bus. MCF5253 Reference Manual, Rev. 1 23-32 Freescale Semiconductor...
Page 459: Resetting Ata Bus
To access the drive in PIO mode, simply read or write to the correct drive register. The bus cycle will be translated to an ATA cycle, and the drive is accessed. When drive registers are accessed while the ATA bus is in reset, the read or write is discarded, not done. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 23-33...
Page 460: Using Dma Mode To Receive Data From Ata Bus
The host can also wait unit the drive asserts ATA_INTRQ. This also indicates end of transfer. 9. On end of transfer, the host or host DMA should wait until controller_idle is set, and next read the remaining halfwords from the FIFO, and transfer these to memory. MCF5253 Reference Manual, Rev. 1 23-34 Freescale Semiconductor...
Page 461: Using Dma Mode To Transmit Data To Ata Bus
DMA transfer on the ATA bus. The nature of these commands is beyond the scope of this document. You should consult the ATA specification to know how to communicate with the drive. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 462 These reads will cause the running DMA to pause; after the read is completed, the DMA resumes. The host can also wait unit the drive asserts ATA_INTRQ. This also indicates end of transfer. On end of transfer, no extra FIFO manipulations are needed. MCF5253 Reference Manual, Rev. 1 23-36 Freescale Semiconductor...
Page 463: Features
Chapter 24 Universal Serial Bus Interface This chapter describes the universal serial bus (USB) interface of the MCF5253. The content includes the operation, signal descriptions, host data structures, and host operations. Also provided is the device operational model and deviations from the host mode of operation.
Page 464: Block Diagram
Host mode supports direct connect of FS/LS devices 24.2 Block Diagram The MCF5253 implements a USB OTG module. This module may be connected to one of two external ports. Collectively the module and external ports are called the USB interface. The USB interface is shown Figure 24-1.
Page 465: Modes Of Operation
Note that the USB Controller does not support Low speed operation in device mode as per USB 2.0 specification. 24.5.2 PHY Clocks The built-in PHY has its own on-chip oscillator and PLL to generate the USB serial clocks. The oscillator needs an external 24 MHz crystal. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-3...
Page 466: System Clock
MBAR2 + 0x75c TTCTRL—TT status and control 0x0000_0000 – MBAR2 + 0x760 BURSTSIZE—Programmable DMA Burst Size 0x0000_0404 24.6.3.10/24-26 MBAR2 + 0x764 TXFILLTUNING—Host TT Xmit Pre-buffer Packet Tuning 0x0000_0000 24.6.3.11/24-27 MBAR2 + 0x780 CONFIGFLAG—Configured Flag Register 0x0000_0001 24.6.3.12/24-29 MCF5253 Reference Manual, Rev. 1 24-4 Freescale Semiconductor...
Page 467: Module Identification Registers
The ID register provides a simple way to determine if the module is provided in the system. The ID register identifies the module and its revision. Figure 24-2 shows the ID register. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-5...
Page 468 Table 24-3. ID Register Field Descriptions Field Description 31–24 Reserved. 23–16 Revision number of the module. REVISION 15–14 Reserved. 13–8 Ones complement version of ID[5:0]. 7–6 Reserved. 5–0 Configuration number. This number is set to 0x05. MCF5253 Reference Manual, Rev. 1 24-6 Freescale Semiconductor...
Page 469: General Hardware Parameters (Hwgeneral) Register
UTMI (on-chip PHY). 5–4 PHY Width. This field is always reads 01 indicating that the UTMI interface width is 16-bits wide. PHYW Reserved. Reads as 0. 2–1 Reserved. Reads as 0b10. Reserved. Always 1. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-7...
Page 470: Host Hardware Parameters (Hwhost) Register
Always 1 indicating the module is host capable. 24.6.1.4 Device Hardware Parameters (HWDEVICE) Register—Non-EHCI This register is not defined in the EHCI specification. The HWDEVICE register provides the device hardware parameters for this implementation. MCF5253 Reference Manual, Rev. 1 24-8 Freescale Semiconductor...
Page 471: Transmit Buffer Hardware Parameters (Hwtxbuf) Register
HWTXBUF register. Address MBAR2 + 0x610 Access: User read R TXLC TXCHANADD Reset TXADD TXBURST Reset Figure 24-6. TX Buffer Hardware Parameters (HWTXBUF) Register Table 24-7 provides bit descriptions for the HWTXBUF register. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-9...
Page 472: Receive Buffer Hardware Parameters (Hwrxbuf) Register
Receive address. The number of address bits for the entire RX buffer. Always 0x5 (5). RXADD 7–0 Receive burst. Indicates the number of data beats in a burst for receive DMA data transfers. Always 0x4 (4). RXBURST MCF5253 Reference Manual, Rev. 1 24-10 Freescale Semiconductor...
Page 473: Capability Registers
Table 24-10 provides bit descriptions for the HCIVERSION register. Table 24-10. Host Controller Interface Version (HCIVERSION) Register Field Descriptions Field Name Description 15–0 – EHCI revision number. Value is 0x0100 indicating version 1.0. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-11...
Page 474: Host Controller Structural Parameters (Hcsparams)
The value of this field determines how many port registers are addressable in the operational register. Always 0x1. 24.6.2.4 Host Controller Capability Parameters (HCCPARAMS) This register identifies multiple mode control (time-base bit functionality) addressing capability. Figure 24-11 shows the HCCPARAMS register. MCF5253 Reference Manual, Rev. 1 24-12 Freescale Semiconductor...
Page 475 4K page boundary. This requirement ensures that the frame list is always physically contiguous. This field is always 1. 64-bit Addressing Capability. This field is always 0; 64-bit addressing is not supported. 0 Data structures use 32-bit address memory pointers MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-13...
Page 476: Device Controller Interface Version (Dciversion)
USB OTG module. Figure 24-13 shows the DCCPARAMS register. Address MBAR2 0x724 Access: User read Reset Reset Figure 24-13. Device Control Capability Parameters (DCCPARAMS) Register Table 24-14 provides bit descriptions for the DCCPARAMS register. MCF5253 Reference Manual, Rev. 1 24-14 Freescale Semiconductor...
Page 477: Operational Registers
USB Command Register (USBCMD) The module executes the command indicated in this register. Address MBAR2 0x740 Access: User read/write Reset FS2 ATDTW SUTW ASPE Reset Figure 24-14. USB Command Register (USBCMD) Register MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-15...
Page 478 The software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. This bit is used only in host mode. Writing a one to this bit when the USB OTG module is in device mode is selected will have undefined results. MCF5253 Reference Manual, Rev. 1 24-16 Freescale Semiconductor...
Page 479 The software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event. 1 Run. 0 Stop. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-17...
Page 480: Usb Status Register (Usbsts)
Run/Stop bit being set to 0, either by the software or by the Host Controller hardware (for example, internal error). Used only in host mode. 1 Halted. 0 Running. 11–9 Reserved. MCF5253 Reference Manual, Rev. 1 24-18 Freescale Semiconductor...
Page 481 The controller sets this bit to a one when it enters the full or high-speed operational state. When the it exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit and the DCSuspend bits respectively. This bit is not EHCI compatible. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-19...
Page 482: Usb Interrupt Enable Register (Usbintr)
Sleep Enable. This is a non-EHCI bit. When this bit is a one, and the DCSuspend bit in the USBSTS register transitions, the controller will issue an interrupt. The interrupt is acknowledged by the software writing a one to the DCSuspend bit. Used only in device mode. 1 Enable. 0 Disable. MCF5253 Reference Manual, Rev. 1 24-20 Freescale Semiconductor...
Page 483: Frame Index Register (Frindex)
Periodic Frame List during periodic schedule execution. The number of bits used for the index depends on the size of the frame list as set by the system software in the Frame List Size field in the USBCMD register. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 484 Table 24-19. FRINDEX N Values USBCMD[FS] Frame List Size FRINDEX N value 1024 elements (4096 bytes) 512 elements (2048 bytes) 256 elements (1024 bytes) 128 elements (512 bytes) MCF5253 Reference Manual, Rev. 1 24-22 Freescale Semiconductor...
Page 485: Control Data Structure Segment Register (Ctrldssegment)
8 elements (32 bytes) 24.6.3.5 Control Data Structure Segment Register (CTRLDSSEGMENT) The CTRLDSSEGMENT register is not implemented on the MCF5253. 24.6.3.6 Periodic Frame List Base Address Register (PERIODICLISTBASE) This register contains the beginning address of the Periodic Frame List in the system memory. The host controller driver loads this register prior to starting the schedule execution by the controller.
Page 486: Device Address Register (Deviceaddr), Non-Ehci
Note that on the USB OTG module, this register is shared between the host and device mode functions. In host mode, it is the ASYNCLISTADDR register; in device mode, it is the ENDPOINTLISTADDR register. See Section 24.6.3.9, “Endpoint List Address Register (ENDPOINTLISTADDR), Non-EHCI,” for more information. MCF5253 Reference Manual, Rev. 1 24-24 Freescale Semiconductor...
Page 487: Endpoint List Address Register (Endpointlistaddr), Non-Ehci
This register is shared between the host and device mode functions. In device mode, it is the ENDPOINTLISTADDR register; in host mode, it is the ASYNCLISTADDR register. See Section 24.6.3.8, “Current Asynchronous List Address Register (ASYNCLISTADDR),” for more information. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-25...
Page 488: Master Interface Data Burst Size Register (Burstsize)—Non-Ehci
(master) interface. Address MBAR2 0x760 Access: User read/write Reset TXPBURST RXPBURST Reset Figure 24-22. Master Interface Data Burst Size (BURSTSIZE) Register MCF5253 Reference Manual, Rev. 1 24-26 Freescale Semiconductor...
Page 489: Transmit Fifo Tuning Controls Register (Txfilltuning)—Non-Ehci
SOF. Too many back-off events can waste bandwidth and power on the system bus and thus should be minimized (not necessarily eliminated). Back-offs can be minimized with use of the TSCHHEALTH (T ) parameter described below. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-27...
Page 490 TXSCHHEALTH exceeds 10 per second, try raising the value by 1. If streaming mode is disabled via the USBMODE register, treat TXFIFOTHRES as the maximum value for purposes of the TXSCHOH calculation. MCF5253 Reference Manual, Rev. 1 24-28 Freescale Semiconductor...
Page 491: Configure Flag Register (Configflag)
It is also used to initiate test mode or force signaling and allows the software to put the PHY into low power suspend mode and disable the PHY clock. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-29...
Page 492 Port Force Full-speed Connect. This bit is used to disable the chirp sequence that allows the port to identify itself as a PFSC HS port. 0 Allow the port to identify itself as High Speed. 1 Force the port to connect only at Full-speed. This bit is not defined in the EHCI specification. MCF5253 Reference Manual, Rev. 1 24-30 Freescale Semiconductor...
Page 493 This feature is implemented in the host/OTG controller (PPC = 1). For the USB OTG module in a device-only implementation port power control is not necessary, thus PPC and PP = 0. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-31...
Page 494 This field is zero if Port Power(PP) is zero in host mode. For device mode: 1 Port in suspend state. 0 Port not in suspend state. Default. In device mode this bit is a read only status bit. MCF5253 Reference Manual, Rev. 1 24-32 Freescale Semiconductor...
Page 495 When the port is disabled, (0) downstream propagation of data is blocked except for reset. This field is zero if Port Power(PP) is zero in host mode. In Device Mode, the device port is always enabled. (This bit will be one). MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-33...
Page 496: On-The-Go Status And Control (Otgsc), Non-Ehci
The status inputs are de-bounced using a 1 msec time constant. Values on the status inputs that do not persist for more than 1 msec will not cause an update of the Status inputs, or cause and OTG interrupt. MCF5253 Reference Manual, Rev. 1 24-34...
Page 497 The software must write a one to clear this bit. 1 millisecond timer Interrupt Status. This bit is set once every millisecond. 1msS The software must write a one to clear this bit. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-35...
Page 498 0 A device Hardware assist B-disconnect to A-connect HABA 0 Disabled 1 Enable automatic B-disconnect to A-connect sequence Hardware assist data pulse HADP 0 No pulse sequence started 1 Start data pulse sequence Reserved. MCF5253 Reference Manual, Rev. 1 24-36 Freescale Semiconductor...
Page 499: Usb Mode Register (Usbmode)—Non-Ehci
This register is not defined in the EHCI specification. This register controls the operating mode of the module. Address MBAR2 + 0x7A8 Access: User read/write Reset SDIS SLOM Reset Figure 24-27. USB Mode (USBMODE) Register MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-37...
Page 500: Endpoint Setup Status Register (Endptsetupstat)—Non-Ehci
The USB OTG module defaults to the idle state and needs to be initialized to the desired operating mode after reset. 24.6.3.16 Endpoint Setup Status Register (ENDPTSETUPSTAT)—Non-EHCI This register is not defined in the EHCI specification. This register contains the endpoint setup status. It is used only in device mode. MCF5253 Reference Manual, Rev. 1 24-38 Freescale Semiconductor...
Page 501: Endpoint Initialization Register (Endptprime)—Non-Ehci
This register is not defined in the EHCI specification. This register is used to initialize endpoints. It is used by the USB OTG module only in device mode. Address MBAR2 + 0x7B0 Access: User read/write PETB Reset PERB Reset Figure 24-29. Endpoint Initialization (ENDPTPRIME) Register MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-39...
Page 502: Endpoint Flush Register (Endptflush), Non-Ehci
If a packet is in progress for one of the associated endpoints, then that transfer will continue until completion. The hardware will clear this register after the endpoint flush operation is successful. MCF5253 Reference Manual, Rev. 1 24-40...
Page 503: Endpoint Status Register (Endptstatus), Non-Ehci
USB reset, by the USB DMA system, or through the ENDPTFLUSH register. ERBR[3] (bit 3 of the register) corresponds to endpoint 3. Note: These bits will be momentarily cleared by the hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-41...
Page 504: Endpoint Complete Register (Endptcomplete), Non-Ehci
ERCE[3] (bit 3 of the register) corresponds to endpoint 3. 24.6.3.21 Endpoint Control Register 0 (ENDPTCTRL0), Non-EHCI This register is not defined in the EHCI specification. Every device will implement endpoint 0 as a control endpoint. MCF5253 Reference Manual, Rev. 1 24-42 Freescale Semiconductor...
Page 505 The software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by the software or it will automatically be cleared upon receipt of a new SETUP request. 1 Endpoint Stalled 0 Endpoint OK MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-43...
Page 506: Endpoint Control Register N (Endptctrln), Non-Ehci
Note: When only one endpoint (RX or TX, but not both) of an endpoint pair is used, the unused endpoint should be configured as a bulk type endpoint. TX endpoint data source. This bit should always be written as 0, which selects the Dual Port Memory/DMA Engine as the source. MCF5253 Reference Manual, Rev. 1 24-44 Freescale Semiconductor...
Page 507: Functional Description
It is responsible for moving all of the data to be transferred over the USB between the module and buffers in DMA cache memory. Like the system interface block the DMA engine block uses a simple synchronous bus signaling protocol. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-45...
Page 508: Fifo Ram Controller
Interrupt, Control, and Bulk data streams are managed via queue heads and Queue Element Transfer Descriptors. These data structures are optimized to reduce the total memory footprint of the schedule and to reduce (on average) the number of memory accesses needed to execute a USB transaction. MCF5253 Reference Manual, Rev. 1 24-46 Freescale Semiconductor...
Page 509: Periodic Frame List
Frame List Link pointers direct the host controller to the first work item in the frame’s periodic schedule for the current micro-frame. The link pointers are aligned on DWord boundaries within the Frame List. Figure 24-36 shows the format for the Frame List Link Pointer. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-47...
Page 510: Asynchronous List Queue Head Pointer
The Asynchronous list is a simple circular list of queue heads. The ASYNCLISTADDR register is simply pointer to the next queue head. This implements a pure round-robin service for all queue heads linked into the asynchronous list. MCF5253 Reference Manual, Rev. 1 24-48 Freescale Semiconductor...
Page 511: Isochronous (High-Speed) Transfer Descriptor (Itd)
31–5 Link Pointer These bits correspond to memory address signals [31–5], respectively. This field points to another Isochronous Transaction Descriptor (iTD/siTD) or Queue Head (QH). 4–3 – Reserved. These bits are reserved and their value has no effect on operation. The software should initialize this field to zero. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-49...
Page 512: Itd Transaction Status And Control List
1 one byte, 2 two bytes, etc.). The maximum value this field may contain is 0xC00 (3072). Interrupt on complete. If this bit is set, it specifies that when this transaction completes, the Host Controller should issue an interrupt at the next interrupt threshold. MCF5253 Reference Manual, Rev. 1 24-50 Freescale Semiconductor...
Page 513: Itd Buffer Page Pointer List (Plus)
This field is also used for all IN transfers to detect packet babble. The software should not set a value larger than 1024 (400h). Any value larger yields undefined results. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-51...
Page 514: Split Transaction Isochronous Transfer Descriptor (Sitd)
T 0x18 Figure 24-39. Split-Transaction Isochronous Transaction Descriptor (siTD) Host controller read/write; all others read-only. 24.8.4.1 Next Link Pointer DWord0 of a siTD is a pointer to the next schedule data structure. MCF5253 Reference Manual, Rev. 1 24-52 Freescale Semiconductor...
Page 515: Sitd Endpoint Capabilities/Characteristics
– Reserved. Bit is reserved for future use. It should be cleared. 6–0 Device Address This field selects the specific device serving as the data source or sink. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-53...
Page 516: Sitd Transfer State
This field is initialized by the software to the total number of bytes expected in this transfer. Maximum Transfer value is 1023 (3FFh) 15–8 µFrame Split complete progress mask. This field is used by the host controller to record which C-prog-mask split-completes have been executed. MCF5253 Reference Manual, Rev. 1 24-54 Freescale Semiconductor...
Page 517: Sitd Buffer Pointer List (Plus)
(as selected with the page indicator bit (P field)). The host controller is not required to write this field back when the siTD is retired (Active bit transitioned from a one to a zero). MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 518: Sitd Back Link Pointer
Host controller updates (host controller writes) to stand-alone qTDs only occur during transfer retirement. References in the following bit field definitions of updates to the qTD are to the qTD portion of a queue head. MCF5253 Reference Manual, Rev. 1 24-56 Freescale Semiconductor...
Page 519: Next Qtd Pointer
This field contains the physical memory address of the next qTD to be processed in the event that the qTD Pointer current qTD execution encounters a short packet (for an IN transaction). The field corresponds to memory address signals [31–5], respectively. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-57...
Page 520: Qtd Token
Current Page. This field is used as an index into the qTD buffer pointer list. Valid values are in the range 0x0 to 0x4. The host controller is not required to write this field back when the qTD is retired. MCF5253 Reference Manual, Rev. 1 24-58...
Page 521 01 IN Token generates token (69H) 10 SETUP Token generates token (2DH) (undefined if endpoint is an Interrupt transfer type, for example. µFrame S-mask field in the queue head is non-zero.) 11 Reserved. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-59...
Page 522 If the QH[EPS] field does not indicate a high-speed device, then this field is used as an error indicator bit. It is set by the host controller whenever a periodic split-transaction receives an ERR handshake. MCF5253 Reference Manual, Rev. 1 24-60 Freescale Semiconductor...
Page 523: Qtd Buffer Page Pointer List
Figure 24-41. Queue Head Layout Offsets 0x04 through 0x0B contain the static endpoint state. Host controller read/write; all others read-only. Offsets 0x10 through 0x2F contain the transfer overlay. Offsets 0x14 through 0x27 contain the transfer results. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-61...
Page 524: Queue Head Horizontal Link Pointer
USB2.0 Hub Transaction Translator. There are additional fields used for addressing the hub and scheduling the protocol transactions (for periodic). The host controller must not modify the bits in this region. MCF5253 Reference Manual, Rev. 1 24-62 Freescale Semiconductor...
Page 525 The value is the port number identifier on the USB 2.0 hub (for hub at device address Hub Addr below), below which the full- or low-speed device associated with this endpoint is attached. This information is used in the split-transaction protocol. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-63...
Page 526: Transfer Overlay
[31–5], respectively. 4–0 – Reserved. These bits are ignored by the host controller when using the value as an address to write data. The actual value may vary depending on the usage. MCF5253 Reference Manual, Rev. 1 24-64 Freescale Semiconductor...
Page 527: Periodic Frame Span Traversal Node (Fstn)
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 14 13 12 11 10 Normal Path Link Pointer T 0x00 Back Path Link Pointer T 0x04 Figure 24-42. Frame Span Traversal Node Structure MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-65...
Page 528: Ftsn Normal Path Pointer
The general operational model is for the USB modules in host mode is defined by the Enhanced Host Controller Interface (EHCI) Specification. The EHCI specification describes the register-level interface for a host controller for the USB Revision 2.0. It includes a description of the hardware/software interface MCF5253 Reference Manual, Rev. 1 24-66 Freescale Semiconductor...
Page 529: Host Controller Initialization
At this point, the port is active with SOFs occurring down the enabled port enabled High-speed ports, but the schedules have not yet been enabled. The EHCI host controller will not transmit SOFs to enabled Full- or Low-speed ports. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-67...
Page 530: Power Port
In this implementation, however, over-current is not reported to the USB core. Therefore the bits: Over-current Active and Over-current Change in the PORTSC register will be static. The over-current detection and limiting logic resides outside the MCF5253. The USB software stack is responsible for monitoring the Over-current condition on the external device.
Page 531: Port Suspend/Resume
Whenever a resume event is detected, the Port Change Detect bit in the USBSTS register is set. If the Port Change Interrupt Enable bit is a one in the USBINTR MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 532: Schedule Traversal Rules
The periodic frame list is an array of physical memory pointers. The objects referenced from the frame list must be valid schedule data structures as defined in Section 24.8, “Host Data Structures.” MCF5253 Reference Manual, Rev. 1 24-70 Freescale Semiconductor...
Page 533 ASYNCLISTADDR register. The software must set queue head horizontal pointer T-bits to a zero for queue heads in the asynchronous schedule. Section 24.9.9, “Asynchronous Schedule” for complete operational details. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-71...
Page 534: Periodic Schedule Frame Boundaries Vs. Bus Frame Boundaries
To aid the presentation, two terms are defined. The host controller's view of the 1-millisecond boundaries is called H-Frames. The high-speed bus's view of the 1-millisecond boundaries is called B-Frames. MCF5253 Reference Manual, Rev. 1 24-72 Freescale Semiconductor...
Page 535 FRINDEX[2:0] and incrementing SOFV based on the transition of 0 to 1 of FRINDEX[2:0]. The software is allowed to write to FRINDEX. Section 24.6.3.4, “Frame Index Register (FRINDEX),” provides the requirements that the software should adhere when writing a new value in FRINDEX. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-73...
Page 536: Periodic Schedule
Interrupt queue heads are linked into the frame list ordered by poll rate. Longer poll rates are linked first (for example, closest to the periodic frame list), followed by shorter poll rates, with queue heads with a poll rate of one, on the very end. MCF5253 Reference Manual, Rev. 1 24-74 Freescale Semiconductor...
Page 537: Managing Isochronous Transfers Using Itds
When the indexed active bit is a one the host controller continues to parse the iTD. It stores the indexed transaction description and the general endpoint information (device address, endpoint number, maximum MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-75...
Page 538 Detected bit and clear the Active bit. Note, that the host controller is not required to update the iTD field Transaction n Length in this error scenario. If the Mult field is greater than one, then the host controller MCF5253 Reference Manual, Rev. 1 24-76...
Page 539: Software Operational Model For Itds
If the buffer is large, then the system software can use a small set of iTDs to service the entire buffer. The system software can activate the transaction description records (contained in each iTD) in any pattern required for the particular data stream. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-77...
Page 540: Periodic Scheduling Threshold
(relative to the current location of the host controller execution in the periodic list) and still have the host controller process them. MCF5253 Reference Manual, Rev. 1 24-78 Freescale Semiconductor...
Page 541: Asynchronous Schedule
ASYNCLISTADDR register to get the next queue head. The Asynchronous Schedule Status bit in the USBSTS register indicates status of the asynchronous schedule. The system software enables (or disables) the asynchronous schedule by writing a one (or zero) MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-79...
Page 542: Adding Queue Heads To Asynchronous Schedule
This is a software requirement section. There are two independent events for adding queue heads to the asynchronous schedule. The first is the initial activation of the asynchronous list. The second is inserting a new queue head into an activated asynchronous list. MCF5253 Reference Manual, Rev. 1 24-80 Freescale Semiconductor...
Page 543: Removing Queue Heads From Asynchronous Schedule
-- schedule. Software provides this pointer with the -- following strict rules: -- if the host software is one queue head, then -- pQHeadNext must be the same as -- QueueheadToUnlink.HorizontalPointer. If the host MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-81...
Page 544 (A & B). It is sufficient that the host controller can set the status bit (and clear the doorbell bit) as soon as it has traversed beyond current reachable schedule information (that is, traversed beyond queue head (B) in this example). MCF5253 Reference Manual, Rev. 1 24-82 Freescale Semiconductor...
Page 545: Empty Asynchronous Schedule Detection
If the controller ever encounters an H-bit of one and a Reclamation bit of zero, the controller simply stops traversal of the asynchronous schedule. An example illustrating the H-bit in a schedule is shown in Figure 24-50. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-83...
Page 546: Asynchronous Schedule Traversal: Start Event
This section presents an overview of how the host controller interacts with queuing data structures. Queue heads use the Queue Element Transfer Descriptor (qTD) structure defined in Section 24.8.5, “Queue Element Transfer Descriptor (qTD).” MCF5253 Reference Manual, Rev. 1 24-84 Freescale Semiconductor...
Page 547: Buffer Pointer List Use For Data Streaming With Qtds
4K page. The final portion, which may only be large enough to occupy a portion of a page, must start at the top of the page and be contiguous within that page. Figure 24-51 illustrates these requirements. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-85...
Page 548 The transactions continue for the rest of the buffer, with the host controller automatically moving to the next page pointer (that is, C_Page) when necessary. There are three conditions for how the host controller handles C_Page. MCF5253 Reference Manual, Rev. 1 24-86 Freescale Semiconductor...
Page 549: Adding Interrupt Queue Heads To The Periodic Schedule
The system software may set IOC's to occur more frequently. A motivation for this may be that it wants early notification so that interface data structures can be re-used in a timely manner. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-87...
Page 550: Ping Control
The host controller preserves the Ping State bit across all queue advancements. This means that when a new qTD is written into the queue head overlay area, the previous value of the Ping State bit is preserved. MCF5253 Reference Manual, Rev. 1 24-88 Freescale Semiconductor...
Page 551: Split Transactions
XactErr of Complete-Split (CERR) !XactErr .and. .and. !NYET Endpoint Active PidCode .eq. SETUP .and. !Stall Set XactErr Bit and Decrement Error Count (CERR) Figure 24-52. Host Controller Asynchronous Schedule Split-Transaction State Machine MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-89...
Page 552: Asynchronous—Do-Start-Split
• STALL. The target endpoint responded with a STALL handshake. The host controller sets the halt bit in the status byte, retires the qTD but does not attempt to advance the queue. MCF5253 Reference Manual, Rev. 1 24-90 Freescale Semiconductor...
Page 553: Split Transaction Interrupt
EHCI periodic schedule and queue head data structure. The S and C labels indicate micro-frames where the software can schedule start-splits and complete splits (respectively). MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-91...
Page 554 The system software cannot build an efficient schedule that satisfies this requirement unless it uses FSTNs. Figure 24-54 illustrates the general layout of the periodic schedule. MCF5253 Reference Manual, Rev. 1 24-92 Freescale Semiconductor...
Page 555 SplitXState indicates Do_Start, and the current micro-frame as indicated by FRINDEX[2:0] is 0, then execute a start-split transaction. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-93...
Page 556: Host Controller Operational Model For Fstns
• When a QH's EPS field indicates a Full/Low-speed device, the host controller only considers it for execution if its SplitXState is DoComplete (note: this applies whether the PID Code indicates an MCF5253 Reference Manual, Rev. 1 24-94 Freescale Semiconductor...
Page 557 In frame N+1 (micro-frames 0 and 1), when the host controller encounters Save-Path FSTN (Save-N), it observes that Save-N.Back Path Link Pointer.T-bit is zero (definition of a Save-Path indicator). The host controller saves the value of Save-N. Normal Path Link Pointer and follows Save-N.Back Path Link MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-95...
Page 558: Software Operational Model For Fstns
Save-Place FSTN from one poll rate level to another. During the transition, the software must preserve the integrity of the previous schedule until the new schedule is in place. MCF5253 Reference Manual, Rev. 1 24-96 Freescale Semiconductor...
Page 559: Tracking Split Transaction Progress For Interrupt Transfers
It is calculated from the three least significant bits of the FRINDEX register (that is, cMicroFrameBit = (1 shifted-left(FRINDEX[2:0]))). The cMicroFrameBit has at most one bit asserted, which always MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-97...
Page 560: Periodic Interrupt—Do-Start-Split
This is the state the software must initialize a full- or low-speed interrupt queue head StartXState bit. This state is entered from the Do_Complete Split state only after the split transaction is complete. MCF5253 Reference Manual, Rev. 1 24-98 Freescale Semiconductor...
Page 561: Periodic Interrupt—Do-Complete-Split
-- Return values: -- TRUE - no error -- FALSE - error Boolean rvalue = TRUE; previousBit = cMicroframeBit logical-rotate-right(1) -- Bit-wise anding previousBit with C-mask indicates -- whether there was an intent MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-99...
Page 562 NYET response from the transaction translator. Do not update any transfer state (except for C-prog-mask and FrameTag) and stay in this state. The host controller must not adjust Cerr on this response. MCF5253 Reference Manual, Rev. 1 24-100 Freescale Semiconductor...
Page 563 The other possible combinations of tests A, B, C, and D may indicate that data or response was lost. Table 24-67 lists the possible combinations and the appropriate action. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-101...
Page 564: Managing The Qh[Frametag] Field
Rule 3: If transitioning from Do_Start Split to Do Complete Split and the current value of FRINDEX[2:0] is not 6, or currently in Do Complete Split and the current value of (FRINDEX[2:0]) is not 7, FrameTag is set to FRINDEX[7:3]. This accommodates all other cases Figure 24-53. MCF5253 Reference Manual, Rev. 1 24-102 Freescale Semiconductor...
Page 565: Rebalancing The Periodic Schedule
This simple arrangement allows a single isochronous scheduling model and adds the additional feature that all data received from the endpoint (per split transaction) must land into a contiguous buffer. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-103...
Page 566: Split Transaction Scheduling Mechanisms For Isochronous
Case 2b: Start & Complete in H-Frame, Micro-Frame 0 HS/FS/LS Bus Micro-Frame B-Frame N–1 B-Frame N B-Frame N+1 H-Frame N H-Frame N+1 siTD siTD Figure 24-57. Split Transaction, Isochronous Scheduling Boundary Conditions MCF5253 Reference Manual, Rev. 1 24-104 Freescale Semiconductor...
Page 567 Back Pointer. This field in a siTD is used to complete an IN split-transaction using the previous H-Frame's siTD. This is only used when the scheduling of the complete-splits span an H-Frame boundary. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-105...
Page 568 (not shown). The complete-splits to extract this data must use the buffer pointer from siTD . The only way for the host controller to reach siTD from H-Frame is to use siTD 's back pointer. MCF5253 Reference Manual, Rev. 1 24-106 Freescale Semiconductor...
Page 569: Tracking Split Transaction Progress For Isochronous Transfers
As with split transaction Interrupt, it is the host controller's responsibility to detect when it has missed an opportunity to execute a complete-split. The MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 570 (for example, state not advanced) and report the appropriate error to the client driver. MCF5253 Reference Manual, Rev. 1 24-108 Freescale Semiconductor...
Page 571: Split Transaction Execution State Machine For Isochronous
Each time the host controller reaches an active siTD in this state, it checks the siTD[S-mask] against cMicroFrameBit. If there is a one in the appropriate position, the siTD executes a start-split transaction. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 572 T-count starts greater than 3. Transition from MID to END. This case can occur for any of the scheduling boundary cases where the T-count starts greater than 2. MCF5253 Reference Manual, Rev. 1 24-110 Freescale Semiconductor...
Page 573: Periodic Isochronous—Do Complete Split
Test A. cMicroFrameBit is bit-wise ANDed with the siTD[C-mask] field. A non-zero result indicates that the software scheduled a complete-split for this endpoint, during this micro-frame. This test is always applied to a newly fetched siTD that is in this state. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-111...
Page 574 Bytes To Transfer]) MDATA and DATA0/1 data payloads up to and including 192 bytes. The host controller may optionally clear siTD[Status-Active] and set siTD[Status-Babble Detected] when it receives MDATA or DATA0/1 with a data payload of more than 192 bytes. MCF5253 Reference Manual, Rev. 1 24-112 Freescale Semiconductor...
Page 575 If Test A succeeds, but Test B fails, it means that one or more of the complete-splits have been skipped. The host controller sets the Missed Micro-Frame status bit and clears the Active bit. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 576: Complete-Split For Scheduling Boundary Cases 2A, 2B
SplitXState to Do Start Split. The host controller then determines whether the case 2b start split boundary condition exists (that is, if cMicroframeBit is 1 and siTD [S-mask[0]] is 1). If this criterion MCF5253 Reference Manual, Rev. 1 24-114 Freescale Semiconductor...
Page 577: Split Transaction For Isochronous—Processing Examples
S-masks of all siTDs for this endpoint have a value of 0x10 (a one bit in micro-frame 4) and C-mask value of 0xC3 (one-bits in micro-frames 0,1, 6 and 7). Additionally, the software ensures that the Back MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 578: Port Test Modes
Clear the Run/Stop bit in the USBCMD register and wait for the HCHalted bit in the USBSTS register, to transition to a one. Note that an EHCI host controller implementation may optionally MCF5253 Reference Manual, Rev. 1 24-116 Freescale Semiconductor...
Page 579: Interrupts
(via an OS-specific mechanism), schedules a deferred procedure call (DPC) which will execute later. The DPC routine processes the results of the schedule execution. The precise mechanisms used are beyond the scope of this document. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-117...
Page 580: Transfer/Transaction Based Interrupts
In general, this is called a Packet Babble. When a device sends more data than the Maximum Length number of bytes, the host controller sets the Babble Detected bit to a one and halts MCF5253 Reference Manual, Rev. 1 24-118...
Page 581: Data Buffer Error
Simply truncating the packet is not considered acceptable. An acceptable implementation option is to 1's complement the CRC bytes and send them. There are other options suggested in the Transaction Translator section of the USB Specification Revision 2.0. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-119...
Page 582: Usb Interrupt (Interrupt On Completion (Ioc))
Interrupt on Async Advance Doorbell bit in the USBCMD register. If it is set, it sets the Interrupt on Async MCF5253 Reference Manual, Rev. 1 24-120...
Page 583: Host System Error
Device Controller Driver (DCD) software and the Device Controller. The data structure definitions in this chapter support a 32-bit memory buffer address space. The interface consists of device Queue Heads and Transfer Descriptors. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-121...
Page 584: Endpoint Queue Head
The device Endpoint Queue Head (dQH) is where all transfers are managed. The dQH is a 48-byte data structure, but must be aligned on 64-byte boundaries. During priming of an endpoint, the dTD (device MCF5253 Reference Manual, Rev. 1 24-122...
Page 585: Endpoint Capabilities/Characteristics
01 Execute 1 Transaction. 10 Execute 2 Transactions. 11 Execute 3 Transactions. Note: Non-ISO endpoints must set Mult = 00. Note: ISO endpoints must set Mult = 01, 10, or 11 as needed. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-123...
Page 586: Transfer Overlay
The set-up buffer is dedicated storage for the 8-byte data that follows a set-up PID. NOTE Each endpoint has a TX and an RX dQH associated with it, and only the RX queue head is used for receiving setup data packets. MCF5253 Reference Manual, Rev. 1 24-124 Freescale Semiconductor...
Page 587: Endpoint Transfer Descriptor (Dtd)
Terminate (T). 1=pointer is invalid. 0=Pointer is valid (points to a valid Transfer Element Descriptor). This bit indicates to the Device Controller that there are no more valid entries in the queue. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-125...
Page 588 Device Controller software. This field contains the status of the last transaction performed on this qTD. The bit encodings are: Status Field Description Active. Halted. Data Buffer Error. Transaction Error. 4,2,0 Reserved. MCF5253 Reference Manual, Rev. 1 24-126 Freescale Semiconductor...
Page 589: Device Operational Model
4. Configure ENDPOINTLISTADDR Pointer. For additional information on ENDPOINTLISTADDR, refer Table 24-23. 5. Enable the microprocessor interrupt associated with the USB OTG and optionally change setting of ITC field in USBCMD register. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-127...
Page 590: Port State And Control
Appendix C.2 of the USB Specification Rev. 2.0. The following state diagram depicts the state of a USB 2.0 device. MCF5253 Reference Manual, Rev. 1 24-128...
Page 591 Software Only State Figure 24-63. USB 2.0 Device States States powered, attach, defaultFS/HS, suspendFS/HS are implemented in the USB_DR and are communicated to the DCD using the status bits identified in Table 24-79. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-129...
Page 592: Bus Reset
DCD is processing a USB reset event, then it is likely that no dTDs have been allocated. At this time, the DCD may release control back to the OS because no further changes to the device controller are permitted until a Port Change Detect is indicated. MCF5253 Reference Manual, Rev. 1 24-130 Freescale Semiconductor...
Page 593: Suspend/Resume
PORTSCn while the device is in suspend state. Sending resume signal to an upstream port should cause the host to issue resume signaling and bring the suspended bus segment (one more devices) back to the active condition. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-131...
Page 594: Managing Endpoints
ENDPTCTRLn register otherwise the behavior is undefined. Table 24-81 shows how to construct a configuration word for endpoint initialization. Table 24-81. Device Controller Endpoint Initialization Field Value Data Toggle Reset Data Toggle Inhibit MCF5253 Reference Manual, Rev. 1 24-132 Freescale Semiconductor...
Page 595: Stalling
The DCD may reset the data toggle state bit and cause the data toggle sequence to reset in the device controller by writing a '1' to the data toggle reset bit in the ENDPTCTRLn register. This should only be necessary when configuring/initializing an endpoint or returning from a STALL condition. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-133...
Page 596: Data Toggle Inhibit
Since only the leading data is stored in the device controller FIFO, it is necessary for the device controller to begin filling in behind leading data after the transaction starts. The FIFO must be sized to account for the maximum latency that can be incurred by the system memory bus. MCF5253 Reference Manual, Rev. 1 24-134 Freescale Semiconductor...
Page 597: Priming Receive Endpoints
Bytes (dTD) Max. Packet Length (dQH) – – – – NOTE The MULT field in the dQH must be set to ‘00’ for bulk, interrupt, and control endpoints. TX-dTD is complete when: MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-135...
Page 598: Interrupt/Bulk Endpoint Bus Response Matrix
NYET/ACK— NYET unless the Transfer Descriptor has packets remaining according to the USB variable length protocol then ACK. SYSERR—System error should never occur when the latency FIFOs are correctly sized and the DCD is responsive. MCF5253 Reference Manual, Rev. 1 24-136 Freescale Semiconductor...
Page 599: Control Endpoint Operation Model
ENDPTPRIME register is zero and the associated bit in the ENDPTSTATUS register is a one. If a prime fails, that is, The ENDPTPRIME bit goes to zero and the ENDPTSTATUS bit MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 600: Status Phase
SYSERR—System error should never occur when the latency FIFOs are correctly sized and the DCD is responsive. Force Bit Stuff Error. NYET/ACK—NYET unless the Transfer Descriptor has packets remaining according to the USB variable length protocol then ACK. MCF5253 Reference Manual, Rev. 1 24-138 Freescale Semiconductor...
Page 601: Isochronous Endpoint Operational Model
Transaction Error bit and the data is stored as usual for the application software to sort out. • TX Packet Retired — MULT counter reaches zero. — Fulfillment Error [Transaction Error bit is set] — #Packets Occurred > 0 AND # Packets Occurred < MULT MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-139...
Page 602: Isochronous Pipe Synchronization
24.11.3.6.2 Isochronous Endpoint Bus Response Matrix Table 24-87. Isochronous Endpoint Bus Response Matrix Stall Not Primed Primed Underflow Overflow STALL STALL STALL Setup NULL NULL Packet Transmit BS Error Packet Ignore Ignore Receive Drop Packet MCF5253 Reference Manual, Rev. 1 24-140 Freescale Semiconductor...
Page 603: Managing Queue Heads
Transfers”, the dQH also contains the following parameters for the associated endpoint: Multipler, Maximum Packet Length, Interrupt On Setup. The complete initialization of the dQH including these fields is demonstrated in the next section. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-141...
Page 604: Queue Head Initialization
Write the Active bit in the status field to ‘0.’ • Write the Halt bit in the status field to ‘0.’ NOTE The DCD must only modify dQH if the associated endpoint is not primed and there are no outstanding dTD's. MCF5253 Reference Manual, Rev. 1 24-142 Freescale Semiconductor...
Page 605: Operational Model For Setup Transfers
To conserve memory, the reserved fields at the end of the dQH can be used to store the Head and Tail pointers but it still remains the responsibility of the DCD to maintain the pointers. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-143...
Page 606: Building A Transfer Descriptor
1. Write dQH next pointer AND dQH terminate bit to 0 as a single DWord operation. 2. Clear active and halt bit in dQH (in case set from a previous error). 3. Prime endpoint by writing '1' to correct bit position in ENDPTPRIME. MCF5253 Reference Manual, Rev. 1 24-144 Freescale Semiconductor...
Page 607: Transfer Completion
For Transmit packets, a packet is only complete after the actual bytes reaches zero, but for receive packets, the host may send fewer bytes in the transfer according the USB variable length packet protocol. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-145...
Page 608: Flushing/De-Priming An Endpoint
Device Controller to cease data transfers on the pipe for one (micro)frame. During the ‘dead’(micro)frame, the Device Controller reports error on the pipe and primes for the following frame. MCF5253 Reference Manual, Rev. 1 24-146 Freescale Semiconductor...
Page 609: Servicing Interrupts
USB Interrupt (w/ ENDPTCOMPLETE). System Error Unrecoverable error. Immediate Reset of core; free transfers buffers in progress and restart the DCD. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-147...
Page 610: Deviations From The Ehci Specifications
Section 24.6.2.3, “Host Controller Structural Parameters (HCSPARAMS)” for usage information. 24.12.1.2 Operational Registers The addition of two-bit Port Speed (PSPD) to the PORTSCn register is added to the operational registers to support the embedded TT: MCF5253 Reference Manual, Rev. 1 24-148 Freescale Semiconductor...
Page 611: Discovery
LS traffic. Maximum Packet Size must be less than or equal 64 or undefined behavior may result. 2. siTD (for direct attach FS) – Periodic (ISO Endpoint) MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-149...
Page 612: Operational Model
HS hub, the start/complete split operation is simple an internal operation to the embedded Transaction Translator. Table 24-94 summarizes the conditions where handshakes are emulated from internal state instead of actual handshakes to HS split bus traffic. MCF5253 Reference Manual, Rev. 1 24-150 Freescale Semiconductor...
Page 613: Asynchronous Transaction Scheduling And Buffer Management
The option to limit the tracking to only 4 periodic data pipes exists in the by changing the configuration constant VUSB_HS_TT_PERIODIC_CONTEXTS to 4. The result is a significant gate count savings to the core given the limitations implied. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-151...
Page 614: Multiple Transaction Translators
Note that the free running interrupt is shared with the device-mode start-of-frame interrupt. See Section 24.6.3.2, “USB Status MCF5253 Reference Manual, Rev. 1 24-152 Freescale Semiconductor...
Page 615: Embedded Design
• [Port Change Interrupt] Port enable change occurs to notify the host controller that the device in now operational and at this point the port speed has been determined. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 24-153...
Page 616: Port Speed Detection
• Port Owner is read-only and always reads 0. • A 2-bit Port Speed indicator in PORTSC register provides the current operating speed of the port to the host controller driver. MCF5253 Reference Manual, Rev. 1 24-154 Freescale Semiconductor...
Page 617: Features
Chapter 25 FlexCAN Module This chapter discusses the modes of operation, signals, memory map, register descriptions, and the functional and initialization sequence of the FlexCAN controller of the MCF5253. 25.1 Features Following are the main features of the FlexCAN module: •...
Page 618: Overview
(such as fiber optic cable or an unshielded twisted pair of wires). The FlexCAN supports both the standard and extended identifier (ID) message formats specified in the CAN protocol specification, revision 2.0, part B. MCF5253 Reference Manual, Rev. 1 25-2 Freescale Semiconductor...
Page 619: The Can System
CAN protocol functions are enabled. User and supervisor modes differ in the access to some restricted control registers. 25.3.2.2 Freeze Mode Freeze mode is entered by setting: • CANMCR n [FRZ], and • CANMCR n [HALT], or by asserting the BKPT signal. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 25-3...
Page 620: Module Disabled Mode
(logic 1). FlexCAN behaves as it normally does when transmitting and treats its own transmitted message as a message received from a remote node. In this mode, FlexCAN MCF5253 Reference Manual, Rev. 1 25-4...
Page 621: Listen-Only Mode
Free Running Timer (TIMERn) 0x0000_0000 25.5.3/25-11 0x2008 0x1010 Rx Global Mask (RXGMASKn) 0x1FFF_FFFF 25.5.4/25-11 0x2010 0x1014 Rx Buffer 14 Mask (RX14MASkn) 0x1FFF_FFFF 25.5.4/25-11 0x2014 0x1018 Rx Buffer 15 Mask (RX15MASKn) 0x1FFF_FFFF 25.5.4/25-11 0x2018 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 25-5...
Page 622: Flexcan Configuration Register (Canmcrn)
Most of the fields in this register can be accessed at any time, except the MAXMB field, which should only be changed while the module is in freeze mode. MCF5253 Reference Manual, Rev. 1 25-6 Freescale Semiconductor...
Page 623 FlexCAN exits these modes. 0 FlexCAN is either in normal mode, listen-only mode, or loop-back mode. h1FlexCAN is in disable or freeze mode. Reserved, should be cleared. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 25-7...
Page 624: Flexcan Control Register (Canctrln)
Exceptions are the BOFFMSK, ERRMSK, and BOFFREC bits, which can be accessed at any time. MCF5253 Reference Manual, Rev. 1 25-8 Freescale Semiconductor...
Page 625 Clock source. Selects the clock source for the CAN interface to be fed to the prescalar. This bit should only be CLK_SRC changed while the module is disabled. 0 Clock source is CRIN 1 Clock source is the internal bus clock, SYSCLK MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 25-9...
Page 626 Propagation segment. Defines the length of the propagation segment in the bit time. The valid programmable PROPSEG values are 0–7. Propagation segment time (PROPSEG + 1) time-quanta Note: A time-quantum = 1 S clock period. MCF5253 Reference Manual, Rev. 1 25-10 Freescale Semiconductor...
Page 627: Flexcan Free Running Timer Register (Timern)
(only while in freeze mode), as locked frames that matched a message buffer (MB) through a mask may be transferred into the MB (upon release) but may no longer match. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 25-11...
Page 628 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Standard ID Extended ID Reset 0 Figure 25-7. FlexCAN Rx Mask (RXGMASKn, RX14MASKn, RX15MASKn) Registers MCF5253 Reference Manual, Rev. 1 25-12 Freescale Semiconductor...
Page 629: Flexcan Error Counter Register (Errcntn)
(indicated by the ERRSTAT n [ACKERR] bit). After the transition to error-passive state, the TXECTR does not increment anymore by acknowledge errors. Therefore, the device never goes to the bus off state. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 25-13...
Page 630: Flexcan Error And Status Register (Errstatn)
1 to them. Writing 0 has no effect. Refer to Section 25.7.1, “Interrupts.” Offset MBAR2 0x1020 (CANCTRL0) Access: User read/write MBAR2 0x2020 (CANCTRL1) Reset R BIT1 BIT0 IDLE TXRX BOFF CONF Reset Figure 25-9. FlexCAN Error and Status (ERRSTATn) Register MCF5253 Reference Manual, Rev. 1 25-14 Freescale Semiconductor...
Page 631 CANCTRLn[LOM] bit is set, FLTCONF will indicate error-passive. Since the CANCTRLn register is not affected by soft reset, the FLTCONF field will not be affected by soft reset if the LOM bit is set. 00 Error active 01 Error passive 1x Bus off Reserved, should be cleared. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 25-15...
Page 632: Interrupt Mask Register (Imaskn)
IFLAG n bit and, if the corresponding IMASK n bit is set, will generate an interrupt. The interrupt flag is cleared by writing a 1, while writing 0 has no effect. MCF5253 Reference Manual, Rev. 1 25-16 Freescale Semiconductor...
Page 633: Message Buffer Structure
0x2000). The 512-byte message buffer space is fully used by the 32 message buffer structures. Each message buffer consists of a control and status field that configures the message buffer, an identifier field for frame identification, and up to 8 bytes of data. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 25-17...
Page 634 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7 Figure 25-13. Message Buffer Structure Register for Both Extended and Standard Frames MCF5253 Reference Manual, Rev. 1 25-18 Freescale Semiconductor...
Page 635 Data field. Up to eight bytes can be used for a data frame. For Rx frames, the data is stored as it is received from 23–16, the CAN bus. For Tx frames, the CPU provides the data to be transmitted within the frame. 15–8, 7–0 DATA MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 25-19...
Page 636 Data frame to be transmitted once, unconditionally. After transmission, the MB automatically returns to the INACTIVE state. 1100 0100 Remote frame to be transmitted unconditionally once, and message buffer becomes an Rx message buffer with the same ID for data frames. MCF5253 Reference Manual, Rev. 1 25-20 Freescale Semiconductor...
Page 637: Functional Overview
The CPU prepares or changes an MB for transmission by writing the following: 1. Control/status word to hold Tx MB inactive (CODE = 1000) 2. ID word 3. Data bytes 4. Control/status word (active CODE, LENGTH) NOTE The first and last steps are mandatory. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 25-21...
Page 638: Arbitration Process
The CPU prepares or changes an MB for frame reception by writing the following: 1. Control/status word to hold Rx MB inactive (CODE = 0000) 2. ID word 3. Control/status word to mark the Rx MB as active and empty (CODE = 1000) MCF5253 Reference Manual, Rev. 1 25-22 Freescale Semiconductor...
Page 639: Self-Received Frames
FlexCAN MB, then the frame will be received by the FlexCAN. Such a frame is a self-received frame. Note that FlexCAN does not receive frames transmitted by itself if another device on the CAN bus has an ID that matches the FlexCAN Rx MB ID. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 25-23...
Page 640: Matching Process
Any CPU write access to the C/S word of an MB causes that MB to be excluded from the transmit or receive processes during the current matching or arbitration round. This mechanism is called MB deactivation. It is temporary, affecting only for the current match/arbitration round. MCF5253 Reference Manual, Rev. 1 25-24 Freescale Semiconductor...
Page 641: Locking And Releasing Message Buffers
ID is locked, the last received frame with that ID is kept within the serial message buffer, while all preceding ones are lost. There is no indication of lost messages when this occurs. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 642: Can Protocol Related Frames
CAN bus. These conditions include detection of a dominant bit in the following: • First or second bit of intermission • Seventh (last) bit of the end-of-frame (EOF) field in receive frames MCF5253 Reference Manual, Rev. 1 25-26 Freescale Semiconductor...
Page 643: Time Stamp
SYNC_SEG: Has a fixed length of one time quantum. Signal edges are expected to happen within this section. 1. For further explanation of the underlying concepts please refer to ISO/DIS 11519–1, Section 10.3. Reference also the Bosch CAN 2.0A/B protocol specification dated September 1991 for bit timing. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 25-27...
Page 644 It is the user’s responsibility to ensure the bit time settings are in compliance with the CAN standard. For bit time calculations, use an IPT (Information Processing Time) of 2, which is the value implemented in the FlexCAN module MCF5253 Reference Manual, Rev. 1 25-28 Freescale Semiconductor...
Page 645: Flexcan Initialization Sequence
1. Initialize all operation modes in the CANCTRL n register. a) Initialize the bit timing parameters PROPSEG, PSEGS1, PSEG2, and RJW. b) Select the S-clock rate by programming the PRESDIV field. c) Select the internal arbitration mode via the LBUF bit. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor 25-29...
Page 646: Interrupts
MB caused the interrupt. The other interrupt source (wired OR of bus off and error) acts in the same way, located in the ERRSTAT n register. The bus off and error interrupt mask bits are located in the CANCTRL n register. MCF5253 Reference Manual, Rev. 1 25-30 Freescale Semiconductor...
Page 647: Block Diagram
This chapter provides the external signal descriptions, memory map, register descriptions, and functional descriptions of the Real-Time Clock module of the MCF5253. The real time clock (RTC) is a mixed-signal circuit which provides an indicator of time (in seconds) for various purposes in the system.
Page 648 To indicate the real-time clock has been in low battery state, it will set the RTC_POWER_LOSS status bit in the ATA-DMA configuration register. This bit will remain set, until the user sets the RTC_CLEAR bit in the ATA-DMA configuration register. MCF5253 Reference Manual, Rev. 1 26-2 Freescale Semiconductor...