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NXP Semiconductors freescale MC92604 User Manual

NXP Semiconductors freescale MC92604 User Manual

Dual get design verification board
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MC92604
Dual GEt Design
Verification Board
User's Guide
MC92604DVBUG
Rev. 1, 06/2005

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Summary of Contents for NXP Semiconductors freescale MC92604

  • Page 1 MC92604 Dual GEt Design Verification Board User’s Guide MC92604DVBUG Rev. 1, 06/2005...
  • Page 2 Blank...

  • Page 3: Table Of Contents

    Contents Contents Paragraph Page Number Title Number Chapter 1 General Information Introduction........................1-1 Design Verification Board Features ................. 1-2 Specifications........................1-2 Abbreviation List ......................1-3 Related Documentation....................1-3 Block Diagram ......................... 1-4 Board Components ......................1-5 Contact Information ......................1-5 Chapter 2 Hardware Preparation and Installation Unpacking Instructions ....................
  • Page 4 Paragraph Page Number Title Number Chapter 3 Laboratory Equipment and Quick Setup Evaluation Recommended Laboratory Equipment ................3-1 Quick Setup Data-Eye Diagram ..................3-3 3.2.1 Quick Setup Data-Eye Generation and Observation ........... 3-3 3.2.1.1 Equipment Setup...................... 3-3 3.2.1.2 Parallel Input Connections..................3-4 3.2.1.3 Basic Eye Observation—Test Procedure..............
  • Page 5 Paragraph Page Number Title Number Appendix C Prescaler for Jitter Measurement Divide-by-xx Prescaler Description .................C-1 Prescaler Components......................C-2 Appendix D Revision History MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1 Freescale Semiconductor...
  • Page 6 blank MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1 Freescale Semiconductor...

  • Page 7: General Information

    Chapter 1 General Information Introduction This user’s guide describes the MC92604DVB design verification board for the MC92604 integrated circuit. The design verification board (DVB) facilitates the full evaluation of the MC92604 Dual Gigabit Ethernet transceiver (GEt). It should be read in conjunction with the MC92604 Dual Gigabit Ethernet Transceiver Reference Guide.

  • Page 8: Design Verification Board Features

    General Information Design Verification Board Features The functional, physical, and performance features of the MC92604DVB are as follows: • A single external 5.0-V to onboard regulators supply power to all onboard circuitry. • Reference clock source is a 250-MHz crystal oscillator or an external clock source. •...

  • Page 9: Abbreviation List

    General Information Abbreviation List Table 1-2 contains abbreviations used in this document. Table 1-2. Acronyms and Abbreviated Terms Term Meaning ‘1’ High logic level (nominally 2.5 or 3.3 V) ‘0’ Low logic level (nominally 0.0 V) BIST Built-in self-test Design verification board Interface MDIO Management data input/output port...

  • Page 10: Block Diagram

    General Information Block Diagram 3.3V_CLK_OUT1 X-TAL 3.3V_CLK_OUT2 CLK_IN 3.3V_CLK_OUT3 X-TAL /GND 3.3V_CLK_OUT4 PG14 0.100" Connector MC100 MPC9456 ES6222 R12V TST1 TST2 T3,4 DIFF_CLK_OUT5 +3.3-V DIFF_CLK_OUT6 +5 V Regulator Vertical 50-Ω Test Traces +3.3 V R22V1 TST5 TST6 +2.5- to 3.5-V Regulator R22V RECV_B...

  • Page 11: Board Components

    General Information Board Components Table 1-3 is a list of major components of the MC92604DVB design verification board. A complete parts listing can be found in Appendix B, “Parts List.” Table 1-3. Major Board Components Component Description MC92604ZT Freescale dual gigabit ethernet transceiver SerDes 2 x 10, 0.100"...
  • Page 12 General Information MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1 Freescale Semiconductor...

  • Page 13: Hardware Preparation And Installation

    Chapter 2 Hardware Preparation and Installation This chapter provides unpacking, hardware preparation, configuration-installation instructions, and description of the interface components for the MC92604DVB. Unpacking Instructions Unpack the board from the shipping carton. Refer to the packing list and verify that all items are present. Save the packing material for storing and reshipping of the equipment.

  • Page 14: Hardware Preparation

    Hardware Preparation and Installation Hardware Preparation Operation of the MC92604DVB requires proper setup of the power supply and voltage regulators as well as the reference clock. Figure 2-1 depicts the location of the major components on the board. The following sections describe the proper setup for the MC92604DVB. External Power Diff Clock Buffered Outputs...

  • Page 15: Setting The Power Supply And Voltage Regulators

    Hardware Preparation and Installation 2.3.1 Setting the Power Supply and Voltage Regulators The MC92604DVB requires a single +5.0-V supply. Fully operational, the board will draw a maximum current less than 1.5 amps from the +5.0-V supply. Actual current consumption depends on the user set voltage levels, clock frequencies, use of an SFP module, and the MC92604 operating mode.

  • Page 16: Using The Onboard Oscillators

    Hardware Preparation and Installation 250-MHz Oscillator MC100ES6222 REF_CLK_P CLK_0 REF_CLK_N CLK_1 DIFF_CLK_OUT5 DIV 1/2 DIFF_CLK_OUT6 CSEL MPC9456 CLK_IN DIV by 1 3.3V_CLK_OUT1 3.3V_CLK_OUT2 DIV 1/2 3.3V_CLK_OUT3 3.3V_CLK_OUT4 TTL_REF_CLK DIV 1/2 Figure 2-2. DVB Clock Circuitry 2.4.1 Using the Onboard Oscillators There are two available positions for using onboard oscillators.

  • Page 17: Supplying A Clock To The Mc92604

    Hardware Preparation and Installation 2.4.3 Supplying a Clock to the MC92604 The input reference clock, from either the onboard oscillator or an external source, is applied to a MC100ES6222 clock buffer. This buffer has an input clock select multiplexer, and a programmable divide-by-one/divide-by-two function.

  • Page 18: Interface Components

    Hardware Preparation and Installation Table 2-2. SW1 Settings and Output Frequencies Switch REF_CLK_P, REF_CLK_N, 3.3V_CLK_OUT1, 3.3V_CLK_OUT3, Switch Position DIFF_CLK_OUT5, DIFF_CLK_OUT6 3.3V_CLK_OUT2 3.3V_CLK_OUT4 CLK_IN CLK_IN/2 CLK_IN CLK_IN/2 CLK_IN CLK_IN/2 Figure 2-3 depicts SW1 settings for using an onboard oscillator with the divide-by-two function set for the MC92604 and 3.3V_CLK_OUTn SMA outputs.

  • Page 19: Parallel Inputs

    Hardware Preparation and Installation 2.5.1.1 Parallel Inputs The parallel inputs, both data and control, are accessible via 2 × 10, 0.100" connectors. Figure 2-4 depicts the 2 × 10, 0.100" connector numbering scheme, with pin 1 being labeled on the board. A complete mapping of the MC92604 inputs to the 2 ×...

  • Page 20: Special Application Connections

    Hardware Preparation and Installation During all testing, the serial transmitter outputs should be terminated with 50 Ω . This can be done by connecting the serial transmitter outputs to serial receiver inputs, to any laboratory equipment with 50-Ω input impedance through in-line AC coupling, or by terminating the outputs with 50-Ω SMA terminations. Special Application Connections There are two sets of special connectors provided for application interface evaluation.

  • Page 21: Laboratory Equipment And Quick Setup Evaluation

    Chapter 3 Laboratory Equipment and Quick Setup Evaluation This chapter begins with a listing of recommended test equipment needed to perform complete evaluations on the MC92604. Chapter 4, “Test Setups,” will cover specific setup configurations for this equipment depending on the desired feature under test. Appendix B, “Parts List,”...
  • Page 22 Laboratory Equipment and Quick Setup Evaluation Table 3-2 lists the laboratory accessories. Table 3-2. Lab Accessories • SMA male each end coax patch cords, lengths: various • SMA 3-dB attenuators • SMA 6-db attenuators • SMA DC blockers (AC couplers) •...

  • Page 23: Quick Setup Data-Eye Diagram

    Laboratory Equipment and Quick Setup Evaluation Quick Setup Data-Eye Diagram The MC92604DVB design evaluation kit comes equipped to immediately demonstrate two of the MC92604 functions: • Data-eye signal generation and observation • Bit error rate checking using internal built-in self-test (BIST) features 3.2.1 Quick Setup Data-Eye Generation and Observation A transmitted data-eye can be observed at either of the serial outputs of the MC92604 using its integrated,...

  • Page 24: Parallel Input Connections

    Laboratory Equipment and Quick Setup Evaluation +5 V +5 V +5-V Supply CLK_OUT1 XMIT_P XMIT_N MC92604DVB CH 1 CH 2 Blockers TRIG Blocker Figure 3-1. Data-Eye Observation Setup 3.2.1.2 Parallel Input Connections The basic eye diagram will be generated by biasing the parallel inputs according to Table 3-4.
  • Page 25 Laboratory Equipment and Quick Setup Evaluation Table 3-4. Parallel Input Biasing for Quick Setup Evaluations Bias Bias Bias Signal Signal Signal Level Level Level CTRL_SIG_0 CTRL_SIG_1 CTRL_SIG_2 REPE LBOE BSYNC RCCE USE_DIFF_CLK DROP_SYNC RECV_CLK_CENT MEDIA TST_1 TBIE TST_0 ADIE COMPAT WSYNC1 RESET Jumper...

  • Page 26: Basic Eye Observation-Test Procedure

    Laboratory Equipment and Quick Setup Evaluation Table 3-4. Parallel Input Biasing for Quick Setup Evaluations (continued) Bias Bias Bias Signal Signal Signal Level Level Level SFP_CTRL — — — MOD_DEF_0 MOD_DEF_1 MOD_DEF_2 RATE_SELECT TX_DISABLE 3.2.1.3 Basic Eye Observation—Test Procedure 1. Connect the MC92604DVB and test equipment as described in Figure 3-1 Table 3-4.
  • Page 27 Laboratory Equipment and Quick Setup Evaluation Figure 3-2. MC92604 Data-Eye Using Recommended Test Setup MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1 Freescale Semiconductor...

  • Page 28: Quick Setup Bit Error Rate Checking

    Laboratory Equipment and Quick Setup Evaluation 3.2.2 Quick Setup Bit Error Rate Checking In addition to having an integrated PN generator, the MC92604 also has a bit error rate checker (BERC). An integrated 23rd order signature analyzer, that is synchronized to the incoming PN stream is used to count code group mismatch errors relative to the internal PN reference pattern.

  • Page 29: Quick Setup Berc Test Procedure

    Laboratory Equipment and Quick Setup Evaluation 3.2.2.3 Quick Setup BERC Test Procedure 1. Connect the MC92604DVB and test equipment as described in Section 3.2.2.1, “Equipment Setup.” This will place the MC92604 in PN generation mode with the MC92604 in reset, and set the receivers to BERC mode using the recovered clock.
  • Page 30 Laboratory Equipment and Quick Setup Evaluation RESET RECV_x_RCLK RECVx_ERR RECV_x_DV RECV_x_COMMA Don’t Care Don’t Care Don’t Care Don’t Care Valid Comma Detected RECV_x_7 RECV_x_1 RECV_x_0 MC92604 Not Byte RCVR BIST BIST in Reset Sync Synced Running Running RCVR in PN Analyzer No PN Mismatch 3 PN Mismatches Startup...

  • Page 31: Test Setups

    Chapter 4 Test Setups This chapter outlines the laboratory test equipment setup and procedure to evaluate the features of the MC92604 in more depth than those outlined in the previous chapter. These setups are meant to be guidelines only and are not implied to be complete. Details of testing in specific system applications are left to the user.

  • Page 32: Test Setup For Full-Speed Mode

    Test Setups 4.1.1 Test Setup for Full-Speed Mode Figure 4-1 depicts the test setup for MC92604 in full-speed mode (HSE = ‘0’). The control bits are set as follows: • REPE = ‘1’ • TBIE = ‘1’ All other control bits are set to ‘0,’ except RESET, which is initially set to ‘0,’ then transitioned to ‘1’ to start the MC92604.

  • Page 33: Test Setup For Half-Speed Modes

    Test Setups 4.1.2 Test Setup for Half-Speed Modes Serial link testing may also be performed using half-speed mode (HSE = ‘1’). This reduces all frequencies in the setup by a factor of two. Figure 4-2 depicts the serial link test setup using HSE and a divide-by-10 prescaler.

  • Page 34: Jitter Testing

    Test Setups Jitter Testing The following tests are guidelines for verifying the performance of MC92604 in ‘noisy’ conditions. Results will vary depending on input reference frequencies, MC92604 mode of operation, test setup and equipment, and test environment. 4.2.1 Jitter Test System Calibration Before beginning any type of jitter measurements, the system must first be calibrated, as shown in the configuration in Figure...

  • Page 35: Reference Clock Jitter Transfer Test

    Test Setups 4.2.2 Reference Clock Jitter Transfer Test The test setup shown in Figure 4-4 is used to observe the amount of jitter placed on the reference clock that is transferred to the data outputs. Example frequencies were chosen to match narrow bandpass filters available with the Agilent 71500C jitter analysis system.

  • Page 36: Reference Clock Jitter Tolerance Test

    Test Setups 4.2.3 Reference Clock Jitter Tolerance Test The test setup in Figure 4-5 is used to observe the amount of jitter placed on the reference clock that does not produce errors on the serial data outputs as compared to the input serial data stream. The MC92604 is placed in ten-bit interface mode (TBIE) and repeater mode (REPE).

  • Page 37: Data Jitter Tolerance Test

    Test Setups 4.2.4 Data Jitter Tolerance Test The test setup shown in Figure 4-6 is used to observe the amount of jitter placed on the serial data inputs that does not produce errors on the serial data outputs. The MC92604 is placed in ten-bit interface mode (TBIE) and repeater mode (REPE).
  • Page 38 Test Setups MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1 Freescale Semiconductor...

  • Page 39: Appendix A Connector Signals

    Appendix A Connector Signals The parallel data input and output signals of the MC92604DVB design verification board are listed in the following tables. All the connection test points use the common 2 row 0.100" spaced 3-M type connectors. Input: 2 × 10 (0.100") Connectors The configuration and control inputs to the MC92604 are via 2 row by 10 connectors.
  • Page 40 Connector Signals Table A-2. CTRL_SIG_1 Connector Connector MC92604 Input Signal Description Name LBOE Loopback output enable USE_DIF_CLK Use differential reference clock inputs MEDIA Media impedance select TBIE Ten-bit interface enable COMPAT IEEE Std 802.3 compatibility mode enable JPACK Enable FIFO for jumbo packets RECV_REF_A Use receiver A as primary clock output XMIT_REF_A...

  • Page 41: Transmitter Parallel Data Input Connectors

    Connector Signals A.1.2 Transmitter Parallel Data Input Connectors The MC92604 transmitter parallel data input signals for channels A and B are mapped to the 2 × 10 connectors as listed in the tables below. Table A-4 shows the 8-bit data byte input to transmitter channels A and B, respectively, on A_XMIT and B_XMIT (PG8, PG10) connectors.
  • Page 42 Connector Signals Table A-5 lists the remaining transmitter input signals for the two channels on A_XCLK and B_XCLK (PG9 and PG11) connectors, respectively. Pin 1 of the x_XCLK connector is the buffered reference clock output from the MC92604 PLL that may be used as the input clock for the pattern generator. These signals supply the GTX_CLK reference when interfacing to Ethernet MACs.

  • Page 43: Output: 2 × 20 (0.100") Connectors

    Connector Signals Output: 2 × 20 (0.100") Connectors The MC92604 receiver parallel data outputs are connected to 2 × 20, 0.100" connectors. A mapping of these signals are contained in Table A-6. Table A-6 lists the signals for the A_RECV (LA1) and B_RECV (LA2) connectors. Note that the receive data clock, RECV_x_RCLK, is brought out to two connector pins.

  • Page 44: Jtag Connector

    Connector Signals JTAG Connector Table A-7 lists the signals for the JTAG (PG13) connector. This is the MC92604 test access port, TAP, interface for IEEE Std 1149 JTAG testing. NOTE There are 100-KΩ internal pullups on TMS, TDI, and TRST. If TRST is not held low during power up or does not receive an active low preset after power up, the test logic may assume an indeterminate state disabling some of the normal transceiver functions.

  • Page 45: Mdio Connector

    Connector Signals MDIO Connector Table A-8 lists the signals for the MDIO (PG4) connector. These connections are for the MDIO device address configuration and interface for the MC92604. If MDIO is not being used, the MD_ENABLE pin must be terminated low. See Chapter 4 in the MC92604 Dual Gigabit Ethernet Transceiver Reference Guide, for details.

  • Page 46: Sfp_Ctrl Connector

    Connector Signals SFP_CTRL Connector The control signals for the small form-factor pluggable (SFP) socket are available on the 2 row by 8, SFP_CTRL (PG12) connector as listed in Table A-9. These are standard signals for the multiple source agreement (MSA) fiber optic modules. The TX_DISABLE pin must be low for the module to operate. Table A-9.

  • Page 47: Appendix B Parts List

    Appendix B Parts List Design Verification Board Parts List Table B-1 shows the parts used in constructing the MC92604DVB design verification board. Table B-1. MC92604DVB Design Verification Board Parts List (Sheet 1 of 3) Item Qty. Reference Value Manufacturer Part No. Description Molex Inc.
  • Page 48 Parts List Table B-1. MC92604DVB Design Verification Board Parts List (Sheet 2 of 3) Item Qty. Reference Value Manufacturer Part No. Description 2 × 20 keyed header with shroud, LA1–2 2540-6002UB 0.1" pin spacing, low profile 1 µH IND-MOLDED, 1 µH Inductor-molded, 1 µH L1–2 VR1 VR18 VR33 Linear...
  • Page 49 Parts List Table B-1. MC92604DVB Design Verification Board Parts List (Sheet 3 of 3) Item Qty. Reference Value Manufacturer Part No. Description 1394B_A_N Johnson SMA 50-Ω RF PCB jack socket 1394B_A_P 1394B_B_N 1394B_B_P CLK_A_PG CLK_B_PG CLK_IN CLK_OUT1–4 DIFF_CLK_OUT5–6 RX_A_N RX_A_P RX_B_N RX_B_P SFP_RX_N SFP_RX_P...
  • Page 50 Parts List MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1 Freescale Semiconductor...
  • Page 51 Appendix C Prescaler for Jitter Measurement Divide-by-xx Prescaler Description Evaluating jitter in a system requires that all clocks within the system be based on one common source. For this reason, it is often necessary to use prescalers to derive the needed reference clock. Freescale has developed a small programmable prescaler with a maximum input frequency of 4.4 GHz which can be assembled using commercially available parts.
  • Page 52 Prescaler for Jitter Measurement Prescaler Components Table C-2 lists the major integrated circuit components needed for the prescaler. Table C-2. Major Components for Divide-by-xx Prescaler Part No. Manufacturer Supplier Comments MC12093 Freescale Newark 1.1-GHz prescaler (divide by 2, 4, or 8) MC100ELT23 On Semiconductor Newark...
  • Page 53 Appendix D Revision History This appendix provides a list of the major differences between revisions of the MC92604 Dual GEt Design Verification Board User’s Guide (MC92604DVBUM). Table D-1 provides a revision history for this document. Table D-1. MC92604DVB Revision History Rev.
  • Page 54 Revision History MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1 Freescale Semiconductor...
  • Page 55 Back Cover...
  • Page 56 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Information in this document is provided solely to enable system and software Technical Information Center implementers to use Freescale Semiconductor products.

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