Monitoring Pid Control Status (Qnacpu Only) - Mitsubishi Electric MELSEC-Q series Programming Manual

Monitoring PID control status (QnACPU only)

Applicable CPU
QCPU
Programmable controller CPU
Basic High Performance
 
[SET DATA]
■Description and data type
Set Data
(n)
S1
S2
■Usable device
Set Data Usable Devices
Internal Devices
(System, User)
Bit

(n)

S1

S2
[FUNCTION]
• The display unit of the AD57(S1) designated by (n) displays the PID control status of the loop number designated by
a bar graph. By executing the initial screen display request, designated by
monitor screen (with the exception of bar graphs and numerical data) are displayed in the initial state of PID control
monitoring.
• Addresses 0 to 1599 in the VRAM area of the AD57(S1) are used for the PID control monitor. Therefore, these addresses
cannot be used by the user if PID control status monitoring is executed; if they are, the data stored in them will be lost.
• Execute the CMODE instruction (AD57 command) to monitor the PID control status before executing the PID57 instruction.
If the CRT standard display mode, set with the CMODE instruction, has not been set for the AD57(S1), the display unit will
not be able to display anything.
• Execute the PID57 instruction only after the PIDINIT(P) and PIDCONT(P) instructions have been executed. An error will
occur if the PID57 instruction is executed before the PIDINIT(P) and PIDCONT(P) instructions.
• Designate the loop number indicated by
Screen Number
1
2
3
4
9 COMPLETE DERIVATIVE PID CONTROL INSTRUCTIONS AND PROGRAM EXAMPLES
76
9.1 PID Control Instructions
Universal

Description
First I/O number of the AD57(S1) used to monitor the PID control status
Screen number corresponding to the loop number to be monitored
Initial screen display request
File Register
Word
with a screen number from "1" to "4", as shown below:
S1
Process CPU

MELSECNET/10 (H) Special
Direct J\ Function
Module
Bit Word
U\G
Loop Numbers to be Monitored
Loop 1 to loop 8
Loop 9 to loop 16
Loop 17 to loop 24
Loop 25 to loop 32
LCPU
Redundant CPU
 
Data Type
16-bit binary
Index
Register Zn
, the characters in the still portion of the
S2
QnA Q4AR
 
Constant Other
K, H
 
 
 
in
S1