SanDisk CompactFlash Extreme III Product Manual page 52

ATA Register Set and Protocol
Device Control Register (con't)
Bit
D7
D6
D5
D4
D3
D2
D1
D0
4.5.11 Card (Drive) Address Register (Address–3F7[377]; Offset Fh)
This register is provided for compatibility with the AT disk drive interface. It is recommended
that this register not be mapped into the host's I/O space because of potential conflicts on Bit 7.
The bits are defined as follows:
D7
X
02/07, Rev. 12.0
Name
X Don't care.
X Don't care.
X Don't care.
X Don't care.
1 Bit ignored by the card.
SW Rst Set to 1 in order to force the card to perform an AT Disk controller Soft
Reset operation. This does not change the PCMCIA Card Configuration
registers as a hardware reset does. The card remains in Reset until this bit
is reset to "0".
-IEn Interrupt Enable bit enables interrupts when the bit is 0. When the bit is 1,
interrupts from the card are disabled. This bit also controls the Int bit in the
Configuration and Status Register. This bit is set to 0 at power on and
reset.
ERR Bit ignored by the card.
D6 D5 D4
-WTG -HS3 -HS2
4-8
SanDisk CompactFlash Card OEM Product Manual
Description
D3 D2 D1
-HS1 -HS0 -nDS1
© 2007 SanDisk Corporation
D0
-nDS0