SanDisk CompactFlash Extreme III Product Manual page 36

Interface Description
Figure 3-7 Register Transfer to/from Device
1:
NOTE
2:
NOTE
Table 3-15
a
t
0
t
1
a
t
2
a
t
2i
t
3
t
4
t
5
t
6
b
t
6z
t
9
a. t is the minimum total cycle time, t
0
command recovery time or command inactive time. The actual cycle time equals the sum of the
actual command active time and the actual command inactive time. The three timing requirements
of t , t
0
t and t
2
equal to or greater than the value reported in the devices IDENTIFY DEVICE data. A device imple ­
mentation shall support any legal host implementation.
b. This parameter specifies the time from the negation edge of /IORD to the time that the data bus is
no longer driven by the device (tri-state).
02/07, Rev. 12.0
Device address consists of signals -CS0, -CS1 and -DA(2:0).
Data consists of DD(7:0).
Register Transfer to/from Device
PIO Timing Parameters
Cycle time (min.)
Address valid to IORD-/IOWR- setup (min.)
IORD-/IOWR- pulse width 8-bit (min.)
IORD-/IOWR- recovery time (min.)
IOWR- data setup (min.)
IOWR- data hold (min.)
IORD- data setup (min.)
IORD- data hold (min.)
IORD- data tri-state (max.)
IORD-/IOWR- to address valid hold (min.)
is the minimum command active time, and t
2
, and t shall be met. The minimum total cycle time requirements are greater than the sum of
2 2i
. This means a host implementation may lengthen either or both t
2i
3-18
SanDisk CompactFlash Card OEM Product Manual
or t
2
© 2007 SanDisk Corporation
Mode 4 (ns)
120
25
70
25
20
10
20
5
30
10
is the minimum
2i
to ensure that t is
2i 0