Mcu - ZiLOG ZNEO Z16F Series User Manual

ZNEO CPU based devices also provide an external interface that allows
seamless connection to external memory and/or peripherals. External
memory can be non-volatile memory such as Flash, or RAM, or both.
External non-volatile memory is used to store program code or constant
data, while external RAM is available primarily for non-constant data.
The external interface supports multiple chip select signals (CSx), which
are asserted by the CPU when an access to external memory is requested.
These signals are used to access distinct ranges and devices in external
memory. The boundaries between memory ranges selected by the chip
select signals are at fixed addresses, and, in some cases, the ranges
covered by chip selects might overlap. For example, there might be some
addresses in the range of both the CS0 and CS1 signals. In this case, the
ZNEO CPU uses a chip select priority scheme. It asserts only a single
chip select with the highest priority among those that contain the
addresses to be accessed, with CS0 having the lowest priority and CS5 the
highest. Also, the chip selects can be individually enabled or disabled.
On-chip memory has greater priority over external memory. CS0 starts at
address
start at addresses
ZNEO
product specification.

MCU

The ZNEO Z16F Series Flash microcontrollers are based on Zilog's
advanced ZNEO 16-bit CPU core. The ZNEO Z16F Series MCU family
of devices sets a new standard of performance and efficiency with a 24-bit
address bus and 16-bit data bus.
The ZNEO Z16F Series External Interface allows seamless connection to
external memory and peripherals. A 24-bit address bus and selectable
8-bit or 16-bit data bus allows parallel access up to 16 MB.
UM020205-0908
, and CS1 starts at address
00_0000H
F0_0000H
®
CPU Core User Manual (UM0188) and the individual device
®
ZNEO Z16F Series Development Kit
80_0000H
and beyond. For more information, refer to
ZNEO Z16F Series Development Board
User Manual
7
. CS2 to CS5