Raisecom RC852-30-FV35 User Manual page 16

rd
2. The 3 bit: Timeslot auto follow function TS_FLOW (default OFF)
ON
OFF
To make local timeslot follow remote timeslot, below four conditions should be ensured:
(1) RC85x series device is used point to point in pair.
(2) There is no any equipment could stop Sa4 bits transmission in Timeslot 0.
(3) Enable this function only in slave clock timing mode.
When all of above condition is satisfied, set the SW5-3 of local device as ON to open timeslot
auto-follow function, the timeslot and frame mode (PCM30/PCM31) of local device will follow the
configurations of remote device automatically.
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3. The 4 bit: Build-in Bit Error Tester function BERT (default OFF)
There is an Bit Error Tester Unit inside this series device, and the main purpose of this unit is that
produces testing pattern 2E15-1 std and sends them to optical line. This pattern can be uploaded
to proper data channel through configuration, then via many loop back mode the returned
sequence is sent to device for testing. The testing result will be displayed by the PAT indicator on
front panel. When bit error is captured the PAT indicator turns to off and keep for at least one
second. If there is no new error occur the PAT indicator will come back to steady yellow status.
The device will add test pattern to user data channel after the test function is running. This
function is available in fractional E1 mode and unframed (transparent) E1 mode, at that time all
the V.35 data will be interrupted.
Notice: The bit error test function can be operated with many loop back test. When the local
ALOOP loopback function is disable the loop back can be realized by external fiber patch cord,
but the dual-fiber S3 and all single fiber are forbidden. At the time when PAT indicator is steady
yellow it indicates that correct bits was received. If the RLOOP remote loop back is enabled
accompanied with bit error test, it means the whole information process will be tested.
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4. The 5 bit: RX CLK Phase (default OFF)
The RX CLK phase choosing is provided according to the different V.35 clock and data phase of
different brand router. On Cisco series router the test result of V.35 synchronization WAN
interface is passing when this device is connected and its RX CLK is Positive.
RX CLK is Positive: Data will be sent to RD signal during RX CLK falling edge.
RX CLK
RD
RX CLK is Reverse: Data will be sent to RD signal during RX CLK rising edge.
RX CLK
RD
SW5-3 Timeslot auto follow function
Enable
Disable
SW5-4 Build in Bit Error Tester
ON
OFF
SW5-5 Phase Choosing
ON RX CLK Reverse Phase
OFF RX CLK Positive Phase
Enable
Disable
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