Raisecom RC852-30-FV35 User Manual page 15

SW1~SW4: Time-slots configuration of E1 data in fiber
"√" indicates enable; "×" indicates disable
SW1 definition (default is all OFF)
1st bit
SET Frame Status
ON Fractional
OFF Unframed
SW2 definition (default is all OFF)
1st bit
SET TS8
ON √
OFF ×
SW3 definition (default is all OFF)
1st bit
SET TS16
ON √
OFF ×
SW4 definition (default is all OFF)
1st bit
SET TS24
ON √
OFF ×
Notice:
When the SW1-1 is OFF (unframed mode) the TS1 to TS31 is invalid.
When the SW1-1 is ON( Fractional mode) the TS1 to TS31 is valid and can not be all OFF. That is to
say there must be some timeslot is enabled.
SW5: Function selection
SW5 definition (default is all OFF)
1st bit
Define
Clock
Timing 1
ON √
OFF ×
st nd
1. The 1 and 2
The Clock mode of device is defined by the 1
table:
SW5-1
OFF
OFF
ON
ON
2nd bit 3rd bit
TS1 TS2
√ √
× ×
2nd bit 3rd bit
TS9 TS10
√ √
× ×
2nd bit 3rd bit
TS17 TS18
√ √
× ×
2nd bit 3rd bit
TS25 TS26
√ √
× ×
2nd bit 3rd bit
Clock TS_FLOW
Timing 2
√ √
× ×
bit: Clock Timing mode Selection(default are ON)
SW5-2
OFF Master Clock (Internal clock)
ON V.35 terminal Clock ( External -
Follow V.35 input clock)
OFF
ON Slave Clock ( Follow fiber line clock)
4th bit 5th bit 6th bit
TS3 TS4 TS5
√ √ √
× × ×
4th bit 5th bit 6th bit
TS11 TS12 TS13
√ √ √
× × ×
4th bit 5th bit 6th bit
TS19 TS20 TS21
√ √ √
× × ×
4th bit 5th bit 6th bit
TS27 TS28 TS29
√ √ √
× × ×
4th bit 5th 6th bit
bit
BERT RX ALOOP DLOOP RLOOP
CLK
phase
√ √ √
× × ×
st nd
bit and 2 bit of SW5, detail is shown in below
Clock Mode
7th bit 8th bit
TS6 TS7
√ √
× ×
7th bit 8th bit
TS14 TS15
√ √
× ×
7th bit 8th bit
TS22 TS23
√ √
× ×
7th bit 8th bit
TS30 TS31
√ √
× ×
7th bit 8th bit
√ √
× ×
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