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Mode 0: Common Stop,
Single Word Mode
Control Registers
15
14
13
12
11
10
Mode
15
14
13
12
11
10
Serial number
Trig. clock
FERA Mode
unit
15
14
13
12
11
10
15
14
13
12
11
10
Mode 0 Control Registers
control register 0 (subaddress 0)
bits 0-7
user definable module ID code. This appears in the
header data word. Default is 0.
bits 8-9
data shift value. This determines the TDC resolution.
0 = 0.5 nsec (default)
1 = 1.0 nsec
2 = 2.0 nsec
3 = 4.0 nsec
bit 10
Selects LEADING edge recording, or BOTH edges.
1 = Both edges are recorded
0 = Leading edge ONLY is recorded (default)
bit 11
Selects readout mode.
1 = ECL PORT (FERA mode)
0 = CAMAC readout (default)
bit 12
Selects Buffer mode
1 = Multi-event buffer mode
0 = Single buffer mode. In this mode the FERA
readout is compatible with the 4300B FERA
ADC. The request delay (see register 3) must
be set appropriately. (default)
bit 13
Selects Header mode
0 = always have header (default)
1 = skip header if no data words
Control Register #0
9
8
7
6
5
4
Data Shift Value
User settable ID Code
Edge Recording
Readout Mode
Buffer Mode
Header Mode
Control Register #1
9
8
7
6
5
4
Trigger pulse
MPI
delay
Control Register #2
9
8
7
6
5
4
Max. full scale time
Control Register #3
9
8
7
6
5
4
Offset
3
2
1
0
3
2
1
0
Trigger Pulse Width
3
2
1
0
Max. # Hits
3
2
1
0
Request delay
21
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