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Signal Inputs
ECLbus output
REAR PANEL
STANDARD CAMAC
FUNCTION CODES
16
Two 34 pin headers are for hit inputs; marked IN. The channels are
arranged sequentially from channel 0 at the top to channel 15 and
channel 16 to channel 31. The bottom pins (33,34) on both headers are
grounded through 100 ohm resistors. The hit inputs are dECL, polarity is
such that a positive going edge on the left hand (odd numbered) pin is
interpreted as the leading edge.
The bottom header is the ECLbus output port; marked ECL OUT. This
header is used for the FERA compatible readout.
Located on the back of the unit is a twenty pin header which is the
trigger output for the unit. This connector is inverted so pin one is at the
bottom. The pins are grouped in pairs, with the bottom pair being the
first (pins 1 and 2).
Pair
1 (1,2)
2 (3,4)
3 (5,6)
4 (7,8)
5 (9,10)
6 (11,12)
7 (13,14)
8 (15,16)
9 (pins 17,18)
10 (pins 19,20)
F0, A0
Read FIFO data until end of event, Q=1 for valid data,
Q=0 at end
F0, A1
Read FIFO data always, (common start only)
F0, A2
Examine FIFO output, do not advance FIFO (common
start only)
F1, A0
Read Control register 0
F1, A1
Read Control register 1
F1, A2
Read Control register 2
F1, A3
Read Control register 3
F1, A4
Read Control register 4 (common start only)
F1, A5
Read Control register 5 (common start only)
F1, A6
Read CAMAC Test Register (common start only)
F8, A0
Test LAM
F9, A0
Clear all data and LAM. This does NOT affect the
control registers
F10, A0
Clear LAM
F16, A0
Write 16 bit data to FIFO (common start only)
F16, A1
Write FIFO tag bit (common start only)
F17, A0
Write Control register 0
F17, A1
Write Control register 1
F17, A2
Write Control register 2
Function
Trigger output 1, ch 0-3
Trigger output 2, ch 4-7
Trigger output 3, ch 8-11
Trigger output 4, ch 12-15
Trigger output 5, ch 16-19
Trigger output 6, ch 20-23
Trigger output 7, ch 24-27
Trigger output 8, ch 28-31
Output disable (enabled when open)
External trigger clock input
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