A/D Convert Signal; A/D Pacer Gate Signal - Measurement Computing PCI-DAS6034 User Manual

PCI-DAS6034 & PCI-DAS6035 User's Guide

4.2.6 A/D CONVERT Signal

The A/D CONVERT signal indicates the start of an A/D conversion. It is available through
software selection as an input to any of the AUXIN pins (defaulting to AUXIN0) or the DAQ-
Sync "DS A/D CONVERT" input and as an output to any of the AUXOUT pins.
When used as an input, the polarity is software selectable. The A/D CONVERT signal starts
an acquisition on the selected edge. The convert pulses must be separated by a minimum of 5
µs to remain within the 200 kS/s conversion rate specification.
Refer back to Figures 4-3 and 4-6 for the relationship of A/D CONVERT to the DAQ
sequence. Figures 4-11 and 4-12 show the input and output pulse width requirements for the
A/D CONVERT signal.
Figure 4-11. A/D CONVERT Signal Input Timing Requirement
Figure 4-12. A/D CONVERT Signal Output Timing Requirement
The A/D CONVERT signal is generated by the on-board pacer circuit unless the external
clock option is in use. This signal may be gated by hardware (A/D PACER GATE) or
software.

4.2.7 A/D PACER GATE Signal

The A/D PACER GATE signal is used to disable scans temporarily. This signal may be
programmed for input at any of the AUXIN pins.
If the A/D PACER GATE signal is active, no scans can occur. If the A/D PACER GATE
signal becomes active during a scan in progress, the current scan is completed and scans are
then held off until the gate is de-asserted.
t = 37.5 ns minimum
w
4–9
Functional Description