Daq Signal Timing; Scanclk Signal - Measurement Computing PCI-DAS6034 User Manual

PCI-DAS6034 & PCI-DAS6035 User's Guide
4.2

DAQ Signal Timing

The primary DAQ timing signals are:
• SCANCLK
• SSH
• A/D START TRIGGER
• A/D STOP TRIGGER
• STARTSCAN
• A/D CONVERT
• A/D PACER GATE

4.2.1 SCANCLK Signal

SCANCLK is an output signal that may be used for switching external multiplexers. It is a
400ns wide pulse that follows the CONVERT signal after a 50ns delay. This is adequate time
for the analog input signal to be acquired so that the next signal may be switched in. The
polarity of the SCANCLK signal is programmable. The default output pin for the SCANCLK
signal is AUXOUT2, but any of the AUXOUT pins may be programmed as a SCANCLK
output.
Figure 4-2. SCANCLK Signal Timing
4–5
Functional Description