Automation Direct CTT-1C-D24 Manual page 193

CTT Timer + Counter Mixed Mode Functions
Timer Mode - Signal Off Delay ( Soffd )
Counter Input Mode - Down ( down )
Timer+Counter Mixed Mode
Timer + Counter Mixed Mode
In Timer + Counter Mixed Mode, timer period setting value SV1 controls Output 1 and counter setting value SV2
controls Output 2. Output 1(Timer) will turn ON momentarily for the time set in the output pulse width param-
eter ( tout1 ) or will be maintained ON ( tout1 set to 0.00). Output 2 (Counter) will turn ON momentarily for
the time set in the output pulse width parameter (tout2) or will be maintained ON depending on the output mode
selected.
Signal Off Delay ( Soffd )
With power applied to the CTT, the leading edge of an input signal at
START will immediately turn ON the Output 1. The trailing edge of the
"start" signal will begin the timing period setting value SV1 timing up
or down based on parameter ( t modE ). At the end of the timing period
Output 1 will turn OFF. The leading edge of a "start" signal applied
during a previously initiated timing period will reset the timing period.
The leading edge of a "reset" input signal at RST1 will turn OFF Output
1, reset the timing period and prohibit the start of a new timing period.
The "reset" signal minimum pulse width is set by reset pulse width param-
eter ( rtSr ).
The leading edge of an "pause" input signal at GATE will pause the
timing period after it has been started. The timing period will continue
after the trailing edge of the "pause" (Gate) signal.
When power is removed, both outputs will turn OFF and the timing
period will be reset.
Counter Input Mode:
Counter Input Mode - Counting Down ( down )
Each leading edge of the input signal at CP1 will decrement the count present value PV by 1.
Counter Output Modes:
Mode F ( F )
When the count present value PV counts down to 0, Output 2
will turn ON. The count PV will continue to decrement with
each input signal.
The leading edge of a "reset" input signal at RST1 will turn
Output 2 OFF, reset the count PV to the count setting value
SV2, and prohibit an input signal from decrementing the count
PV. The trailing edge of the "reset" signal at RST1 enables
counting to begin.
The "reset" signal minimum pulse width is set by reset pulse
width parameter ( rtSr ).
4-28
Digital Counter / Timer / Tach User Manual, 1st Ed.
Power signal
Start signal
Pause signal
Reset
Output signal
SV
Up
0
SV
Down
0
Signal Off Delay
RESET
999999
COUNT SV 2
COUNT PV
0
OUT2
TIMER + COUNTER
Counter Input Mode DOWN
Counter Output Mode F
1 - 8 0 0 - 6 3 3 - 0 4 0 5