Timing - JDS Uniphase SKB SERIES User Manual

Timing

The SKB switch uses bidirectional parallel lines for the data bus (D0 to D7) and dedicated
input/output lines for flow control. Data flow control is implemented on a byte-by-byte basis, using
the BUSY output line of the SKB switch as the primary mechanism of controlling the data transfer
rate. By using control signals, the actual signal timing can vary (within defined tolerances)
according to the availability of the SKB switch, which is indicated with a low-level BUSY signal.
The primary control signals of the master are the /SOP and /STROBE lines. Transitions of the
/SOP line are used to delimit the beginning and end of packets. The /STROBE line is used to
signal the SKB switch to either read bytes from the data lines or write bytes to the data lines.
Timing dependencies have been minimized, allowing use of control signals to regulate
communication. However, the following timing requirements must be observed:
•
A hold time of 5 µs must be applied when toggling SKB input lines (for example, R/W, D0-D7,
/SOP, /STROBE, /RESET).
•
The maximum period between sequential bytes (indicated by transitions of the /STROBE line)
is 500 ms.
The following general rules apply:
•
The master needs to ensure that the BUSY line is de-asserted (low) before toggling any
parallel communication lines (for example, /SOP, /STROBE, and so on).
•
Communication lines must be toggled according to the steps indicated in the protocol flow
charts for read and write operations. Poll the error line following each operation.
The read cycle protocol is illustrated in Figure 15. Typical line toggling for a master read cycle is
shown. The figure shows the relationship of the R/W, /SOP, and /STROBE input lines and the
BUSY output line during a three-byte response packet read from the SKB switch.
Figure 15: Three-Byte Response Packet Read from the SKB Switch
Operating and Maintenance Instructions – 27