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Freescale Semiconductor
Application Note
Qorivva MPC5643L Dual
Processor Mode
by: Mark Ruthenbeck
Applications Engineering
Microcontroller Solutions Group
1
Scope
This paper is a brief tutorial and description on how to
select and run the MPC5643L in decoupled parallel
mode (DPM).
2
Reference material
Freescale document MPC5643LRM, MPC5643L
Microcontroller Reference Manual, Rev. 7, October
2010.
3
Overview
The paper reviews the dual core modes of the
MPC5643L, but focuses on the operation of the
decoupled parallel mode (DP mode or DPM) on the chip
and on how to enable the DPM.
The MPC5643L operates in both lock step mode and
DPM - this paper will focus on the DPM mode.
© Freescale Semiconductor, Inc., 2011. All rights reserved.
Document Number: AN4034
Contents
1
Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2
Reference material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4
MPC5643L dual core architecture . . . . . . . . . . . . . . . . . . 2
4.1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
4.2
Sphere of replication . . . . . . . . . . . . . . . . . . . . . . . . 3
4.3
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5
Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.1
Hardware setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.2
Software setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.3
Basic dual core flash boot program flow . . . . . . . . . 5
6
Changing between LSM and DPM . . . . . . . . . . . . . . . . . 7
6.1
Configure the flash programming utility . . . . . . . . . . 7
6.2
Dump shadow flash to s-record file . . . . . . . . . . . . . 8
6.3
8
6.4
tion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.5
Verify new configuration . . . . . . . . . . . . . . . . . . . . . 9
7
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Rev. 0, 03/2011
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Page 1: Table Of Contents
Freescale Semiconductor Document Number: AN4034 Rev. 0, 03/2011 Application Note Qorivva MPC5643L Dual Processor Mode by: Mark Ruthenbeck Applications Engineering Microcontroller Solutions Group Scope Contents Scope ........1 This paper is a brief tutorial and description on how to Reference material . -
Page 2: Mpc5643L Dual Core Architecture
This replication is one of the features that enables this chip to be used in a safety environment. In a dual core mode, this replication adds a bit of additional programming for full operation. Qorivva MPC5643L Dual Processor Mode, Rev. 0 Freescale Semiconductor... -
Page 3: Block Diagram
However, if the system is in dual processor mode, these same peripherals have unique addresses. On core(0) the SoR peripherals remain at the LSM addresses, and the core(1) SoR peripherals are now visible at a different set of addresses. Qorivva MPC5643L Dual Processor Mode, Rev. 0 Freescale Semiconductor... -
Page 4: Startup
The System Status and Configuration Module (SSCM) is the control module for making the second core operational. The registers of interest are: • DPM Boot Register: Base + 0x0018 • Boot Key Register: Base + 0x001C Qorivva MPC5643L Dual Processor Mode, Rev. 0 Freescale Semiconductor... -
Page 5: Basic Dual Core Flash Boot Program Flow
One point to remember is that an NMI is generated to both cores and this interrupt must be serviced properly before the system runs both cores. The diagram below shows a simplified boot process. Qorivva MPC5643L Dual Processor Mode, Rev. 0 Freescale Semiconductor... - Page 6 Core(1) changes the device mode from Core(0) is now operational. DRUN to RUN0 FCCU Triggers NMI for both cores Both cores manage their own NMI Branch to Main() Core(1) now operational Qorivva MPC5643L Dual Processor Mode, Rev. 0 Freescale Semiconductor...
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Page 7: Changing Between Lsm And Dpm
2. Ensure the MPC5643L is powered on and the USB Multilink is connected between the EVB and the PC. 3. Select the Connect (Reset) to connect to the MPC5643L as shown in Figure Qorivva MPC5643L Dual Processor Mode, Rev. 0 Freescale Semiconductor... -
Page 8: Dump Shadow Flash To S-Record File
Zero to sixty-four pairs of hexadecimal characters specifying the data bytes • Two hex digits indicating the checksum, which is calculated by taking the sum of the all the bytes Qorivva MPC5643L Dual Processor Mode, Rev. 0 Freescale Semiconductor... -
Page 9: Program Shadow Flash With Updated User Configuration
2. Launch the P&E debugger from ...\pemicro\cw_icdppcnexus.exe and connect to the MPC5643L. 3. The status window shows the operating mode. Verify that the new mode is detected as shown in Figure Qorivva MPC5643L Dual Processor Mode, Rev. 0 Freescale Semiconductor... -
Page 10: Summary
Add SafeAssure branding. Add Qorivva branding. Back page Apply new back page format. No substantive changes were made to the content of this document; therefore the revision number was not incremented. Qorivva MPC5643L Dual Processor Mode, Rev. 0 Freescale Semiconductor... - Page 11 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright Home Page: licenses granted hereunder to design or fabricate any integrated circuits based on the freescale.com information in this document.
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